2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.24"
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR
= 0, /* offset 0x10: memory space */
43 MV_IO_BAR
= 2, /* offset 0x18: IO space */
44 MV_MISC_BAR
= 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46 MV_MAJOR_REG_AREA_SZ
= 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ
= 0x2000, /* 8KB */
50 MV_IRQ_COAL_REG_BASE
= 0x18000, /* 6xxx part only */
51 MV_SATAHC0_REG_BASE
= 0x20000,
53 MV_PCI_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
54 MV_SATAHC_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
55 MV_SATAHC_ARBTR_REG_SZ
= MV_MINOR_REG_AREA_SZ
, /* arbiter */
56 MV_PORT_REG_SZ
= MV_MINOR_REG_AREA_SZ
,
58 MV_USE_Q_DEPTH
= ATA_DEF_QUEUE
,
61 MV_MAX_Q_DEPTH_MASK
= MV_MAX_Q_DEPTH
- 1,
63 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
64 * CRPB needs alignment on a 256B boundary. Size == 256B
65 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
66 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
68 MV_CRQB_Q_SZ
= (32 * MV_MAX_Q_DEPTH
),
69 MV_CRPB_Q_SZ
= (8 * MV_MAX_Q_DEPTH
),
71 MV_SG_TBL_SZ
= (16 * MV_MAX_SG_CT
),
72 MV_PORT_PRIV_DMA_SZ
= (MV_CRQB_Q_SZ
+ MV_CRPB_Q_SZ
+ MV_SG_TBL_SZ
),
74 /* Our DMA boundary is determined by an ePRD being unable to handle
75 * anything larger than 64KB
77 MV_DMA_BOUNDARY
= 0xffffU
,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
86 MV_FLAG_DUAL_HC
= (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE
= (1 << 29), /* IRQ coalescing capability */
88 MV_FLAG_GLBL_SFT_RST
= (1 << 28), /* Global Soft Reset support */
89 MV_COMMON_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
90 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
),
91 MV_6XXX_FLAGS
= (MV_FLAG_IRQ_COALESCE
|
92 MV_FLAG_GLBL_SFT_RST
),
99 CRQB_FLAG_READ
= (1 << 0),
101 CRQB_CMD_ADDR_SHIFT
= 8,
102 CRQB_CMD_CS
= (0x2 << 11),
103 CRQB_CMD_LAST
= (1 << 15),
105 CRPB_FLAG_STATUS_SHIFT
= 8,
107 EPRD_FLAG_END_OF_TBL
= (1 << 31),
109 /* PCI interface registers */
111 PCI_COMMAND_OFS
= 0xc00,
113 PCI_MAIN_CMD_STS_OFS
= 0xd30,
114 STOP_PCI_MASTER
= (1 << 2),
115 PCI_MASTER_EMPTY
= (1 << 3),
116 GLOB_SFT_RST
= (1 << 4),
118 PCI_IRQ_CAUSE_OFS
= 0x1d58,
119 PCI_IRQ_MASK_OFS
= 0x1d5c,
120 PCI_UNMASK_ALL_IRQS
= 0x7fffff, /* bits 22-0 */
122 HC_MAIN_IRQ_CAUSE_OFS
= 0x1d60,
123 HC_MAIN_IRQ_MASK_OFS
= 0x1d64,
124 PORT0_ERR
= (1 << 0), /* shift by port # */
125 PORT0_DONE
= (1 << 1), /* shift by port # */
126 HC0_IRQ_PEND
= 0x1ff, /* bits 0-8 = HC0's ports */
127 HC_SHIFT
= 9, /* bits 9-17 = HC1's ports */
129 TRAN_LO_DONE
= (1 << 19), /* 6xxx: IRQ coalescing */
130 TRAN_HI_DONE
= (1 << 20), /* 6xxx: IRQ coalescing */
131 PORTS_0_7_COAL_DONE
= (1 << 21), /* 6xxx: IRQ coalescing */
132 GPIO_INT
= (1 << 22),
133 SELF_INT
= (1 << 23),
134 TWSI_INT
= (1 << 24),
135 HC_MAIN_RSVD
= (0x7f << 25), /* bits 31-25 */
136 HC_MAIN_MASKED_IRQS
= (TRAN_LO_DONE
| TRAN_HI_DONE
|
137 PORTS_0_7_COAL_DONE
| GPIO_INT
| TWSI_INT
|
140 /* SATAHC registers */
143 HC_IRQ_CAUSE_OFS
= 0x14,
144 CRPB_DMA_DONE
= (1 << 0), /* shift by port # */
145 HC_IRQ_COAL
= (1 << 4), /* IRQ coalescing */
146 DEV_IRQ
= (1 << 8), /* shift by port # */
148 /* Shadow block registers */
150 SHD_CTL_AST_OFS
= 0x20, /* ofs from SHD_BLK_OFS */
153 SATA_STATUS_OFS
= 0x300, /* ctrl, err regs follow status */
154 SATA_ACTIVE_OFS
= 0x350,
158 EDMA_CFG_Q_DEPTH
= 0, /* queueing disabled */
159 EDMA_CFG_NCQ
= (1 << 5),
160 EDMA_CFG_NCQ_GO_ON_ERR
= (1 << 14), /* continue on error */
161 EDMA_CFG_RD_BRST_EXT
= (1 << 11), /* read burst 512B */
162 EDMA_CFG_WR_BUFF_LEN
= (1 << 13), /* write buffer 512B */
164 EDMA_ERR_IRQ_CAUSE_OFS
= 0x8,
165 EDMA_ERR_IRQ_MASK_OFS
= 0xc,
166 EDMA_ERR_D_PAR
= (1 << 0),
167 EDMA_ERR_PRD_PAR
= (1 << 1),
168 EDMA_ERR_DEV
= (1 << 2),
169 EDMA_ERR_DEV_DCON
= (1 << 3),
170 EDMA_ERR_DEV_CON
= (1 << 4),
171 EDMA_ERR_SERR
= (1 << 5),
172 EDMA_ERR_SELF_DIS
= (1 << 7),
173 EDMA_ERR_BIST_ASYNC
= (1 << 8),
174 EDMA_ERR_CRBQ_PAR
= (1 << 9),
175 EDMA_ERR_CRPB_PAR
= (1 << 10),
176 EDMA_ERR_INTRL_PAR
= (1 << 11),
177 EDMA_ERR_IORDY
= (1 << 12),
178 EDMA_ERR_LNK_CTRL_RX
= (0xf << 13),
179 EDMA_ERR_LNK_CTRL_RX_2
= (1 << 15),
180 EDMA_ERR_LNK_DATA_RX
= (0xf << 17),
181 EDMA_ERR_LNK_CTRL_TX
= (0x1f << 21),
182 EDMA_ERR_LNK_DATA_TX
= (0x1f << 26),
183 EDMA_ERR_TRANS_PROTO
= (1 << 31),
184 EDMA_ERR_FATAL
= (EDMA_ERR_D_PAR
| EDMA_ERR_PRD_PAR
|
185 EDMA_ERR_DEV_DCON
| EDMA_ERR_CRBQ_PAR
|
186 EDMA_ERR_CRPB_PAR
| EDMA_ERR_INTRL_PAR
|
187 EDMA_ERR_IORDY
| EDMA_ERR_LNK_CTRL_RX_2
|
188 EDMA_ERR_LNK_DATA_RX
|
189 EDMA_ERR_LNK_DATA_TX
|
190 EDMA_ERR_TRANS_PROTO
),
192 EDMA_REQ_Q_BASE_HI_OFS
= 0x10,
193 EDMA_REQ_Q_IN_PTR_OFS
= 0x14, /* also contains BASE_LO */
194 EDMA_REQ_Q_BASE_LO_MASK
= 0xfffffc00U
,
196 EDMA_REQ_Q_OUT_PTR_OFS
= 0x18,
197 EDMA_REQ_Q_PTR_SHIFT
= 5,
199 EDMA_RSP_Q_BASE_HI_OFS
= 0x1c,
200 EDMA_RSP_Q_IN_PTR_OFS
= 0x20,
201 EDMA_RSP_Q_OUT_PTR_OFS
= 0x24, /* also contains BASE_LO */
202 EDMA_RSP_Q_BASE_LO_MASK
= 0xffffff00U
,
203 EDMA_RSP_Q_PTR_SHIFT
= 3,
210 /* Host private flags (hp_flags) */
211 MV_HP_FLAG_MSI
= (1 << 0),
213 /* Port private flags (pp_flags) */
214 MV_PP_FLAG_EDMA_EN
= (1 << 0),
215 MV_PP_FLAG_EDMA_DS_ACT
= (1 << 1),
218 /* Command ReQuest Block: 32B */
226 /* Command ResPonse Block: 8B */
233 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
241 struct mv_port_priv
{
242 struct mv_crqb
*crqb
;
244 struct mv_crpb
*crpb
;
246 struct mv_sg
*sg_tbl
;
247 dma_addr_t sg_tbl_dma
;
249 unsigned req_producer
; /* cp of req_in_ptr */
250 unsigned rsp_consumer
; /* cp of rsp_out_ptr */
254 struct mv_host_priv
{
258 static void mv_irq_clear(struct ata_port
*ap
);
259 static u32
mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
);
260 static void mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
261 static u8
mv_check_err(struct ata_port
*ap
);
262 static void mv_phy_reset(struct ata_port
*ap
);
263 static void mv_host_stop(struct ata_host_set
*host_set
);
264 static int mv_port_start(struct ata_port
*ap
);
265 static void mv_port_stop(struct ata_port
*ap
);
266 static void mv_qc_prep(struct ata_queued_cmd
*qc
);
267 static int mv_qc_issue(struct ata_queued_cmd
*qc
);
268 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
,
269 struct pt_regs
*regs
);
270 static void mv_eng_timeout(struct ata_port
*ap
);
271 static int mv_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
273 static Scsi_Host_Template mv_sht
= {
274 .module
= THIS_MODULE
,
276 .ioctl
= ata_scsi_ioctl
,
277 .queuecommand
= ata_scsi_queuecmd
,
278 .eh_strategy_handler
= ata_scsi_error
,
279 .can_queue
= MV_USE_Q_DEPTH
,
280 .this_id
= ATA_SHT_THIS_ID
,
281 .sg_tablesize
= MV_MAX_SG_CT
,
282 .max_sectors
= ATA_MAX_SECTORS
,
283 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
284 .emulated
= ATA_SHT_EMULATED
,
285 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
286 .proc_name
= DRV_NAME
,
287 .dma_boundary
= MV_DMA_BOUNDARY
,
288 .slave_configure
= ata_scsi_slave_config
,
289 .bios_param
= ata_std_bios_param
,
293 static struct ata_port_operations mv_ops
= {
294 .port_disable
= ata_port_disable
,
296 .tf_load
= ata_tf_load
,
297 .tf_read
= ata_tf_read
,
298 .check_status
= ata_check_status
,
299 .check_err
= mv_check_err
,
300 .exec_command
= ata_exec_command
,
301 .dev_select
= ata_std_dev_select
,
303 .phy_reset
= mv_phy_reset
,
305 .qc_prep
= mv_qc_prep
,
306 .qc_issue
= mv_qc_issue
,
308 .eng_timeout
= mv_eng_timeout
,
310 .irq_handler
= mv_interrupt
,
311 .irq_clear
= mv_irq_clear
,
313 .scr_read
= mv_scr_read
,
314 .scr_write
= mv_scr_write
,
316 .port_start
= mv_port_start
,
317 .port_stop
= mv_port_stop
,
318 .host_stop
= mv_host_stop
,
321 static struct ata_port_info mv_port_info
[] = {
324 .host_flags
= MV_COMMON_FLAGS
,
325 .pio_mask
= 0x1f, /* pio0-4 */
326 .udma_mask
= 0, /* 0x7f (udma0-6 disabled for now) */
331 .host_flags
= (MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
),
332 .pio_mask
= 0x1f, /* pio0-4 */
333 .udma_mask
= 0, /* 0x7f (udma0-6 disabled for now) */
338 .host_flags
= (MV_COMMON_FLAGS
| MV_6XXX_FLAGS
),
339 .pio_mask
= 0x1f, /* pio0-4 */
340 .udma_mask
= 0x7f, /* udma0-6 */
345 .host_flags
= (MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
347 .pio_mask
= 0x1f, /* pio0-4 */
348 .udma_mask
= 0x7f, /* udma0-6 */
353 static struct pci_device_id mv_pci_tbl
[] = {
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5040), 0, 0, chip_504x
},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5041), 0, 0, chip_504x
},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5080), 0, 0, chip_508x
},
357 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5081), 0, 0, chip_508x
},
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6040), 0, 0, chip_604x
},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6041), 0, 0, chip_604x
},
361 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6080), 0, 0, chip_608x
},
362 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x6081), 0, 0, chip_608x
},
363 {} /* terminate list */
366 static struct pci_driver mv_pci_driver
= {
368 .id_table
= mv_pci_tbl
,
369 .probe
= mv_init_one
,
370 .remove
= ata_pci_remove_one
,
377 static inline void writelfl(unsigned long data
, void __iomem
*addr
)
380 (void) readl(addr
); /* flush to avoid PCI posted write */
383 static inline void __iomem
*mv_hc_base(void __iomem
*base
, unsigned int hc
)
385 return (base
+ MV_SATAHC0_REG_BASE
+ (hc
* MV_SATAHC_REG_SZ
));
388 static inline void __iomem
*mv_port_base(void __iomem
*base
, unsigned int port
)
390 return (mv_hc_base(base
, port
>> MV_PORT_HC_SHIFT
) +
391 MV_SATAHC_ARBTR_REG_SZ
+
392 ((port
& MV_PORT_MASK
) * MV_PORT_REG_SZ
));
395 static inline void __iomem
*mv_ap_base(struct ata_port
*ap
)
397 return mv_port_base(ap
->host_set
->mmio_base
, ap
->port_no
);
400 static inline int mv_get_hc_count(unsigned long hp_flags
)
402 return ((hp_flags
& MV_FLAG_DUAL_HC
) ? 2 : 1);
405 static void mv_irq_clear(struct ata_port
*ap
)
410 * mv_start_dma - Enable eDMA engine
411 * @base: port base address
412 * @pp: port private data
414 * Verify the local cache of the eDMA state is accurate with an
418 * Inherited from caller.
420 static void mv_start_dma(void __iomem
*base
, struct mv_port_priv
*pp
)
422 if (!(MV_PP_FLAG_EDMA_EN
& pp
->pp_flags
)) {
423 writelfl(EDMA_EN
, base
+ EDMA_CMD_OFS
);
424 pp
->pp_flags
|= MV_PP_FLAG_EDMA_EN
;
426 assert(EDMA_EN
& readl(base
+ EDMA_CMD_OFS
));
430 * mv_stop_dma - Disable eDMA engine
431 * @ap: ATA channel to manipulate
433 * Verify the local cache of the eDMA state is accurate with an
437 * Inherited from caller.
439 static void mv_stop_dma(struct ata_port
*ap
)
441 void __iomem
*port_mmio
= mv_ap_base(ap
);
442 struct mv_port_priv
*pp
= ap
->private_data
;
446 if (MV_PP_FLAG_EDMA_EN
& pp
->pp_flags
) {
447 /* Disable EDMA if active. The disable bit auto clears.
449 writelfl(EDMA_DS
, port_mmio
+ EDMA_CMD_OFS
);
450 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
452 assert(!(EDMA_EN
& readl(port_mmio
+ EDMA_CMD_OFS
)));
455 /* now properly wait for the eDMA to stop */
456 for (i
= 1000; i
> 0; i
--) {
457 reg
= readl(port_mmio
+ EDMA_CMD_OFS
);
458 if (!(EDMA_EN
& reg
)) {
465 printk(KERN_ERR
"ata%u: Unable to stop eDMA\n", ap
->id
);
466 /* FIXME: Consider doing a reset here to recover */
471 static void mv_dump_mem(void __iomem
*start
, unsigned bytes
)
474 for (b
= 0; b
< bytes
; ) {
475 DPRINTK("%p: ", start
+ b
);
476 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
477 printk("%08x ",readl(start
+ b
));
485 static void mv_dump_pci_cfg(struct pci_dev
*pdev
, unsigned bytes
)
490 for (b
= 0; b
< bytes
; ) {
491 DPRINTK("%02x: ", b
);
492 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
493 (void) pci_read_config_dword(pdev
,b
,&dw
);
501 static void mv_dump_all_regs(void __iomem
*mmio_base
, int port
,
502 struct pci_dev
*pdev
)
505 void __iomem
*hc_base
= mv_hc_base(mmio_base
,
506 port
>> MV_PORT_HC_SHIFT
);
507 void __iomem
*port_base
;
508 int start_port
, num_ports
, p
, start_hc
, num_hcs
, hc
;
511 start_hc
= start_port
= 0;
512 num_ports
= 8; /* shld be benign for 4 port devs */
515 start_hc
= port
>> MV_PORT_HC_SHIFT
;
517 num_ports
= num_hcs
= 1;
519 DPRINTK("All registers for port(s) %u-%u:\n", start_port
,
520 num_ports
> 1 ? num_ports
- 1 : start_port
);
523 DPRINTK("PCI config space regs:\n");
524 mv_dump_pci_cfg(pdev
, 0x68);
526 DPRINTK("PCI regs:\n");
527 mv_dump_mem(mmio_base
+0xc00, 0x3c);
528 mv_dump_mem(mmio_base
+0xd00, 0x34);
529 mv_dump_mem(mmio_base
+0xf00, 0x4);
530 mv_dump_mem(mmio_base
+0x1d00, 0x6c);
531 for (hc
= start_hc
; hc
< start_hc
+ num_hcs
; hc
++) {
532 hc_base
= mv_hc_base(mmio_base
, port
>> MV_PORT_HC_SHIFT
);
533 DPRINTK("HC regs (HC %i):\n", hc
);
534 mv_dump_mem(hc_base
, 0x1c);
536 for (p
= start_port
; p
< start_port
+ num_ports
; p
++) {
537 port_base
= mv_port_base(mmio_base
, p
);
538 DPRINTK("EDMA regs (port %i):\n",p
);
539 mv_dump_mem(port_base
, 0x54);
540 DPRINTK("SATA regs (port %i):\n",p
);
541 mv_dump_mem(port_base
+0x300, 0x60);
546 static unsigned int mv_scr_offset(unsigned int sc_reg_in
)
554 ofs
= SATA_STATUS_OFS
+ (sc_reg_in
* sizeof(u32
));
557 ofs
= SATA_ACTIVE_OFS
; /* active is not with the others */
566 static u32
mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
)
568 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
570 if (0xffffffffU
!= ofs
) {
571 return readl(mv_ap_base(ap
) + ofs
);
577 static void mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
579 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
581 if (0xffffffffU
!= ofs
) {
582 writelfl(val
, mv_ap_base(ap
) + ofs
);
587 * mv_global_soft_reset - Perform the 6xxx global soft reset
588 * @mmio_base: base address of the HBA
590 * This routine only applies to 6xxx parts.
593 * Inherited from caller.
595 static int mv_global_soft_reset(void __iomem
*mmio_base
)
597 void __iomem
*reg
= mmio_base
+ PCI_MAIN_CMD_STS_OFS
;
601 /* Following procedure defined in PCI "main command and status
605 writel(t
| STOP_PCI_MASTER
, reg
);
607 for (i
= 0; i
< 1000; i
++) {
610 if (PCI_MASTER_EMPTY
& t
) {
614 if (!(PCI_MASTER_EMPTY
& t
)) {
615 printk(KERN_ERR DRV_NAME
": PCI master won't flush\n");
623 writel(t
| GLOB_SFT_RST
, reg
);
626 } while (!(GLOB_SFT_RST
& t
) && (i
-- > 0));
628 if (!(GLOB_SFT_RST
& t
)) {
629 printk(KERN_ERR DRV_NAME
": can't set global reset\n");
634 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
637 writel(t
& ~(GLOB_SFT_RST
| STOP_PCI_MASTER
), reg
);
640 } while ((GLOB_SFT_RST
& t
) && (i
-- > 0));
642 if (GLOB_SFT_RST
& t
) {
643 printk(KERN_ERR DRV_NAME
": can't clear global reset\n");
651 * mv_host_stop - Host specific cleanup/stop routine.
652 * @host_set: host data structure
654 * Disable ints, cleanup host memory, call general purpose
658 * Inherited from caller.
660 static void mv_host_stop(struct ata_host_set
*host_set
)
662 struct mv_host_priv
*hpriv
= host_set
->private_data
;
663 struct pci_dev
*pdev
= to_pci_dev(host_set
->dev
);
665 if (hpriv
->hp_flags
& MV_HP_FLAG_MSI
) {
666 pci_disable_msi(pdev
);
671 ata_host_stop(host_set
);
675 * mv_port_start - Port specific init/start routine.
676 * @ap: ATA channel to manipulate
678 * Allocate and point to DMA memory, init port private memory,
682 * Inherited from caller.
684 static int mv_port_start(struct ata_port
*ap
)
686 struct device
*dev
= ap
->host_set
->dev
;
687 struct mv_port_priv
*pp
;
688 void __iomem
*port_mmio
= mv_ap_base(ap
);
692 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
696 memset(pp
, 0, sizeof(*pp
));
698 mem
= dma_alloc_coherent(dev
, MV_PORT_PRIV_DMA_SZ
, &mem_dma
,
704 memset(mem
, 0, MV_PORT_PRIV_DMA_SZ
);
706 /* First item in chunk of DMA memory:
707 * 32-slot command request table (CRQB), 32 bytes each in size
710 pp
->crqb_dma
= mem_dma
;
712 mem_dma
+= MV_CRQB_Q_SZ
;
715 * 32-slot command response table (CRPB), 8 bytes each in size
718 pp
->crpb_dma
= mem_dma
;
720 mem_dma
+= MV_CRPB_Q_SZ
;
723 * Table of scatter-gather descriptors (ePRD), 16 bytes each
726 pp
->sg_tbl_dma
= mem_dma
;
728 writelfl(EDMA_CFG_Q_DEPTH
| EDMA_CFG_RD_BRST_EXT
|
729 EDMA_CFG_WR_BUFF_LEN
, port_mmio
+ EDMA_CFG_OFS
);
731 writel((pp
->crqb_dma
>> 16) >> 16, port_mmio
+ EDMA_REQ_Q_BASE_HI_OFS
);
732 writelfl(pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
,
733 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
735 writelfl(0, port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
);
736 writelfl(0, port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
);
738 writel((pp
->crpb_dma
>> 16) >> 16, port_mmio
+ EDMA_RSP_Q_BASE_HI_OFS
);
739 writelfl(pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
,
740 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
742 pp
->req_producer
= pp
->rsp_consumer
= 0;
744 /* Don't turn on EDMA here...do it before DMA commands only. Else
745 * we'll be unable to send non-data, PIO, etc due to restricted access
748 ap
->private_data
= pp
;
753 * mv_port_stop - Port specific cleanup/stop routine.
754 * @ap: ATA channel to manipulate
756 * Stop DMA, cleanup port memory.
759 * This routine uses the host_set lock to protect the DMA stop.
761 static void mv_port_stop(struct ata_port
*ap
)
763 struct device
*dev
= ap
->host_set
->dev
;
764 struct mv_port_priv
*pp
= ap
->private_data
;
767 spin_lock_irqsave(&ap
->host_set
->lock
, flags
);
769 spin_unlock_irqrestore(&ap
->host_set
->lock
, flags
);
771 ap
->private_data
= NULL
;
772 dma_free_coherent(dev
, MV_PORT_PRIV_DMA_SZ
, pp
->crpb
, pp
->crpb_dma
);
777 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
778 * @qc: queued command whose SG list to source from
780 * Populate the SG list and mark the last entry.
783 * Inherited from caller.
785 static void mv_fill_sg(struct ata_queued_cmd
*qc
)
787 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
790 for (i
= 0; i
< qc
->n_elem
; i
++) {
794 addr
= sg_dma_address(&qc
->sg
[i
]);
795 sg_len
= sg_dma_len(&qc
->sg
[i
]);
797 pp
->sg_tbl
[i
].addr
= cpu_to_le32(addr
& 0xffffffff);
798 pp
->sg_tbl
[i
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
799 assert(0 == (sg_len
& ~MV_DMA_BOUNDARY
));
800 pp
->sg_tbl
[i
].flags_size
= cpu_to_le32(sg_len
);
802 if (0 < qc
->n_elem
) {
803 pp
->sg_tbl
[qc
->n_elem
- 1].flags_size
|= EPRD_FLAG_END_OF_TBL
;
807 static inline unsigned mv_inc_q_index(unsigned *index
)
809 *index
= (*index
+ 1) & MV_MAX_Q_DEPTH_MASK
;
813 static inline void mv_crqb_pack_cmd(u16
*cmdw
, u8 data
, u8 addr
, unsigned last
)
815 *cmdw
= data
| (addr
<< CRQB_CMD_ADDR_SHIFT
) | CRQB_CMD_CS
|
816 (last
? CRQB_CMD_LAST
: 0);
820 * mv_qc_prep - Host specific command preparation.
821 * @qc: queued command to prepare
823 * This routine simply redirects to the general purpose routine
824 * if command is not DMA. Else, it handles prep of the CRQB
825 * (command request block), does some sanity checking, and calls
826 * the SG load routine.
829 * Inherited from caller.
831 static void mv_qc_prep(struct ata_queued_cmd
*qc
)
833 struct ata_port
*ap
= qc
->ap
;
834 struct mv_port_priv
*pp
= ap
->private_data
;
836 struct ata_taskfile
*tf
;
839 if (ATA_PROT_DMA
!= qc
->tf
.protocol
) {
843 /* the req producer index should be the same as we remember it */
844 assert(((readl(mv_ap_base(qc
->ap
) + EDMA_REQ_Q_IN_PTR_OFS
) >>
845 EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
848 /* Fill in command request block
850 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
)) {
851 flags
|= CRQB_FLAG_READ
;
853 assert(MV_MAX_Q_DEPTH
> qc
->tag
);
854 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
856 pp
->crqb
[pp
->req_producer
].sg_addr
=
857 cpu_to_le32(pp
->sg_tbl_dma
& 0xffffffff);
858 pp
->crqb
[pp
->req_producer
].sg_addr_hi
=
859 cpu_to_le32((pp
->sg_tbl_dma
>> 16) >> 16);
860 pp
->crqb
[pp
->req_producer
].ctrl_flags
= cpu_to_le16(flags
);
862 cw
= &pp
->crqb
[pp
->req_producer
].ata_cmd
[0];
865 /* Sadly, the CRQB cannot accomodate all registers--there are
866 * only 11 bytes...so we must pick and choose required
867 * registers based on the command. So, we drop feature and
868 * hob_feature for [RW] DMA commands, but they are needed for
869 * NCQ. NCQ will drop hob_nsect.
871 switch (tf
->command
) {
873 case ATA_CMD_READ_EXT
:
875 case ATA_CMD_WRITE_EXT
:
876 mv_crqb_pack_cmd(cw
++, tf
->hob_nsect
, ATA_REG_NSECT
, 0);
878 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
879 case ATA_CMD_FPDMA_READ
:
880 case ATA_CMD_FPDMA_WRITE
:
881 mv_crqb_pack_cmd(cw
++, tf
->hob_feature
, ATA_REG_FEATURE
, 0);
882 mv_crqb_pack_cmd(cw
++, tf
->feature
, ATA_REG_FEATURE
, 0);
884 #endif /* FIXME: remove this line when NCQ added */
886 /* The only other commands EDMA supports in non-queued and
887 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
888 * of which are defined/used by Linux. If we get here, this
891 * FIXME: modify libata to give qc_prep a return value and
897 mv_crqb_pack_cmd(cw
++, tf
->nsect
, ATA_REG_NSECT
, 0);
898 mv_crqb_pack_cmd(cw
++, tf
->hob_lbal
, ATA_REG_LBAL
, 0);
899 mv_crqb_pack_cmd(cw
++, tf
->lbal
, ATA_REG_LBAL
, 0);
900 mv_crqb_pack_cmd(cw
++, tf
->hob_lbam
, ATA_REG_LBAM
, 0);
901 mv_crqb_pack_cmd(cw
++, tf
->lbam
, ATA_REG_LBAM
, 0);
902 mv_crqb_pack_cmd(cw
++, tf
->hob_lbah
, ATA_REG_LBAH
, 0);
903 mv_crqb_pack_cmd(cw
++, tf
->lbah
, ATA_REG_LBAH
, 0);
904 mv_crqb_pack_cmd(cw
++, tf
->device
, ATA_REG_DEVICE
, 0);
905 mv_crqb_pack_cmd(cw
++, tf
->command
, ATA_REG_CMD
, 1); /* last */
907 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
)) {
914 * mv_qc_issue - Initiate a command to the host
915 * @qc: queued command to start
917 * This routine simply redirects to the general purpose routine
918 * if command is not DMA. Else, it sanity checks our local
919 * caches of the request producer/consumer indices then enables
920 * DMA and bumps the request producer index.
923 * Inherited from caller.
925 static int mv_qc_issue(struct ata_queued_cmd
*qc
)
927 void __iomem
*port_mmio
= mv_ap_base(qc
->ap
);
928 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
931 if (ATA_PROT_DMA
!= qc
->tf
.protocol
) {
932 /* We're about to send a non-EDMA capable command to the
933 * port. Turn off EDMA so there won't be problems accessing
934 * shadow block, etc registers.
937 return ata_qc_issue_prot(qc
);
940 in_ptr
= readl(port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
942 /* the req producer index should be the same as we remember it */
943 assert(((in_ptr
>> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
945 /* until we do queuing, the queue should be empty at this point */
946 assert(((in_ptr
>> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
947 ((readl(port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
) >>
948 EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
));
950 mv_inc_q_index(&pp
->req_producer
); /* now incr producer index */
952 mv_start_dma(port_mmio
, pp
);
954 /* and write the request in pointer to kick the EDMA to life */
955 in_ptr
&= EDMA_REQ_Q_BASE_LO_MASK
;
956 in_ptr
|= pp
->req_producer
<< EDMA_REQ_Q_PTR_SHIFT
;
957 writelfl(in_ptr
, port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
963 * mv_get_crpb_status - get status from most recently completed cmd
964 * @ap: ATA channel to manipulate
966 * This routine is for use when the port is in DMA mode, when it
967 * will be using the CRPB (command response block) method of
968 * returning command completion information. We assert indices
969 * are good, grab status, and bump the response consumer index to
970 * prove that we're up to date.
973 * Inherited from caller.
975 static u8
mv_get_crpb_status(struct ata_port
*ap
)
977 void __iomem
*port_mmio
= mv_ap_base(ap
);
978 struct mv_port_priv
*pp
= ap
->private_data
;
981 out_ptr
= readl(port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
983 /* the response consumer index should be the same as we remember it */
984 assert(((out_ptr
>> EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
987 /* increment our consumer index... */
988 pp
->rsp_consumer
= mv_inc_q_index(&pp
->rsp_consumer
);
990 /* and, until we do NCQ, there should only be 1 CRPB waiting */
991 assert(((readl(port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
) >>
992 EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
) ==
995 /* write out our inc'd consumer index so EDMA knows we're caught up */
996 out_ptr
&= EDMA_RSP_Q_BASE_LO_MASK
;
997 out_ptr
|= pp
->rsp_consumer
<< EDMA_RSP_Q_PTR_SHIFT
;
998 writelfl(out_ptr
, port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
1000 /* Return ATA status register for completed CRPB */
1001 return (pp
->crpb
[pp
->rsp_consumer
].flags
>> CRPB_FLAG_STATUS_SHIFT
);
1005 * mv_err_intr - Handle error interrupts on the port
1006 * @ap: ATA channel to manipulate
1008 * In most cases, just clear the interrupt and move on. However,
1009 * some cases require an eDMA reset, which is done right before
1010 * the COMRESET in mv_phy_reset(). The SERR case requires a
1011 * clear of pending errors in the SATA SERROR register. Finally,
1012 * if the port disabled DMA, update our cached copy to match.
1015 * Inherited from caller.
1017 static void mv_err_intr(struct ata_port
*ap
)
1019 void __iomem
*port_mmio
= mv_ap_base(ap
);
1020 u32 edma_err_cause
, serr
= 0;
1022 edma_err_cause
= readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1024 if (EDMA_ERR_SERR
& edma_err_cause
) {
1025 serr
= scr_read(ap
, SCR_ERROR
);
1026 scr_write_flush(ap
, SCR_ERROR
, serr
);
1028 if (EDMA_ERR_SELF_DIS
& edma_err_cause
) {
1029 struct mv_port_priv
*pp
= ap
->private_data
;
1030 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1032 DPRINTK(KERN_ERR
"ata%u: port error; EDMA err cause: 0x%08x "
1033 "SERR: 0x%08x\n", ap
->id
, edma_err_cause
, serr
);
1035 /* Clear EDMA now that SERR cleanup done */
1036 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1038 /* check for fatal here and recover if needed */
1039 if (EDMA_ERR_FATAL
& edma_err_cause
) {
1045 * mv_host_intr - Handle all interrupts on the given host controller
1046 * @host_set: host specific structure
1047 * @relevant: port error bits relevant to this host controller
1048 * @hc: which host controller we're to look at
1050 * Read then write clear the HC interrupt status then walk each
1051 * port connected to the HC and see if it needs servicing. Port
1052 * success ints are reported in the HC interrupt status reg, the
1053 * port error ints are reported in the higher level main
1054 * interrupt status register and thus are passed in via the
1055 * 'relevant' argument.
1058 * Inherited from caller.
1060 static void mv_host_intr(struct ata_host_set
*host_set
, u32 relevant
,
1063 void __iomem
*mmio
= host_set
->mmio_base
;
1064 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
1065 struct ata_port
*ap
;
1066 struct ata_queued_cmd
*qc
;
1068 int shift
, port
, port0
, hard_port
, handled
;
1074 port0
= MV_PORTS_PER_HC
;
1077 /* we'll need the HC success int register in most cases */
1078 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1080 writelfl(~hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1083 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1084 hc
,relevant
,hc_irq_cause
);
1086 for (port
= port0
; port
< port0
+ MV_PORTS_PER_HC
; port
++) {
1087 ap
= host_set
->ports
[port
];
1088 hard_port
= port
& MV_PORT_MASK
; /* range 0-3 */
1089 handled
= 0; /* ensure ata_status is set if handled++ */
1091 if ((CRPB_DMA_DONE
<< hard_port
) & hc_irq_cause
) {
1092 /* new CRPB on the queue; just one at a time until NCQ
1094 ata_status
= mv_get_crpb_status(ap
);
1096 } else if ((DEV_IRQ
<< hard_port
) & hc_irq_cause
) {
1097 /* received ATA IRQ; read the status reg to clear INTRQ
1099 ata_status
= readb((void __iomem
*)
1100 ap
->ioaddr
.status_addr
);
1104 shift
= port
<< 1; /* (port * 2) */
1105 if (port
>= MV_PORTS_PER_HC
) {
1106 shift
++; /* skip bit 8 in the HC Main IRQ reg */
1108 if ((PORT0_ERR
<< shift
) & relevant
) {
1110 /* OR in ATA_ERR to ensure libata knows we took one */
1111 ata_status
= readb((void __iomem
*)
1112 ap
->ioaddr
.status_addr
) | ATA_ERR
;
1116 if (handled
&& ap
) {
1117 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1119 VPRINTK("port %u IRQ found for qc, "
1120 "ata_status 0x%x\n", port
,ata_status
);
1121 /* mark qc status appropriately */
1122 ata_qc_complete(qc
, ata_status
);
1132 * @dev_instance: private data; in this case the host structure
1135 * Read the read only register to determine if any host
1136 * controllers have pending interrupts. If so, call lower level
1137 * routine to handle. Also check for PCI errors which are only
1141 * This routine holds the host_set lock while processing pending
1144 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
,
1145 struct pt_regs
*regs
)
1147 struct ata_host_set
*host_set
= dev_instance
;
1148 unsigned int hc
, handled
= 0, n_hcs
;
1149 void __iomem
*mmio
= host_set
->mmio_base
;
1152 irq_stat
= readl(mmio
+ HC_MAIN_IRQ_CAUSE_OFS
);
1154 /* check the cases where we either have nothing pending or have read
1155 * a bogus register value which can indicate HW removal or PCI fault
1157 if (!irq_stat
|| (0xffffffffU
== irq_stat
)) {
1161 n_hcs
= mv_get_hc_count(host_set
->ports
[0]->flags
);
1162 spin_lock(&host_set
->lock
);
1164 for (hc
= 0; hc
< n_hcs
; hc
++) {
1165 u32 relevant
= irq_stat
& (HC0_IRQ_PEND
<< (hc
* HC_SHIFT
));
1167 mv_host_intr(host_set
, relevant
, hc
);
1171 if (PCI_ERR
& irq_stat
) {
1172 printk(KERN_ERR DRV_NAME
": PCI ERROR; PCI IRQ cause=0x%08x\n",
1173 readl(mmio
+ PCI_IRQ_CAUSE_OFS
));
1175 DPRINTK("All regs @ PCI error\n");
1176 mv_dump_all_regs(mmio
, -1, to_pci_dev(host_set
->dev
));
1178 writelfl(0, mmio
+ PCI_IRQ_CAUSE_OFS
);
1181 spin_unlock(&host_set
->lock
);
1183 return IRQ_RETVAL(handled
);
1187 * mv_check_err - Return the error shadow register to caller.
1188 * @ap: ATA channel to manipulate
1190 * Marvell requires DMA to be stopped before accessing shadow
1191 * registers. So we do that, then return the needed register.
1194 * Inherited from caller. FIXME: protect mv_stop_dma with lock?
1196 static u8
mv_check_err(struct ata_port
*ap
)
1198 mv_stop_dma(ap
); /* can't read shadow regs if DMA on */
1199 return readb((void __iomem
*) ap
->ioaddr
.error_addr
);
1203 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1204 * @ap: ATA channel to manipulate
1206 * Part of this is taken from __sata_phy_reset and modified to
1207 * not sleep since this routine gets called from interrupt level.
1210 * Inherited from caller. This is coded to safe to call at
1211 * interrupt level, i.e. it does not sleep.
1213 static void mv_phy_reset(struct ata_port
*ap
)
1215 void __iomem
*port_mmio
= mv_ap_base(ap
);
1216 struct ata_taskfile tf
;
1217 struct ata_device
*dev
= &ap
->device
[0];
1218 unsigned long timeout
;
1220 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap
->port_no
, port_mmio
);
1224 writelfl(ATA_RST
, port_mmio
+ EDMA_CMD_OFS
);
1225 udelay(25); /* allow reset propagation */
1227 /* Spec never mentions clearing the bit. Marvell's driver does
1228 * clear the bit, however.
1230 writelfl(0, port_mmio
+ EDMA_CMD_OFS
);
1232 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1233 "SCtrl 0x%08x\n", mv_scr_read(ap
, SCR_STATUS
),
1234 mv_scr_read(ap
, SCR_ERROR
), mv_scr_read(ap
, SCR_CONTROL
));
1236 /* proceed to init communications via the scr_control reg */
1237 scr_write_flush(ap
, SCR_CONTROL
, 0x301);
1239 scr_write_flush(ap
, SCR_CONTROL
, 0x300);
1240 timeout
= jiffies
+ (HZ
* 1);
1243 if ((scr_read(ap
, SCR_STATUS
) & 0xf) != 1)
1245 } while (time_before(jiffies
, timeout
));
1247 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1248 "SCtrl 0x%08x\n", mv_scr_read(ap
, SCR_STATUS
),
1249 mv_scr_read(ap
, SCR_ERROR
), mv_scr_read(ap
, SCR_CONTROL
));
1251 if (sata_dev_present(ap
)) {
1254 printk(KERN_INFO
"ata%u: no device found (phy stat %08x)\n",
1255 ap
->id
, scr_read(ap
, SCR_STATUS
));
1256 ata_port_disable(ap
);
1259 ap
->cbl
= ATA_CBL_SATA
;
1261 tf
.lbah
= readb((void __iomem
*) ap
->ioaddr
.lbah_addr
);
1262 tf
.lbam
= readb((void __iomem
*) ap
->ioaddr
.lbam_addr
);
1263 tf
.lbal
= readb((void __iomem
*) ap
->ioaddr
.lbal_addr
);
1264 tf
.nsect
= readb((void __iomem
*) ap
->ioaddr
.nsect_addr
);
1266 dev
->class = ata_dev_classify(&tf
);
1267 if (!ata_dev_present(dev
)) {
1268 VPRINTK("Port disabled post-sig: No device present.\n");
1269 ata_port_disable(ap
);
1275 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1276 * @ap: ATA channel to manipulate
1278 * Intent is to clear all pending error conditions, reset the
1279 * chip/bus, fail the command, and move on.
1282 * This routine holds the host_set lock while failing the command.
1284 static void mv_eng_timeout(struct ata_port
*ap
)
1286 struct ata_queued_cmd
*qc
;
1287 unsigned long flags
;
1289 printk(KERN_ERR
"ata%u: Entering mv_eng_timeout\n",ap
->id
);
1290 DPRINTK("All regs @ start of eng_timeout\n");
1291 mv_dump_all_regs(ap
->host_set
->mmio_base
, ap
->port_no
,
1292 to_pci_dev(ap
->host_set
->dev
));
1294 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1295 printk(KERN_ERR
"mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1296 ap
->host_set
->mmio_base
, ap
, qc
, qc
->scsicmd
,
1297 &qc
->scsicmd
->cmnd
);
1303 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
1306 /* hack alert! We cannot use the supplied completion
1307 * function from inside the ->eh_strategy_handler() thread.
1308 * libata is the only user of ->eh_strategy_handler() in
1309 * any kernel, so the default scsi_done() assumes it is
1310 * not being called from the SCSI EH.
1312 spin_lock_irqsave(&ap
->host_set
->lock
, flags
);
1313 qc
->scsidone
= scsi_finish_command
;
1314 ata_qc_complete(qc
, ATA_ERR
);
1315 spin_unlock_irqrestore(&ap
->host_set
->lock
, flags
);
1320 * mv_port_init - Perform some early initialization on a single port.
1321 * @port: libata data structure storing shadow register addresses
1322 * @port_mmio: base address of the port
1324 * Initialize shadow register mmio addresses, clear outstanding
1325 * interrupts on the port, and unmask interrupts for the future
1326 * start of the port.
1329 * Inherited from caller.
1331 static void mv_port_init(struct ata_ioports
*port
, void __iomem
*port_mmio
)
1333 unsigned long shd_base
= (unsigned long) port_mmio
+ SHD_BLK_OFS
;
1336 /* PIO related setup
1338 port
->data_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DATA
);
1340 port
->feature_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_ERR
);
1341 port
->nsect_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_NSECT
);
1342 port
->lbal_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAL
);
1343 port
->lbam_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAM
);
1344 port
->lbah_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAH
);
1345 port
->device_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DEVICE
);
1347 port
->command_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_STATUS
);
1348 /* special case: control/altstatus doesn't have ATA_REG_ address */
1349 port
->altstatus_addr
= port
->ctl_addr
= shd_base
+ SHD_CTL_AST_OFS
;
1352 port
->cmd_addr
= port
->bmdma_addr
= port
->scr_addr
= 0;
1354 /* Clear any currently outstanding port interrupt conditions */
1355 serr_ofs
= mv_scr_offset(SCR_ERROR
);
1356 writelfl(readl(port_mmio
+ serr_ofs
), port_mmio
+ serr_ofs
);
1357 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1359 /* unmask all EDMA error interrupts */
1360 writelfl(~0, port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
);
1362 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1363 readl(port_mmio
+ EDMA_CFG_OFS
),
1364 readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
),
1365 readl(port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
));
1369 * mv_host_init - Perform some early initialization of the host.
1370 * @probe_ent: early data struct representing the host
1372 * If possible, do an early global reset of the host. Then do
1373 * our port init and clear/unmask all/relevant host interrupts.
1376 * Inherited from caller.
1378 static int mv_host_init(struct ata_probe_ent
*probe_ent
)
1380 int rc
= 0, n_hc
, port
, hc
;
1381 void __iomem
*mmio
= probe_ent
->mmio_base
;
1382 void __iomem
*port_mmio
;
1384 if ((MV_FLAG_GLBL_SFT_RST
& probe_ent
->host_flags
) &&
1385 mv_global_soft_reset(probe_ent
->mmio_base
)) {
1390 n_hc
= mv_get_hc_count(probe_ent
->host_flags
);
1391 probe_ent
->n_ports
= MV_PORTS_PER_HC
* n_hc
;
1393 for (port
= 0; port
< probe_ent
->n_ports
; port
++) {
1394 port_mmio
= mv_port_base(mmio
, port
);
1395 mv_port_init(&probe_ent
->port
[port
], port_mmio
);
1398 for (hc
= 0; hc
< n_hc
; hc
++) {
1399 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
1401 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1402 "(before clear)=0x%08x\n", hc
,
1403 readl(hc_mmio
+ HC_CFG_OFS
),
1404 readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
));
1406 /* Clear any currently outstanding hc interrupt conditions */
1407 writelfl(0, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1410 /* Clear any currently outstanding host interrupt conditions */
1411 writelfl(0, mmio
+ PCI_IRQ_CAUSE_OFS
);
1413 /* and unmask interrupt generation for host regs */
1414 writelfl(PCI_UNMASK_ALL_IRQS
, mmio
+ PCI_IRQ_MASK_OFS
);
1415 writelfl(~HC_MAIN_MASKED_IRQS
, mmio
+ HC_MAIN_IRQ_MASK_OFS
);
1417 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1418 "PCI int cause/mask=0x%08x/0x%08x\n",
1419 readl(mmio
+ HC_MAIN_IRQ_CAUSE_OFS
),
1420 readl(mmio
+ HC_MAIN_IRQ_MASK_OFS
),
1421 readl(mmio
+ PCI_IRQ_CAUSE_OFS
),
1422 readl(mmio
+ PCI_IRQ_MASK_OFS
));
1428 * mv_print_info - Dump key info to kernel log for perusal.
1429 * @probe_ent: early data struct representing the host
1431 * FIXME: complete this.
1434 * Inherited from caller.
1436 static void mv_print_info(struct ata_probe_ent
*probe_ent
)
1438 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1439 struct mv_host_priv
*hpriv
= probe_ent
->private_data
;
1443 /* Use this to determine the HW stepping of the chip so we know
1444 * what errata to workaround
1446 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev_id
);
1448 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &scc
);
1451 else if (scc
== 0x01)
1456 printk(KERN_INFO DRV_NAME
1457 "(%s) %u slots %u ports %s mode IRQ via %s\n",
1458 pci_name(pdev
), (unsigned)MV_MAX_Q_DEPTH
, probe_ent
->n_ports
,
1459 scc_s
, (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) ? "MSI" : "INTx");
1463 * mv_init_one - handle a positive probe of a Marvell host
1464 * @pdev: PCI device found
1465 * @ent: PCI device ID entry for the matched host
1468 * Inherited from caller.
1470 static int mv_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1472 static int printed_version
= 0;
1473 struct ata_probe_ent
*probe_ent
= NULL
;
1474 struct mv_host_priv
*hpriv
;
1475 unsigned int board_idx
= (unsigned int)ent
->driver_data
;
1476 void __iomem
*mmio_base
;
1477 int pci_dev_busy
= 0, rc
;
1479 if (!printed_version
++) {
1480 printk(KERN_INFO DRV_NAME
" version " DRV_VERSION
"\n");
1483 rc
= pci_enable_device(pdev
);
1488 rc
= pci_request_regions(pdev
, DRV_NAME
);
1494 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1495 if (probe_ent
== NULL
) {
1497 goto err_out_regions
;
1500 memset(probe_ent
, 0, sizeof(*probe_ent
));
1501 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1502 INIT_LIST_HEAD(&probe_ent
->node
);
1504 mmio_base
= pci_iomap(pdev
, MV_PRIMARY_BAR
, 0);
1505 if (mmio_base
== NULL
) {
1507 goto err_out_free_ent
;
1510 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1513 goto err_out_iounmap
;
1515 memset(hpriv
, 0, sizeof(*hpriv
));
1517 probe_ent
->sht
= mv_port_info
[board_idx
].sht
;
1518 probe_ent
->host_flags
= mv_port_info
[board_idx
].host_flags
;
1519 probe_ent
->pio_mask
= mv_port_info
[board_idx
].pio_mask
;
1520 probe_ent
->udma_mask
= mv_port_info
[board_idx
].udma_mask
;
1521 probe_ent
->port_ops
= mv_port_info
[board_idx
].port_ops
;
1523 probe_ent
->irq
= pdev
->irq
;
1524 probe_ent
->irq_flags
= SA_SHIRQ
;
1525 probe_ent
->mmio_base
= mmio_base
;
1526 probe_ent
->private_data
= hpriv
;
1528 /* initialize adapter */
1529 rc
= mv_host_init(probe_ent
);
1534 /* Enable interrupts */
1535 if (pci_enable_msi(pdev
) == 0) {
1536 hpriv
->hp_flags
|= MV_HP_FLAG_MSI
;
1541 mv_dump_pci_cfg(pdev
, 0x68);
1542 mv_print_info(probe_ent
);
1544 if (ata_device_add(probe_ent
) == 0) {
1545 rc
= -ENODEV
; /* No devices discovered */
1546 goto err_out_dev_add
;
1553 if (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) {
1554 pci_disable_msi(pdev
);
1561 pci_iounmap(pdev
, mmio_base
);
1565 pci_release_regions(pdev
);
1567 if (!pci_dev_busy
) {
1568 pci_disable_device(pdev
);
1574 static int __init
mv_init(void)
1576 return pci_module_init(&mv_pci_driver
);
1579 static void __exit
mv_exit(void)
1581 pci_unregister_driver(&mv_pci_driver
);
1584 MODULE_AUTHOR("Brett Russ");
1585 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1586 MODULE_LICENSE("GPL");
1587 MODULE_DEVICE_TABLE(pci
, mv_pci_tbl
);
1588 MODULE_VERSION(DRV_VERSION
);
1590 module_init(mv_init
);
1591 module_exit(mv_exit
);