1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
2 * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
4 * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
7 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/fcntl.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/crc32.h>
20 #include <linux/errno.h>
21 #include <linux/ethtool.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/bitops.h>
27 #include <asm/auxio.h>
28 #include <asm/byteorder.h>
30 #include <asm/idprom.h>
32 #include <asm/openprom.h>
33 #include <asm/oplib.h>
34 #include <asm/pgtable.h>
36 #include <asm/system.h>
40 static char version
[] __initdata
=
41 "sunbmac.c:v2.0 24/Nov/03 David S. Miller (davem@redhat.com)\n";
48 #define DP(x) printk x
54 #define DTX(x) printk x
60 #define DIRQ(x) printk x
65 static struct bigmac
*root_bigmac_dev
;
67 #define DEFAULT_JAMSIZE 4 /* Toe jam */
69 #define QEC_RESET_TRIES 200
71 static int qec_global_reset(void __iomem
*gregs
)
73 int tries
= QEC_RESET_TRIES
;
75 sbus_writel(GLOB_CTRL_RESET
, gregs
+ GLOB_CTRL
);
77 if (sbus_readl(gregs
+ GLOB_CTRL
) & GLOB_CTRL_RESET
) {
85 printk(KERN_ERR
"BigMAC: Cannot reset the QEC.\n");
89 static void qec_init(struct bigmac
*bp
)
91 void __iomem
*gregs
= bp
->gregs
;
92 struct sbus_dev
*qec_sdev
= bp
->qec_sdev
;
93 u8 bsizes
= bp
->bigmac_bursts
;
96 /* 64byte bursts do not work at the moment, do
97 * not even try to enable them. -DaveM
99 if (bsizes
& DMA_BURST32
)
100 regval
= GLOB_CTRL_B32
;
102 regval
= GLOB_CTRL_B16
;
103 sbus_writel(regval
| GLOB_CTRL_BMODE
, gregs
+ GLOB_CTRL
);
104 sbus_writel(GLOB_PSIZE_2048
, gregs
+ GLOB_PSIZE
);
106 /* All of memsize is given to bigmac. */
107 sbus_writel(qec_sdev
->reg_addrs
[1].reg_size
,
110 /* Half to the transmitter, half to the receiver. */
111 sbus_writel(qec_sdev
->reg_addrs
[1].reg_size
>> 1,
113 sbus_writel(qec_sdev
->reg_addrs
[1].reg_size
>> 1,
117 #define TX_RESET_TRIES 32
118 #define RX_RESET_TRIES 32
120 static void bigmac_tx_reset(void __iomem
*bregs
)
122 int tries
= TX_RESET_TRIES
;
124 sbus_writel(0, bregs
+ BMAC_TXCFG
);
126 /* The fifo threshold bit is read-only and does
129 while ((sbus_readl(bregs
+ BMAC_TXCFG
) & ~(BIGMAC_TXCFG_FIFO
)) != 0 &&
134 printk(KERN_ERR
"BIGMAC: Transmitter will not reset.\n");
135 printk(KERN_ERR
"BIGMAC: tx_cfg is %08x\n",
136 sbus_readl(bregs
+ BMAC_TXCFG
));
140 static void bigmac_rx_reset(void __iomem
*bregs
)
142 int tries
= RX_RESET_TRIES
;
144 sbus_writel(0, bregs
+ BMAC_RXCFG
);
145 while (sbus_readl(bregs
+ BMAC_RXCFG
) && --tries
)
149 printk(KERN_ERR
"BIGMAC: Receiver will not reset.\n");
150 printk(KERN_ERR
"BIGMAC: rx_cfg is %08x\n",
151 sbus_readl(bregs
+ BMAC_RXCFG
));
155 /* Reset the transmitter and receiver. */
156 static void bigmac_stop(struct bigmac
*bp
)
158 bigmac_tx_reset(bp
->bregs
);
159 bigmac_rx_reset(bp
->bregs
);
162 static void bigmac_get_counters(struct bigmac
*bp
, void __iomem
*bregs
)
164 struct net_device_stats
*stats
= &bp
->enet_stats
;
166 stats
->rx_crc_errors
+= sbus_readl(bregs
+ BMAC_RCRCECTR
);
167 sbus_writel(0, bregs
+ BMAC_RCRCECTR
);
169 stats
->rx_frame_errors
+= sbus_readl(bregs
+ BMAC_UNALECTR
);
170 sbus_writel(0, bregs
+ BMAC_UNALECTR
);
172 stats
->rx_length_errors
+= sbus_readl(bregs
+ BMAC_GLECTR
);
173 sbus_writel(0, bregs
+ BMAC_GLECTR
);
175 stats
->tx_aborted_errors
+= sbus_readl(bregs
+ BMAC_EXCTR
);
178 (sbus_readl(bregs
+ BMAC_EXCTR
) +
179 sbus_readl(bregs
+ BMAC_LTCTR
));
180 sbus_writel(0, bregs
+ BMAC_EXCTR
);
181 sbus_writel(0, bregs
+ BMAC_LTCTR
);
184 static void bigmac_clean_rings(struct bigmac
*bp
)
188 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
189 if (bp
->rx_skbs
[i
] != NULL
) {
190 dev_kfree_skb_any(bp
->rx_skbs
[i
]);
191 bp
->rx_skbs
[i
] = NULL
;
195 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
196 if (bp
->tx_skbs
[i
] != NULL
) {
197 dev_kfree_skb_any(bp
->tx_skbs
[i
]);
198 bp
->tx_skbs
[i
] = NULL
;
203 static void bigmac_init_rings(struct bigmac
*bp
, int from_irq
)
205 struct bmac_init_block
*bb
= bp
->bmac_block
;
206 struct net_device
*dev
= bp
->dev
;
207 int i
, gfp_flags
= GFP_KERNEL
;
209 if (from_irq
|| in_interrupt())
210 gfp_flags
= GFP_ATOMIC
;
212 bp
->rx_new
= bp
->rx_old
= bp
->tx_new
= bp
->tx_old
= 0;
214 /* Free any skippy bufs left around in the rings. */
215 bigmac_clean_rings(bp
);
217 /* Now get new skbufs for the receive ring. */
218 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
221 skb
= big_mac_alloc_skb(RX_BUF_ALLOC_SIZE
, gfp_flags
);
225 bp
->rx_skbs
[i
] = skb
;
228 /* Because we reserve afterwards. */
229 skb_put(skb
, ETH_FRAME_LEN
);
230 skb_reserve(skb
, 34);
232 bb
->be_rxd
[i
].rx_addr
=
233 sbus_map_single(bp
->bigmac_sdev
, skb
->data
,
234 RX_BUF_ALLOC_SIZE
- 34,
235 SBUS_DMA_FROMDEVICE
);
236 bb
->be_rxd
[i
].rx_flags
=
237 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
240 for (i
= 0; i
< TX_RING_SIZE
; i
++)
241 bb
->be_txd
[i
].tx_flags
= bb
->be_txd
[i
].tx_addr
= 0;
244 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
245 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
247 static void idle_transceiver(void __iomem
*tregs
)
252 sbus_writel(MGMT_CLKOFF
, tregs
+ TCVR_MPAL
);
253 sbus_readl(tregs
+ TCVR_MPAL
);
254 sbus_writel(MGMT_CLKON
, tregs
+ TCVR_MPAL
);
255 sbus_readl(tregs
+ TCVR_MPAL
);
259 static void write_tcvr_bit(struct bigmac
*bp
, void __iomem
*tregs
, int bit
)
261 if (bp
->tcvr_type
== internal
) {
262 bit
= (bit
& 1) << 3;
263 sbus_writel(bit
| (MGMT_PAL_OENAB
| MGMT_PAL_EXT_MDIO
),
265 sbus_readl(tregs
+ TCVR_MPAL
);
266 sbus_writel(bit
| MGMT_PAL_OENAB
| MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
268 sbus_readl(tregs
+ TCVR_MPAL
);
269 } else if (bp
->tcvr_type
== external
) {
270 bit
= (bit
& 1) << 2;
271 sbus_writel(bit
| MGMT_PAL_INT_MDIO
| MGMT_PAL_OENAB
,
273 sbus_readl(tregs
+ TCVR_MPAL
);
274 sbus_writel(bit
| MGMT_PAL_INT_MDIO
| MGMT_PAL_OENAB
| MGMT_PAL_DCLOCK
,
276 sbus_readl(tregs
+ TCVR_MPAL
);
278 printk(KERN_ERR
"write_tcvr_bit: No transceiver type known!\n");
282 static int read_tcvr_bit(struct bigmac
*bp
, void __iomem
*tregs
)
286 if (bp
->tcvr_type
== internal
) {
287 sbus_writel(MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
288 sbus_readl(tregs
+ TCVR_MPAL
);
289 sbus_writel(MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
291 sbus_readl(tregs
+ TCVR_MPAL
);
292 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_INT_MDIO
) >> 3;
293 } else if (bp
->tcvr_type
== external
) {
294 sbus_writel(MGMT_PAL_INT_MDIO
, tregs
+ TCVR_MPAL
);
295 sbus_readl(tregs
+ TCVR_MPAL
);
296 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
297 sbus_readl(tregs
+ TCVR_MPAL
);
298 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_EXT_MDIO
) >> 2;
300 printk(KERN_ERR
"read_tcvr_bit: No transceiver type known!\n");
305 static int read_tcvr_bit2(struct bigmac
*bp
, void __iomem
*tregs
)
309 if (bp
->tcvr_type
== internal
) {
310 sbus_writel(MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
311 sbus_readl(tregs
+ TCVR_MPAL
);
312 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_INT_MDIO
) >> 3;
313 sbus_writel(MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
314 sbus_readl(tregs
+ TCVR_MPAL
);
315 } else if (bp
->tcvr_type
== external
) {
316 sbus_writel(MGMT_PAL_INT_MDIO
, tregs
+ TCVR_MPAL
);
317 sbus_readl(tregs
+ TCVR_MPAL
);
318 retval
= (sbus_readl(tregs
+ TCVR_MPAL
) & MGMT_PAL_EXT_MDIO
) >> 2;
319 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_DCLOCK
, tregs
+ TCVR_MPAL
);
320 sbus_readl(tregs
+ TCVR_MPAL
);
322 printk(KERN_ERR
"read_tcvr_bit2: No transceiver type known!\n");
327 static void put_tcvr_byte(struct bigmac
*bp
,
334 write_tcvr_bit(bp
, tregs
, ((byte
>> shift
) & 1));
336 } while (shift
>= 0);
339 static void bigmac_tcvr_write(struct bigmac
*bp
, void __iomem
*tregs
,
340 int reg
, unsigned short val
)
346 switch(bp
->tcvr_type
) {
352 printk(KERN_ERR
"bigmac_tcvr_read: Whoops, no known transceiver type.\n");
356 idle_transceiver(tregs
);
357 write_tcvr_bit(bp
, tregs
, 0);
358 write_tcvr_bit(bp
, tregs
, 1);
359 write_tcvr_bit(bp
, tregs
, 0);
360 write_tcvr_bit(bp
, tregs
, 1);
362 put_tcvr_byte(bp
, tregs
,
363 ((bp
->tcvr_type
== internal
) ?
364 BIGMAC_PHY_INTERNAL
: BIGMAC_PHY_EXTERNAL
));
366 put_tcvr_byte(bp
, tregs
, reg
);
368 write_tcvr_bit(bp
, tregs
, 1);
369 write_tcvr_bit(bp
, tregs
, 0);
373 write_tcvr_bit(bp
, tregs
, (val
>> shift
) & 1);
375 } while (shift
>= 0);
378 static unsigned short bigmac_tcvr_read(struct bigmac
*bp
,
382 unsigned short retval
= 0;
385 switch(bp
->tcvr_type
) {
391 printk(KERN_ERR
"bigmac_tcvr_read: Whoops, no known transceiver type.\n");
395 idle_transceiver(tregs
);
396 write_tcvr_bit(bp
, tregs
, 0);
397 write_tcvr_bit(bp
, tregs
, 1);
398 write_tcvr_bit(bp
, tregs
, 1);
399 write_tcvr_bit(bp
, tregs
, 0);
401 put_tcvr_byte(bp
, tregs
,
402 ((bp
->tcvr_type
== internal
) ?
403 BIGMAC_PHY_INTERNAL
: BIGMAC_PHY_EXTERNAL
));
405 put_tcvr_byte(bp
, tregs
, reg
);
407 if (bp
->tcvr_type
== external
) {
410 (void) read_tcvr_bit2(bp
, tregs
);
411 (void) read_tcvr_bit2(bp
, tregs
);
416 tmp
= read_tcvr_bit2(bp
, tregs
);
417 retval
|= ((tmp
& 1) << shift
);
419 } while (shift
>= 0);
421 (void) read_tcvr_bit2(bp
, tregs
);
422 (void) read_tcvr_bit2(bp
, tregs
);
423 (void) read_tcvr_bit2(bp
, tregs
);
427 (void) read_tcvr_bit(bp
, tregs
);
428 (void) read_tcvr_bit(bp
, tregs
);
433 tmp
= read_tcvr_bit(bp
, tregs
);
434 retval
|= ((tmp
& 1) << shift
);
436 } while (shift
>= 0);
438 (void) read_tcvr_bit(bp
, tregs
);
439 (void) read_tcvr_bit(bp
, tregs
);
440 (void) read_tcvr_bit(bp
, tregs
);
445 static void bigmac_tcvr_init(struct bigmac
*bp
)
447 void __iomem
*tregs
= bp
->tregs
;
450 idle_transceiver(tregs
);
451 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_EXT_MDIO
| MGMT_PAL_DCLOCK
,
453 sbus_readl(tregs
+ TCVR_MPAL
);
455 /* Only the bit for the present transceiver (internal or
456 * external) will stick, set them both and see what stays.
458 sbus_writel(MGMT_PAL_INT_MDIO
| MGMT_PAL_EXT_MDIO
, tregs
+ TCVR_MPAL
);
459 sbus_readl(tregs
+ TCVR_MPAL
);
462 mpal
= sbus_readl(tregs
+ TCVR_MPAL
);
463 if (mpal
& MGMT_PAL_EXT_MDIO
) {
464 bp
->tcvr_type
= external
;
465 sbus_writel(~(TCVR_PAL_EXTLBACK
| TCVR_PAL_MSENSE
| TCVR_PAL_LTENABLE
),
467 sbus_readl(tregs
+ TCVR_TPAL
);
468 } else if (mpal
& MGMT_PAL_INT_MDIO
) {
469 bp
->tcvr_type
= internal
;
470 sbus_writel(~(TCVR_PAL_SERIAL
| TCVR_PAL_EXTLBACK
|
471 TCVR_PAL_MSENSE
| TCVR_PAL_LTENABLE
),
473 sbus_readl(tregs
+ TCVR_TPAL
);
475 printk(KERN_ERR
"BIGMAC: AIEEE, neither internal nor "
476 "external MDIO available!\n");
477 printk(KERN_ERR
"BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
478 sbus_readl(tregs
+ TCVR_MPAL
),
479 sbus_readl(tregs
+ TCVR_TPAL
));
483 static int bigmac_init(struct bigmac
*, int);
485 static int try_next_permutation(struct bigmac
*bp
, void __iomem
*tregs
)
487 if (bp
->sw_bmcr
& BMCR_SPEED100
) {
491 bp
->sw_bmcr
= (BMCR_ISOLATE
| BMCR_PDOWN
| BMCR_LOOPBACK
);
492 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
493 bp
->sw_bmcr
= (BMCR_RESET
);
494 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
498 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
499 if ((bp
->sw_bmcr
& BMCR_RESET
) == 0)
504 printk(KERN_ERR
"%s: PHY reset failed.\n", bp
->dev
->name
);
506 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
508 /* Now we try 10baseT. */
509 bp
->sw_bmcr
&= ~(BMCR_SPEED100
);
510 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
514 /* We've tried them all. */
518 static void bigmac_timer(unsigned long data
)
520 struct bigmac
*bp
= (struct bigmac
*) data
;
521 void __iomem
*tregs
= bp
->tregs
;
522 int restart_timer
= 0;
525 if (bp
->timer_state
== ltrywait
) {
526 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMSR
);
527 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
528 if (bp
->sw_bmsr
& BMSR_LSTATUS
) {
529 printk(KERN_INFO
"%s: Link is now up at %s.\n",
531 (bp
->sw_bmcr
& BMCR_SPEED100
) ?
532 "100baseT" : "10baseT");
533 bp
->timer_state
= asleep
;
536 if (bp
->timer_ticks
>= 4) {
539 ret
= try_next_permutation(bp
, tregs
);
541 printk(KERN_ERR
"%s: Link down, cable problem?\n",
543 ret
= bigmac_init(bp
, 0);
545 printk(KERN_ERR
"%s: Error, cannot re-init the "
546 "BigMAC.\n", bp
->dev
->name
);
557 /* Can't happens.... */
558 printk(KERN_ERR
"%s: Aieee, link timer is asleep but we got one anyways!\n",
562 bp
->timer_state
= asleep
; /* foo on you */
565 if (restart_timer
!= 0) {
566 bp
->bigmac_timer
.expires
= jiffies
+ ((12 * HZ
)/10); /* 1.2 sec. */
567 add_timer(&bp
->bigmac_timer
);
571 /* Well, really we just force the chip into 100baseT then
572 * 10baseT, each time checking for a link status.
574 static void bigmac_begin_auto_negotiation(struct bigmac
*bp
)
576 void __iomem
*tregs
= bp
->tregs
;
579 /* Grab new software copies of PHY registers. */
580 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMSR
);
581 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
584 bp
->sw_bmcr
= (BMCR_ISOLATE
| BMCR_PDOWN
| BMCR_LOOPBACK
);
585 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
586 bp
->sw_bmcr
= (BMCR_RESET
);
587 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
591 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
592 if ((bp
->sw_bmcr
& BMCR_RESET
) == 0)
597 printk(KERN_ERR
"%s: PHY reset failed.\n", bp
->dev
->name
);
599 bp
->sw_bmcr
= bigmac_tcvr_read(bp
, tregs
, BIGMAC_BMCR
);
601 /* First we try 100baseT. */
602 bp
->sw_bmcr
|= BMCR_SPEED100
;
603 bigmac_tcvr_write(bp
, tregs
, BIGMAC_BMCR
, bp
->sw_bmcr
);
605 bp
->timer_state
= ltrywait
;
607 bp
->bigmac_timer
.expires
= jiffies
+ (12 * HZ
) / 10;
608 bp
->bigmac_timer
.data
= (unsigned long) bp
;
609 bp
->bigmac_timer
.function
= &bigmac_timer
;
610 add_timer(&bp
->bigmac_timer
);
613 static int bigmac_init(struct bigmac
*bp
, int from_irq
)
615 void __iomem
*gregs
= bp
->gregs
;
616 void __iomem
*cregs
= bp
->creg
;
617 void __iomem
*bregs
= bp
->bregs
;
618 unsigned char *e
= &bp
->dev
->dev_addr
[0];
620 /* Latch current counters into statistics. */
621 bigmac_get_counters(bp
, bregs
);
624 qec_global_reset(gregs
);
629 /* Alloc and reset the tx/rx descriptor chains. */
630 bigmac_init_rings(bp
, from_irq
);
632 /* Initialize the PHY. */
633 bigmac_tcvr_init(bp
);
635 /* Stop transmitter and receiver. */
638 /* Set hardware ethernet address. */
639 sbus_writel(((e
[4] << 8) | e
[5]), bregs
+ BMAC_MACADDR2
);
640 sbus_writel(((e
[2] << 8) | e
[3]), bregs
+ BMAC_MACADDR1
);
641 sbus_writel(((e
[0] << 8) | e
[1]), bregs
+ BMAC_MACADDR0
);
643 /* Clear the hash table until mc upload occurs. */
644 sbus_writel(0, bregs
+ BMAC_HTABLE3
);
645 sbus_writel(0, bregs
+ BMAC_HTABLE2
);
646 sbus_writel(0, bregs
+ BMAC_HTABLE1
);
647 sbus_writel(0, bregs
+ BMAC_HTABLE0
);
649 /* Enable Big Mac hash table filter. */
650 sbus_writel(BIGMAC_RXCFG_HENABLE
| BIGMAC_RXCFG_FIFO
,
654 /* Ok, configure the Big Mac transmitter. */
655 sbus_writel(BIGMAC_TXCFG_FIFO
, bregs
+ BMAC_TXCFG
);
657 /* The HME docs recommend to use the 10LSB of our MAC here. */
658 sbus_writel(((e
[5] | e
[4] << 8) & 0x3ff),
661 /* Enable the output drivers no matter what. */
662 sbus_writel(BIGMAC_XCFG_ODENABLE
| BIGMAC_XCFG_RESV
,
663 bregs
+ BMAC_XIFCFG
);
665 /* Tell the QEC where the ring descriptors are. */
666 sbus_writel(bp
->bblock_dvma
+ bib_offset(be_rxd
, 0),
668 sbus_writel(bp
->bblock_dvma
+ bib_offset(be_txd
, 0),
671 /* Setup the FIFO pointers into QEC local memory. */
672 sbus_writel(0, cregs
+ CREG_RXRBUFPTR
);
673 sbus_writel(0, cregs
+ CREG_RXWBUFPTR
);
674 sbus_writel(sbus_readl(gregs
+ GLOB_RSIZE
),
675 cregs
+ CREG_TXRBUFPTR
);
676 sbus_writel(sbus_readl(gregs
+ GLOB_RSIZE
),
677 cregs
+ CREG_TXWBUFPTR
);
679 /* Tell bigmac what interrupts we don't want to hear about. */
680 sbus_writel(BIGMAC_IMASK_GOTFRAME
| BIGMAC_IMASK_SENTFRAME
,
683 /* Enable the various other irq's. */
684 sbus_writel(0, cregs
+ CREG_RIMASK
);
685 sbus_writel(0, cregs
+ CREG_TIMASK
);
686 sbus_writel(0, cregs
+ CREG_QMASK
);
687 sbus_writel(0, cregs
+ CREG_BMASK
);
689 /* Set jam size to a reasonable default. */
690 sbus_writel(DEFAULT_JAMSIZE
, bregs
+ BMAC_JSIZE
);
692 /* Clear collision counter. */
693 sbus_writel(0, cregs
+ CREG_CCNT
);
695 /* Enable transmitter and receiver. */
696 sbus_writel(sbus_readl(bregs
+ BMAC_TXCFG
) | BIGMAC_TXCFG_ENABLE
,
698 sbus_writel(sbus_readl(bregs
+ BMAC_RXCFG
) | BIGMAC_RXCFG_ENABLE
,
701 /* Ok, start detecting link speed/duplex. */
702 bigmac_begin_auto_negotiation(bp
);
708 /* Error interrupts get sent here. */
709 static void bigmac_is_medium_rare(struct bigmac
*bp
, u32 qec_status
, u32 bmac_status
)
711 printk(KERN_ERR
"bigmac_is_medium_rare: ");
712 if (qec_status
& (GLOB_STAT_ER
| GLOB_STAT_BM
)) {
713 if (qec_status
& GLOB_STAT_ER
)
714 printk("QEC_ERROR, ");
715 if (qec_status
& GLOB_STAT_BM
)
716 printk("QEC_BMAC_ERROR, ");
718 if (bmac_status
& CREG_STAT_ERRORS
) {
719 if (bmac_status
& CREG_STAT_BERROR
)
720 printk("BMAC_ERROR, ");
721 if (bmac_status
& CREG_STAT_TXDERROR
)
722 printk("TXD_ERROR, ");
723 if (bmac_status
& CREG_STAT_TXLERR
)
724 printk("TX_LATE_ERROR, ");
725 if (bmac_status
& CREG_STAT_TXPERR
)
726 printk("TX_PARITY_ERROR, ");
727 if (bmac_status
& CREG_STAT_TXSERR
)
728 printk("TX_SBUS_ERROR, ");
730 if (bmac_status
& CREG_STAT_RXDROP
)
731 printk("RX_DROP_ERROR, ");
733 if (bmac_status
& CREG_STAT_RXSMALL
)
734 printk("RX_SMALL_ERROR, ");
735 if (bmac_status
& CREG_STAT_RXLERR
)
736 printk("RX_LATE_ERROR, ");
737 if (bmac_status
& CREG_STAT_RXPERR
)
738 printk("RX_PARITY_ERROR, ");
739 if (bmac_status
& CREG_STAT_RXSERR
)
740 printk("RX_SBUS_ERROR, ");
747 /* BigMAC transmit complete service routines. */
748 static void bigmac_tx(struct bigmac
*bp
)
750 struct be_txd
*txbase
= &bp
->bmac_block
->be_txd
[0];
751 struct net_device
*dev
= bp
->dev
;
754 spin_lock(&bp
->lock
);
757 DTX(("bigmac_tx: tx_old[%d] ", elem
));
758 while (elem
!= bp
->tx_new
) {
760 struct be_txd
*this = &txbase
[elem
];
762 DTX(("this(%p) [flags(%08x)addr(%08x)]",
763 this, this->tx_flags
, this->tx_addr
));
765 if (this->tx_flags
& TXD_OWN
)
767 skb
= bp
->tx_skbs
[elem
];
768 bp
->enet_stats
.tx_packets
++;
769 bp
->enet_stats
.tx_bytes
+= skb
->len
;
770 sbus_unmap_single(bp
->bigmac_sdev
,
771 this->tx_addr
, skb
->len
,
774 DTX(("skb(%p) ", skb
));
775 bp
->tx_skbs
[elem
] = NULL
;
776 dev_kfree_skb_irq(skb
);
778 elem
= NEXT_TX(elem
);
780 DTX((" DONE, tx_old=%d\n", elem
));
783 if (netif_queue_stopped(dev
) &&
784 TX_BUFFS_AVAIL(bp
) > 0)
785 netif_wake_queue(bp
->dev
);
787 spin_unlock(&bp
->lock
);
790 /* BigMAC receive complete service routines. */
791 static void bigmac_rx(struct bigmac
*bp
)
793 struct be_rxd
*rxbase
= &bp
->bmac_block
->be_rxd
[0];
795 int elem
= bp
->rx_new
, drops
= 0;
798 this = &rxbase
[elem
];
799 while (!((flags
= this->rx_flags
) & RXD_OWN
)) {
801 int len
= (flags
& RXD_LENGTH
); /* FCS not included */
803 /* Check for errors. */
804 if (len
< ETH_ZLEN
) {
805 bp
->enet_stats
.rx_errors
++;
806 bp
->enet_stats
.rx_length_errors
++;
809 /* Return it to the BigMAC. */
810 bp
->enet_stats
.rx_dropped
++;
812 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
815 skb
= bp
->rx_skbs
[elem
];
816 if (len
> RX_COPY_THRESHOLD
) {
817 struct sk_buff
*new_skb
;
819 /* Now refill the entry, if we can. */
820 new_skb
= big_mac_alloc_skb(RX_BUF_ALLOC_SIZE
, GFP_ATOMIC
);
821 if (new_skb
== NULL
) {
825 sbus_unmap_single(bp
->bigmac_sdev
,
827 RX_BUF_ALLOC_SIZE
- 34,
828 SBUS_DMA_FROMDEVICE
);
829 bp
->rx_skbs
[elem
] = new_skb
;
830 new_skb
->dev
= bp
->dev
;
831 skb_put(new_skb
, ETH_FRAME_LEN
);
832 skb_reserve(new_skb
, 34);
833 this->rx_addr
= sbus_map_single(bp
->bigmac_sdev
,
835 RX_BUF_ALLOC_SIZE
- 34,
836 SBUS_DMA_FROMDEVICE
);
838 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
840 /* Trim the original skb for the netif. */
843 struct sk_buff
*copy_skb
= dev_alloc_skb(len
+ 2);
845 if (copy_skb
== NULL
) {
849 copy_skb
->dev
= bp
->dev
;
850 skb_reserve(copy_skb
, 2);
851 skb_put(copy_skb
, len
);
852 sbus_dma_sync_single_for_cpu(bp
->bigmac_sdev
,
854 SBUS_DMA_FROMDEVICE
);
855 eth_copy_and_sum(copy_skb
, (unsigned char *)skb
->data
, len
, 0);
856 sbus_dma_sync_single_for_device(bp
->bigmac_sdev
,
858 SBUS_DMA_FROMDEVICE
);
860 /* Reuse original ring buffer. */
862 (RXD_OWN
| ((RX_BUF_ALLOC_SIZE
- 34) & RXD_LENGTH
));
867 /* No checksums done by the BigMAC ;-( */
868 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
870 bp
->dev
->last_rx
= jiffies
;
871 bp
->enet_stats
.rx_packets
++;
872 bp
->enet_stats
.rx_bytes
+= len
;
874 elem
= NEXT_RX(elem
);
875 this = &rxbase
[elem
];
879 printk(KERN_NOTICE
"%s: Memory squeeze, deferring packet.\n", bp
->dev
->name
);
882 static irqreturn_t
bigmac_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
884 struct bigmac
*bp
= (struct bigmac
*) dev_id
;
885 u32 qec_status
, bmac_status
;
887 DIRQ(("bigmac_interrupt: "));
889 /* Latch status registers now. */
890 bmac_status
= sbus_readl(bp
->creg
+ CREG_STAT
);
891 qec_status
= sbus_readl(bp
->gregs
+ GLOB_STAT
);
893 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status
, bmac_status
));
894 if ((qec_status
& (GLOB_STAT_ER
| GLOB_STAT_BM
)) ||
895 (bmac_status
& CREG_STAT_ERRORS
))
896 bigmac_is_medium_rare(bp
, qec_status
, bmac_status
);
898 if (bmac_status
& CREG_STAT_TXIRQ
)
901 if (bmac_status
& CREG_STAT_RXIRQ
)
907 static int bigmac_open(struct net_device
*dev
)
909 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
912 ret
= request_irq(dev
->irq
, &bigmac_interrupt
, SA_SHIRQ
, dev
->name
, bp
);
914 printk(KERN_ERR
"BIGMAC: Can't order irq %d to go.\n", dev
->irq
);
917 init_timer(&bp
->bigmac_timer
);
918 ret
= bigmac_init(bp
, 0);
920 free_irq(dev
->irq
, bp
);
924 static int bigmac_close(struct net_device
*dev
)
926 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
928 del_timer(&bp
->bigmac_timer
);
929 bp
->timer_state
= asleep
;
933 bigmac_clean_rings(bp
);
934 free_irq(dev
->irq
, bp
);
938 static void bigmac_tx_timeout(struct net_device
*dev
)
940 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
943 netif_wake_queue(dev
);
946 /* Put a packet on the wire. */
947 static int bigmac_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
949 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
954 mapping
= sbus_map_single(bp
->bigmac_sdev
, skb
->data
, len
, SBUS_DMA_TODEVICE
);
956 /* Avoid a race... */
957 spin_lock_irq(&bp
->lock
);
959 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len
, entry
));
960 bp
->bmac_block
->be_txd
[entry
].tx_flags
= TXD_UPDATE
;
961 bp
->tx_skbs
[entry
] = skb
;
962 bp
->bmac_block
->be_txd
[entry
].tx_addr
= mapping
;
963 bp
->bmac_block
->be_txd
[entry
].tx_flags
=
964 (TXD_OWN
| TXD_SOP
| TXD_EOP
| (len
& TXD_LENGTH
));
965 bp
->tx_new
= NEXT_TX(entry
);
966 if (TX_BUFFS_AVAIL(bp
) <= 0)
967 netif_stop_queue(dev
);
968 spin_unlock_irq(&bp
->lock
);
971 sbus_writel(CREG_CTRL_TWAKEUP
, bp
->creg
+ CREG_CTRL
);
974 dev
->trans_start
= jiffies
;
979 static struct net_device_stats
*bigmac_get_stats(struct net_device
*dev
)
981 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
983 bigmac_get_counters(bp
, bp
->bregs
);
984 return &bp
->enet_stats
;
987 static void bigmac_set_multicast(struct net_device
*dev
)
989 struct bigmac
*bp
= (struct bigmac
*) dev
->priv
;
990 void __iomem
*bregs
= bp
->bregs
;
991 struct dev_mc_list
*dmi
= dev
->mc_list
;
996 /* Disable the receiver. The bit self-clears when
997 * the operation is complete.
999 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1000 tmp
&= ~(BIGMAC_RXCFG_ENABLE
);
1001 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1002 while ((sbus_readl(bregs
+ BMAC_RXCFG
) & BIGMAC_RXCFG_ENABLE
) != 0)
1005 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 64)) {
1006 sbus_writel(0xffff, bregs
+ BMAC_HTABLE0
);
1007 sbus_writel(0xffff, bregs
+ BMAC_HTABLE1
);
1008 sbus_writel(0xffff, bregs
+ BMAC_HTABLE2
);
1009 sbus_writel(0xffff, bregs
+ BMAC_HTABLE3
);
1010 } else if (dev
->flags
& IFF_PROMISC
) {
1011 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1012 tmp
|= BIGMAC_RXCFG_PMISC
;
1013 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1017 for (i
= 0; i
< 4; i
++)
1020 for (i
= 0; i
< dev
->mc_count
; i
++) {
1021 addrs
= dmi
->dmi_addr
;
1027 crc
= ether_crc_le(6, addrs
);
1029 hash_table
[crc
>> 4] |= 1 << (crc
& 0xf);
1031 sbus_writel(hash_table
[0], bregs
+ BMAC_HTABLE0
);
1032 sbus_writel(hash_table
[1], bregs
+ BMAC_HTABLE1
);
1033 sbus_writel(hash_table
[2], bregs
+ BMAC_HTABLE2
);
1034 sbus_writel(hash_table
[3], bregs
+ BMAC_HTABLE3
);
1037 /* Re-enable the receiver. */
1038 tmp
= sbus_readl(bregs
+ BMAC_RXCFG
);
1039 tmp
|= BIGMAC_RXCFG_ENABLE
;
1040 sbus_writel(tmp
, bregs
+ BMAC_RXCFG
);
1043 /* Ethtool support... */
1044 static void bigmac_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1046 struct bigmac
*bp
= dev
->priv
;
1048 strcpy(info
->driver
, "sunbmac");
1049 strcpy(info
->version
, "2.0");
1050 sprintf(info
->bus_info
, "SBUS:%d",
1051 bp
->qec_sdev
->slot
);
1054 static u32
bigmac_get_link(struct net_device
*dev
)
1056 struct bigmac
*bp
= dev
->priv
;
1058 spin_lock_irq(&bp
->lock
);
1059 bp
->sw_bmsr
= bigmac_tcvr_read(bp
, bp
->tregs
, BIGMAC_BMSR
);
1060 spin_unlock_irq(&bp
->lock
);
1062 return (bp
->sw_bmsr
& BMSR_LSTATUS
);
1065 static struct ethtool_ops bigmac_ethtool_ops
= {
1066 .get_drvinfo
= bigmac_get_drvinfo
,
1067 .get_link
= bigmac_get_link
,
1070 static int __init
bigmac_ether_init(struct sbus_dev
*qec_sdev
)
1072 struct net_device
*dev
;
1073 static int version_printed
;
1075 u8 bsizes
, bsizes_more
;
1078 /* Get a new device struct for this interface. */
1079 dev
= alloc_etherdev(sizeof(struct bigmac
));
1082 SET_MODULE_OWNER(dev
);
1084 if (version_printed
++ == 0)
1085 printk(KERN_INFO
"%s", version
);
1087 dev
->base_addr
= (long) qec_sdev
;
1088 for (i
= 0; i
< 6; i
++)
1089 dev
->dev_addr
[i
] = idprom
->id_ethaddr
[i
];
1091 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1093 bp
->qec_sdev
= qec_sdev
;
1094 bp
->bigmac_sdev
= qec_sdev
->child
;
1096 spin_lock_init(&bp
->lock
);
1098 /* Verify the registers we expect, are actually there. */
1099 if ((bp
->bigmac_sdev
->num_registers
!= 3) ||
1100 (bp
->qec_sdev
->num_registers
!= 2)) {
1101 printk(KERN_ERR
"BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1102 bp
->qec_sdev
->num_registers
,
1103 bp
->bigmac_sdev
->num_registers
);
1104 printk(KERN_ERR
"BIGMAC: Would you like that for here or to go?\n");
1105 goto fail_and_cleanup
;
1108 /* Map in QEC global control registers. */
1109 bp
->gregs
= sbus_ioremap(&bp
->qec_sdev
->resource
[0], 0,
1110 GLOB_REG_SIZE
, "BigMAC QEC GLobal Regs");
1112 printk(KERN_ERR
"BIGMAC: Cannot map QEC global registers.\n");
1113 goto fail_and_cleanup
;
1116 /* Make sure QEC is in BigMAC mode. */
1117 if ((sbus_readl(bp
->gregs
+ GLOB_CTRL
) & 0xf0000000) != GLOB_CTRL_BMODE
) {
1118 printk(KERN_ERR
"BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1119 goto fail_and_cleanup
;
1122 /* Reset the QEC. */
1123 if (qec_global_reset(bp
->gregs
))
1124 goto fail_and_cleanup
;
1126 /* Get supported SBUS burst sizes. */
1127 bsizes
= prom_getintdefault(bp
->qec_sdev
->prom_node
,
1131 bsizes_more
= prom_getintdefault(bp
->qec_sdev
->bus
->prom_node
,
1136 if (bsizes_more
!= 0xff)
1137 bsizes
&= bsizes_more
;
1138 if (bsizes
== 0xff || (bsizes
& DMA_BURST16
) == 0 ||
1139 (bsizes
& DMA_BURST32
) == 0)
1140 bsizes
= (DMA_BURST32
- 1);
1141 bp
->bigmac_bursts
= bsizes
;
1143 /* Perform QEC initialization. */
1146 /* Map in the BigMAC channel registers. */
1147 bp
->creg
= sbus_ioremap(&bp
->bigmac_sdev
->resource
[0], 0,
1148 CREG_REG_SIZE
, "BigMAC QEC Channel Regs");
1150 printk(KERN_ERR
"BIGMAC: Cannot map QEC channel registers.\n");
1151 goto fail_and_cleanup
;
1154 /* Map in the BigMAC control registers. */
1155 bp
->bregs
= sbus_ioremap(&bp
->bigmac_sdev
->resource
[1], 0,
1156 BMAC_REG_SIZE
, "BigMAC Primary Regs");
1158 printk(KERN_ERR
"BIGMAC: Cannot map BigMAC primary registers.\n");
1159 goto fail_and_cleanup
;
1162 /* Map in the BigMAC transceiver registers, this is how you poke at
1165 bp
->tregs
= sbus_ioremap(&bp
->bigmac_sdev
->resource
[2], 0,
1166 TCVR_REG_SIZE
, "BigMAC Transceiver Regs");
1168 printk(KERN_ERR
"BIGMAC: Cannot map BigMAC transceiver registers.\n");
1169 goto fail_and_cleanup
;
1172 /* Stop the BigMAC. */
1175 /* Allocate transmit/receive descriptor DVMA block. */
1176 bp
->bmac_block
= sbus_alloc_consistent(bp
->bigmac_sdev
,
1179 if (bp
->bmac_block
== NULL
|| bp
->bblock_dvma
== 0) {
1180 printk(KERN_ERR
"BIGMAC: Cannot allocate consistent DMA.\n");
1181 goto fail_and_cleanup
;
1184 /* Get the board revision of this BigMAC. */
1185 bp
->board_rev
= prom_getintdefault(bp
->bigmac_sdev
->prom_node
,
1186 "board-version", 1);
1188 /* Init auto-negotiation timer state. */
1189 init_timer(&bp
->bigmac_timer
);
1190 bp
->timer_state
= asleep
;
1191 bp
->timer_ticks
= 0;
1193 /* Backlink to generic net device struct. */
1196 /* Set links to our BigMAC open and close routines. */
1197 dev
->open
= &bigmac_open
;
1198 dev
->stop
= &bigmac_close
;
1199 dev
->hard_start_xmit
= &bigmac_start_xmit
;
1200 dev
->ethtool_ops
= &bigmac_ethtool_ops
;
1202 /* Set links to BigMAC statistic and multi-cast loading code. */
1203 dev
->get_stats
= &bigmac_get_stats
;
1204 dev
->set_multicast_list
= &bigmac_set_multicast
;
1206 dev
->tx_timeout
= &bigmac_tx_timeout
;
1207 dev
->watchdog_timeo
= 5*HZ
;
1209 /* Finish net device registration. */
1210 dev
->irq
= bp
->bigmac_sdev
->irqs
[0];
1213 if (register_netdev(dev
)) {
1214 printk(KERN_ERR
"BIGMAC: Cannot register device.\n");
1215 goto fail_and_cleanup
;
1218 /* Put us into the list of instances attached for later driver
1221 bp
->next_module
= root_bigmac_dev
;
1222 root_bigmac_dev
= bp
;
1224 printk(KERN_INFO
"%s: BigMAC 100baseT Ethernet ", dev
->name
);
1225 for (i
= 0; i
< 6; i
++)
1226 printk("%2.2x%c", dev
->dev_addr
[i
],
1227 i
== 5 ? ' ' : ':');
1233 /* Something went wrong, undo whatever we did so far. */
1234 /* Free register mappings if any. */
1236 sbus_iounmap(bp
->gregs
, GLOB_REG_SIZE
);
1238 sbus_iounmap(bp
->creg
, CREG_REG_SIZE
);
1240 sbus_iounmap(bp
->bregs
, BMAC_REG_SIZE
);
1242 sbus_iounmap(bp
->tregs
, TCVR_REG_SIZE
);
1245 sbus_free_consistent(bp
->bigmac_sdev
,
1250 /* This also frees the co-located 'dev->priv' */
1255 /* QEC can be the parent of either QuadEthernet or
1256 * a BigMAC. We want the latter.
1258 static int __init
bigmac_match(struct sbus_dev
*sdev
)
1260 struct sbus_dev
*child
= sdev
->child
;
1262 if (strcmp(sdev
->prom_name
, "qec") != 0)
1268 if (strcmp(child
->prom_name
, "be") != 0)
1274 static int __init
bigmac_probe(void)
1276 struct sbus_bus
*sbus
;
1277 struct sbus_dev
*sdev
= NULL
;
1281 root_bigmac_dev
= NULL
;
1287 for_each_sbus(sbus
) {
1288 for_each_sbusdev(sdev
, sbus
) {
1289 if (bigmac_match(sdev
)) {
1291 if ((v
= bigmac_ether_init(sdev
)))
1301 static void __exit
bigmac_cleanup(void)
1303 while (root_bigmac_dev
) {
1304 struct bigmac
*bp
= root_bigmac_dev
;
1305 struct bigmac
*bp_nxt
= root_bigmac_dev
->next_module
;
1307 sbus_iounmap(bp
->gregs
, GLOB_REG_SIZE
);
1308 sbus_iounmap(bp
->creg
, CREG_REG_SIZE
);
1309 sbus_iounmap(bp
->bregs
, BMAC_REG_SIZE
);
1310 sbus_iounmap(bp
->tregs
, TCVR_REG_SIZE
);
1311 sbus_free_consistent(bp
->bigmac_sdev
,
1316 unregister_netdev(bp
->dev
);
1317 free_netdev(bp
->dev
);
1318 root_bigmac_dev
= bp_nxt
;
1322 module_init(bigmac_probe
);
1323 module_exit(bigmac_cleanup
);
1324 MODULE_LICENSE("GPL");