2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid
= -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid
;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map
;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
78 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic
;
90 * APIC command line parameters
92 static int __init
parse_lapic(char *arg
)
94 force_enable_local_apic
= 1;
97 early_param("lapic", parse_lapic
);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase
;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline void imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline void imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata
;
128 static __init
int setup_apicpmtimer(char *s
)
130 apic_calibrate_pmtmr
= 1;
134 __setup("apicpmtimer", setup_apicpmtimer
);
137 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled
;
141 static int disable_x2apic
;
142 static __init
int setup_nox2apic(char *str
)
144 if (x2apic_enabled())
145 panic("Bios already enabled x2apic, can't enforce nox2apic");
147 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
150 early_param("nox2apic", setup_nox2apic
);
153 unsigned long mp_lapic_addr
;
155 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
156 static int disable_apic_timer __cpuinitdata
;
157 /* Local APIC timer works in C2 */
158 int local_apic_timer_c2_ok
;
159 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
161 int first_system_vector
= 0xfe;
164 * Debug level, exported for io_apic.c
166 unsigned int apic_verbosity
;
170 /* Have we found an MP table */
171 int smp_found_config
;
173 static struct resource lapic_resource
= {
174 .name
= "Local APIC",
175 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
178 static unsigned int calibration_result
;
180 static int lapic_next_event(unsigned long delta
,
181 struct clock_event_device
*evt
);
182 static void lapic_timer_setup(enum clock_event_mode mode
,
183 struct clock_event_device
*evt
);
184 static void lapic_timer_broadcast(const struct cpumask
*mask
);
185 static void apic_pm_activate(void);
188 * The local apic timer can be used for any function which is CPU local.
190 static struct clock_event_device lapic_clockevent
= {
192 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
193 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
195 .set_mode
= lapic_timer_setup
,
196 .set_next_event
= lapic_next_event
,
197 .broadcast
= lapic_timer_broadcast
,
201 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
203 static unsigned long apic_phys
;
206 * Get the LAPIC version
208 static inline int lapic_get_version(void)
210 return GET_APIC_VERSION(apic_read(APIC_LVR
));
214 * Check, if the APIC is integrated or a separate chip
216 static inline int lapic_is_integrated(void)
221 return APIC_INTEGRATED(lapic_get_version());
226 * Check, whether this is a modern or a first generation APIC
228 static int modern_apic(void)
230 /* AMD systems use old APIC versions, so check the CPU */
231 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
232 boot_cpu_data
.x86
>= 0xf)
234 return lapic_get_version() >= 0x14;
238 * bare function to substitute write operation
239 * and it's _that_ fast :)
241 void native_apic_write_dummy(u32 reg
, u32 v
)
243 WARN_ON_ONCE((cpu_has_apic
|| !disable_apic
));
247 * right after this call apic->write doesn't do anything
248 * note that there is no restore operation it works one way
250 void apic_disable(void)
252 apic
->write
= native_apic_write_dummy
;
255 void native_apic_wait_icr_idle(void)
257 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
261 u32
native_safe_apic_wait_icr_idle(void)
268 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
272 } while (timeout
++ < 1000);
277 void native_apic_icr_write(u32 low
, u32 id
)
279 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
280 apic_write(APIC_ICR
, low
);
283 u64
native_apic_icr_read(void)
287 icr2
= apic_read(APIC_ICR2
);
288 icr1
= apic_read(APIC_ICR
);
290 return icr1
| ((u64
)icr2
<< 32);
294 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
296 void __cpuinit
enable_NMI_through_LVT0(void)
300 /* unmask and set to NMI */
303 /* Level triggered for 82489DX (32bit mode) */
304 if (!lapic_is_integrated())
305 v
|= APIC_LVT_LEVEL_TRIGGER
;
307 apic_write(APIC_LVT0
, v
);
312 * get_physical_broadcast - Get number of physical broadcast IDs
314 int get_physical_broadcast(void)
316 return modern_apic() ? 0xff : 0xf;
321 * lapic_get_maxlvt - get the maximum number of local vector table entries
323 int lapic_get_maxlvt(void)
327 v
= apic_read(APIC_LVR
);
329 * - we always have APIC integrated on 64bit mode
330 * - 82489DXs do not report # of LVT entries
332 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
340 #define APIC_DIVISOR 16
343 * This function sets up the local APIC timer, with a timeout of
344 * 'clocks' APIC bus clock. During calibration we actually call
345 * this function twice on the boot CPU, once with a bogus timeout
346 * value, second time for real. The other (noncalibrating) CPUs
347 * call this function only once, with the real, calibrated value.
349 * We do reads before writes even if unnecessary, to get around the
350 * P5 APIC double write bug.
352 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
354 unsigned int lvtt_value
, tmp_value
;
356 lvtt_value
= LOCAL_TIMER_VECTOR
;
358 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
359 if (!lapic_is_integrated())
360 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
363 lvtt_value
|= APIC_LVT_MASKED
;
365 apic_write(APIC_LVTT
, lvtt_value
);
370 tmp_value
= apic_read(APIC_TDCR
);
371 apic_write(APIC_TDCR
,
372 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
376 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
380 * Setup extended LVT, AMD specific (K8, family 10h)
382 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
383 * MCE interrupts are supported. Thus MCE offset must be set to 0.
385 * If mask=1, the LVT entry does not generate interrupts while mask=0
386 * enables the vector. See also the BKDGs.
389 #define APIC_EILVT_LVTOFF_MCE 0
390 #define APIC_EILVT_LVTOFF_IBS 1
392 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
394 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
395 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
400 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
402 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
403 return APIC_EILVT_LVTOFF_MCE
;
406 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
408 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
409 return APIC_EILVT_LVTOFF_IBS
;
411 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
414 * Program the next event, relative to now
416 static int lapic_next_event(unsigned long delta
,
417 struct clock_event_device
*evt
)
419 apic_write(APIC_TMICT
, delta
);
424 * Setup the lapic timer in periodic or oneshot mode
426 static void lapic_timer_setup(enum clock_event_mode mode
,
427 struct clock_event_device
*evt
)
432 /* Lapic used as dummy for broadcast ? */
433 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
436 local_irq_save(flags
);
439 case CLOCK_EVT_MODE_PERIODIC
:
440 case CLOCK_EVT_MODE_ONESHOT
:
441 __setup_APIC_LVTT(calibration_result
,
442 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
444 case CLOCK_EVT_MODE_UNUSED
:
445 case CLOCK_EVT_MODE_SHUTDOWN
:
446 v
= apic_read(APIC_LVTT
);
447 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
448 apic_write(APIC_LVTT
, v
);
449 apic_write(APIC_TMICT
, 0xffffffff);
451 case CLOCK_EVT_MODE_RESUME
:
452 /* Nothing to do here */
456 local_irq_restore(flags
);
460 * Local APIC timer broadcast function
462 static void lapic_timer_broadcast(const struct cpumask
*mask
)
465 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
470 * Setup the local APIC timer for this CPU. Copy the initilized values
471 * of the boot CPU and register the clock event in the framework.
473 static void __cpuinit
setup_APIC_timer(void)
475 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
477 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
478 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
479 /* Make LAPIC timer preferrable over percpu HPET */
480 lapic_clockevent
.rating
= 150;
483 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
484 levt
->cpumask
= cpumask_of(smp_processor_id());
486 clockevents_register_device(levt
);
490 * In this functions we calibrate APIC bus clocks to the external timer.
492 * We want to do the calibration only once since we want to have local timer
493 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
496 * This was previously done by reading the PIT/HPET and waiting for a wrap
497 * around to find out, that a tick has elapsed. I have a box, where the PIT
498 * readout is broken, so it never gets out of the wait loop again. This was
499 * also reported by others.
501 * Monitoring the jiffies value is inaccurate and the clockevents
502 * infrastructure allows us to do a simple substitution of the interrupt
505 * The calibration routine also uses the pm_timer when possible, as the PIT
506 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
507 * back to normal later in the boot process).
510 #define LAPIC_CAL_LOOPS (HZ/10)
512 static __initdata
int lapic_cal_loops
= -1;
513 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
514 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
515 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
516 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
519 * Temporary interrupt handler.
521 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
523 unsigned long long tsc
= 0;
524 long tapic
= apic_read(APIC_TMCCT
);
525 unsigned long pm
= acpi_pm_read_early();
530 switch (lapic_cal_loops
++) {
532 lapic_cal_t1
= tapic
;
533 lapic_cal_tsc1
= tsc
;
535 lapic_cal_j1
= jiffies
;
538 case LAPIC_CAL_LOOPS
:
539 lapic_cal_t2
= tapic
;
540 lapic_cal_tsc2
= tsc
;
541 if (pm
< lapic_cal_pm1
)
542 pm
+= ACPI_PM_OVRRUN
;
544 lapic_cal_j2
= jiffies
;
550 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
552 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
553 const long pm_thresh
= pm_100ms
/ 100;
557 #ifndef CONFIG_X86_PM_TIMER
561 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
563 /* Check, if the PM timer is available */
567 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
569 if (deltapm
> (pm_100ms
- pm_thresh
) &&
570 deltapm
< (pm_100ms
+ pm_thresh
)) {
571 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
575 res
= (((u64
)deltapm
) * mult
) >> 22;
576 do_div(res
, 1000000);
577 pr_warning("APIC calibration not consistent "
578 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
580 /* Correct the lapic counter value */
581 res
= (((u64
)(*delta
)) * pm_100ms
);
582 do_div(res
, deltapm
);
583 pr_info("APIC delta adjusted to PM-Timer: "
584 "%lu (%ld)\n", (unsigned long)res
, *delta
);
587 /* Correct the tsc counter value */
589 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
590 do_div(res
, deltapm
);
591 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
592 "PM-Timer: %lu (%ld) \n",
593 (unsigned long)res
, *deltatsc
);
594 *deltatsc
= (long)res
;
600 static int __init
calibrate_APIC_clock(void)
602 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
603 void (*real_handler
)(struct clock_event_device
*dev
);
604 unsigned long deltaj
;
605 long delta
, deltatsc
;
606 int pm_referenced
= 0;
610 /* Replace the global interrupt handler */
611 real_handler
= global_clock_event
->event_handler
;
612 global_clock_event
->event_handler
= lapic_cal_handler
;
615 * Setup the APIC counter to maximum. There is no way the lapic
616 * can underflow in the 100ms detection time frame
618 __setup_APIC_LVTT(0xffffffff, 0, 0);
620 /* Let the interrupts run */
623 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
628 /* Restore the real event handler */
629 global_clock_event
->event_handler
= real_handler
;
631 /* Build delta t1-t2 as apic timer counts down */
632 delta
= lapic_cal_t1
- lapic_cal_t2
;
633 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
635 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
637 /* we trust the PM based calibration if possible */
638 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
641 /* Calculate the scaled math multiplication factor */
642 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
643 lapic_clockevent
.shift
);
644 lapic_clockevent
.max_delta_ns
=
645 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
646 lapic_clockevent
.min_delta_ns
=
647 clockevent_delta2ns(0xF, &lapic_clockevent
);
649 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
651 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
652 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
653 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
657 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
659 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
660 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
663 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
665 calibration_result
/ (1000000 / HZ
),
666 calibration_result
% (1000000 / HZ
));
669 * Do a sanity check on the APIC calibration result
671 if (calibration_result
< (1000000 / HZ
)) {
673 pr_warning("APIC frequency too slow, disabling apic timer\n");
677 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
680 * PM timer calibration failed or not turned on
681 * so lets try APIC timer based calibration
683 if (!pm_referenced
) {
684 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
687 * Setup the apic timer manually
689 levt
->event_handler
= lapic_cal_handler
;
690 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
691 lapic_cal_loops
= -1;
693 /* Let the interrupts run */
696 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
699 /* Stop the lapic timer */
700 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
703 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
704 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
706 /* Check, if the jiffies result is consistent */
707 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
708 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
710 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
714 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
715 pr_warning("APIC timer disabled due to verification failure\n");
723 * Setup the boot APIC
725 * Calibrate and verify the result.
727 void __init
setup_boot_APIC_clock(void)
730 * The local apic timer can be disabled via the kernel
731 * commandline or from the CPU detection code. Register the lapic
732 * timer as a dummy clock event source on SMP systems, so the
733 * broadcast mechanism is used. On UP systems simply ignore it.
735 if (disable_apic_timer
) {
736 pr_info("Disabling APIC timer\n");
737 /* No broadcast on UP ! */
738 if (num_possible_cpus() > 1) {
739 lapic_clockevent
.mult
= 1;
745 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
746 "calibrating APIC timer ...\n");
748 if (calibrate_APIC_clock()) {
749 /* No broadcast on UP ! */
750 if (num_possible_cpus() > 1)
756 * If nmi_watchdog is set to IO_APIC, we need the
757 * PIT/HPET going. Otherwise register lapic as a dummy
760 if (nmi_watchdog
!= NMI_IO_APIC
)
761 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
763 pr_warning("APIC timer registered as dummy,"
764 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
766 /* Setup the lapic or request the broadcast */
770 void __cpuinit
setup_secondary_APIC_clock(void)
776 * The guts of the apic timer interrupt
778 static void local_apic_timer_interrupt(void)
780 int cpu
= smp_processor_id();
781 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
784 * Normally we should not be here till LAPIC has been initialized but
785 * in some cases like kdump, its possible that there is a pending LAPIC
786 * timer interrupt from previous kernel's context and is delivered in
787 * new kernel the moment interrupts are enabled.
789 * Interrupts are enabled early and LAPIC is setup much later, hence
790 * its possible that when we get here evt->event_handler is NULL.
791 * Check for event_handler being NULL and discard the interrupt as
794 if (!evt
->event_handler
) {
795 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
797 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
802 * the NMI deadlock-detector uses this.
804 inc_irq_stat(apic_timer_irqs
);
806 evt
->event_handler(evt
);
810 * Local APIC timer interrupt. This is the most natural way for doing
811 * local interrupts, but local timer interrupts can be emulated by
812 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
814 * [ if a single-CPU system runs an SMP kernel then we call the local
815 * interrupt as well. Thus we cannot inline the local irq ... ]
817 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
819 struct pt_regs
*old_regs
= set_irq_regs(regs
);
822 * NOTE! We'd better ACK the irq immediately,
823 * because timer handling can be slow.
827 * update_process_times() expects us to have done irq_enter().
828 * Besides, if we don't timer interrupts ignore the global
829 * interrupt lock, which is the WrongThing (tm) to do.
833 local_apic_timer_interrupt();
836 set_irq_regs(old_regs
);
839 int setup_profiling_timer(unsigned int multiplier
)
845 * Local APIC start and shutdown
849 * clear_local_APIC - shutdown the local APIC
851 * This is called, when a CPU is disabled and before rebooting, so the state of
852 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
853 * leftovers during boot.
855 void clear_local_APIC(void)
860 /* APIC hasn't been mapped yet */
861 if (!x2apic
&& !apic_phys
)
864 maxlvt
= lapic_get_maxlvt();
866 * Masking an LVT entry can trigger a local APIC error
867 * if the vector is zero. Mask LVTERR first to prevent this.
870 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
871 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
874 * Careful: we have to set masks only first to deassert
875 * any level-triggered sources.
877 v
= apic_read(APIC_LVTT
);
878 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
879 v
= apic_read(APIC_LVT0
);
880 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
881 v
= apic_read(APIC_LVT1
);
882 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
884 v
= apic_read(APIC_LVTPC
);
885 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
888 /* lets not touch this if we didn't frob it */
889 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
891 v
= apic_read(APIC_LVTTHMR
);
892 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
895 #ifdef CONFIG_X86_MCE_INTEL
897 v
= apic_read(APIC_LVTCMCI
);
898 if (!(v
& APIC_LVT_MASKED
))
899 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
904 * Clean APIC state for other OSs:
906 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
907 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
908 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
910 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
912 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
914 /* Integrated APIC (!82489DX) ? */
915 if (lapic_is_integrated()) {
917 /* Clear ESR due to Pentium errata 3AP and 11AP */
918 apic_write(APIC_ESR
, 0);
924 * disable_local_APIC - clear and disable the local APIC
926 void disable_local_APIC(void)
930 /* APIC hasn't been mapped yet */
937 * Disable APIC (implies clearing of registers
940 value
= apic_read(APIC_SPIV
);
941 value
&= ~APIC_SPIV_APIC_ENABLED
;
942 apic_write(APIC_SPIV
, value
);
946 * When LAPIC was disabled by the BIOS and enabled by the kernel,
947 * restore the disabled state.
949 if (enabled_via_apicbase
) {
952 rdmsr(MSR_IA32_APICBASE
, l
, h
);
953 l
&= ~MSR_IA32_APICBASE_ENABLE
;
954 wrmsr(MSR_IA32_APICBASE
, l
, h
);
960 * If Linux enabled the LAPIC against the BIOS default disable it down before
961 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
962 * not power-off. Additionally clear all LVT entries before disable_local_APIC
963 * for the case where Linux didn't enable the LAPIC.
965 void lapic_shutdown(void)
972 local_irq_save(flags
);
975 if (!enabled_via_apicbase
)
979 disable_local_APIC();
982 local_irq_restore(flags
);
986 * This is to verify that we're looking at a real local APIC.
987 * Check these against your board if the CPUs aren't getting
988 * started for no apparent reason.
990 int __init
verify_local_APIC(void)
992 unsigned int reg0
, reg1
;
995 * The version register is read-only in a real APIC.
997 reg0
= apic_read(APIC_LVR
);
998 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
999 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1000 reg1
= apic_read(APIC_LVR
);
1001 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1004 * The two version reads above should print the same
1005 * numbers. If the second one is different, then we
1006 * poke at a non-APIC.
1012 * Check if the version looks reasonably.
1014 reg1
= GET_APIC_VERSION(reg0
);
1015 if (reg1
== 0x00 || reg1
== 0xff)
1017 reg1
= lapic_get_maxlvt();
1018 if (reg1
< 0x02 || reg1
== 0xff)
1022 * The ID register is read/write in a real APIC.
1024 reg0
= apic_read(APIC_ID
);
1025 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1026 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1027 reg1
= apic_read(APIC_ID
);
1028 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1029 apic_write(APIC_ID
, reg0
);
1030 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1034 * The next two are just to see if we have sane values.
1035 * They're only really relevant if we're in Virtual Wire
1036 * compatibility mode, but most boxes are anymore.
1038 reg0
= apic_read(APIC_LVT0
);
1039 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1040 reg1
= apic_read(APIC_LVT1
);
1041 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1047 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1049 void __init
sync_Arb_IDs(void)
1052 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1055 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1061 apic_wait_icr_idle();
1063 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1064 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1065 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1069 * An initial setup of the virtual wire mode.
1071 void __init
init_bsp_APIC(void)
1076 * Don't do the setup now if we have a SMP BIOS as the
1077 * through-I/O-APIC virtual wire mode might be active.
1079 if (smp_found_config
|| !cpu_has_apic
)
1083 * Do not trust the local APIC being empty at bootup.
1090 value
= apic_read(APIC_SPIV
);
1091 value
&= ~APIC_VECTOR_MASK
;
1092 value
|= APIC_SPIV_APIC_ENABLED
;
1094 #ifdef CONFIG_X86_32
1095 /* This bit is reserved on P4/Xeon and should be cleared */
1096 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1097 (boot_cpu_data
.x86
== 15))
1098 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1101 value
|= APIC_SPIV_FOCUS_DISABLED
;
1102 value
|= SPURIOUS_APIC_VECTOR
;
1103 apic_write(APIC_SPIV
, value
);
1106 * Set up the virtual wire mode.
1108 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1109 value
= APIC_DM_NMI
;
1110 if (!lapic_is_integrated()) /* 82489DX */
1111 value
|= APIC_LVT_LEVEL_TRIGGER
;
1112 apic_write(APIC_LVT1
, value
);
1115 static void __cpuinit
lapic_setup_esr(void)
1117 unsigned int oldvalue
, value
, maxlvt
;
1119 if (!lapic_is_integrated()) {
1120 pr_info("No ESR for 82489DX.\n");
1124 if (apic
->disable_esr
) {
1126 * Something untraceable is creating bad interrupts on
1127 * secondary quads ... for the moment, just leave the
1128 * ESR disabled - we can't do anything useful with the
1129 * errors anyway - mbligh
1131 pr_info("Leaving ESR disabled.\n");
1135 maxlvt
= lapic_get_maxlvt();
1136 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1137 apic_write(APIC_ESR
, 0);
1138 oldvalue
= apic_read(APIC_ESR
);
1140 /* enables sending errors */
1141 value
= ERROR_APIC_VECTOR
;
1142 apic_write(APIC_LVTERR
, value
);
1145 * spec says clear errors after enabling vector.
1148 apic_write(APIC_ESR
, 0);
1149 value
= apic_read(APIC_ESR
);
1150 if (value
!= oldvalue
)
1151 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1152 "vector: 0x%08x after: 0x%08x\n",
1158 * setup_local_APIC - setup the local APIC
1160 void __cpuinit
setup_local_APIC(void)
1166 arch_disable_smp_support();
1170 #ifdef CONFIG_X86_32
1171 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1172 if (lapic_is_integrated() && apic
->disable_esr
) {
1173 apic_write(APIC_ESR
, 0);
1174 apic_write(APIC_ESR
, 0);
1175 apic_write(APIC_ESR
, 0);
1176 apic_write(APIC_ESR
, 0);
1183 * Double-check whether this APIC is really registered.
1184 * This is meaningless in clustered apic mode, so we skip it.
1186 if (!apic
->apic_id_registered())
1190 * Intel recommends to set DFR, LDR and TPR before enabling
1191 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1192 * document number 292116). So here it goes...
1194 apic
->init_apic_ldr();
1197 * Set Task Priority to 'accept all'. We never change this
1200 value
= apic_read(APIC_TASKPRI
);
1201 value
&= ~APIC_TPRI_MASK
;
1202 apic_write(APIC_TASKPRI
, value
);
1205 * After a crash, we no longer service the interrupts and a pending
1206 * interrupt from previous kernel might still have ISR bit set.
1208 * Most probably by now CPU has serviced that pending interrupt and
1209 * it might not have done the ack_APIC_irq() because it thought,
1210 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1211 * does not clear the ISR bit and cpu thinks it has already serivced
1212 * the interrupt. Hence a vector might get locked. It was noticed
1213 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1215 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1216 value
= apic_read(APIC_ISR
+ i
*0x10);
1217 for (j
= 31; j
>= 0; j
--) {
1224 * Now that we are all set up, enable the APIC
1226 value
= apic_read(APIC_SPIV
);
1227 value
&= ~APIC_VECTOR_MASK
;
1231 value
|= APIC_SPIV_APIC_ENABLED
;
1233 #ifdef CONFIG_X86_32
1235 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1236 * certain networking cards. If high frequency interrupts are
1237 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1238 * entry is masked/unmasked at a high rate as well then sooner or
1239 * later IOAPIC line gets 'stuck', no more interrupts are received
1240 * from the device. If focus CPU is disabled then the hang goes
1243 * [ This bug can be reproduced easily with a level-triggered
1244 * PCI Ne2000 networking cards and PII/PIII processors, dual
1248 * Actually disabling the focus CPU check just makes the hang less
1249 * frequent as it makes the interrupt distributon model be more
1250 * like LRU than MRU (the short-term load is more even across CPUs).
1251 * See also the comment in end_level_ioapic_irq(). --macro
1255 * - enable focus processor (bit==0)
1256 * - 64bit mode always use processor focus
1257 * so no need to set it
1259 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1263 * Set spurious IRQ vector
1265 value
|= SPURIOUS_APIC_VECTOR
;
1266 apic_write(APIC_SPIV
, value
);
1269 * Set up LVT0, LVT1:
1271 * set up through-local-APIC on the BP's LINT0. This is not
1272 * strictly necessary in pure symmetric-IO mode, but sometimes
1273 * we delegate interrupts to the 8259A.
1276 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1278 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1279 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1280 value
= APIC_DM_EXTINT
;
1281 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1282 smp_processor_id());
1284 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1285 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1286 smp_processor_id());
1288 apic_write(APIC_LVT0
, value
);
1291 * only the BP should see the LINT1 NMI signal, obviously.
1293 if (!smp_processor_id())
1294 value
= APIC_DM_NMI
;
1296 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1297 if (!lapic_is_integrated()) /* 82489DX */
1298 value
|= APIC_LVT_LEVEL_TRIGGER
;
1299 apic_write(APIC_LVT1
, value
);
1303 #ifdef CONFIG_X86_MCE_INTEL
1304 /* Recheck CMCI information after local APIC is up on CPU #0 */
1305 if (smp_processor_id() == 0)
1310 void __cpuinit
end_local_APIC_setup(void)
1314 #ifdef CONFIG_X86_32
1317 /* Disable the local apic timer */
1318 value
= apic_read(APIC_LVTT
);
1319 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1320 apic_write(APIC_LVTT
, value
);
1324 setup_apic_nmi_watchdog(NULL
);
1328 #ifdef CONFIG_X86_X2APIC
1329 void check_x2apic(void)
1331 if (x2apic_enabled()) {
1332 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1333 x2apic_preenabled
= x2apic
= 1;
1337 void enable_x2apic(void)
1344 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1345 if (!(msr
& X2APIC_ENABLE
)) {
1346 pr_info("Enabling x2apic\n");
1347 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1350 #endif /* CONFIG_X86_X2APIC */
1352 void __init
enable_IR_x2apic(void)
1354 #ifdef CONFIG_INTR_REMAP
1356 unsigned long flags
;
1357 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1359 ret
= dmar_table_init();
1361 pr_debug("dmar_table_init() failed with %d:\n", ret
);
1365 if (!intr_remapping_supported()) {
1366 pr_debug("intr-remapping not supported\n");
1371 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1372 pr_info("Skipped enabling intr-remap because of skipping "
1377 ioapic_entries
= alloc_ioapic_entries();
1378 if (!ioapic_entries
) {
1379 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1383 ret
= save_IO_APIC_setup(ioapic_entries
);
1385 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1389 local_irq_save(flags
);
1390 mask_IO_APIC_setup(ioapic_entries
);
1393 #ifdef CONFIG_X86_X2APIC
1395 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1398 ret
= enable_intr_remapping(EIM_8BIT_APIC_ID
);
1403 pr_info("Enabled Interrupt-remapping\n");
1405 #ifdef CONFIG_X86_X2APIC
1406 if (cpu_has_x2apic
&& !x2apic
) {
1409 pr_info("Enabled x2apic\n");
1416 * IR enabling failed
1418 restore_IO_APIC_setup(ioapic_entries
);
1420 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1423 local_irq_restore(flags
);
1427 free_ioapic_entries(ioapic_entries
);
1433 if (x2apic_preenabled
)
1434 panic("x2apic enabled by bios. But IR enabling failed");
1435 else if (cpu_has_x2apic
)
1436 pr_info("Not enabling x2apic,Intr-remapping\n");
1438 if (!cpu_has_x2apic
)
1441 if (x2apic_preenabled
)
1442 panic("x2apic enabled prior OS handover,"
1443 " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
1450 #ifdef CONFIG_X86_64
1452 * Detect and enable local APICs on non-SMP boards.
1453 * Original code written by Keir Fraser.
1454 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1455 * not correctly set up (usually the APIC timer won't work etc.)
1457 static int __init
detect_init_APIC(void)
1459 if (!cpu_has_apic
) {
1460 pr_info("No local APIC present\n");
1464 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1465 boot_cpu_physical_apicid
= 0;
1470 * Detect and initialize APIC
1472 static int __init
detect_init_APIC(void)
1476 /* Disabled by kernel option? */
1480 switch (boot_cpu_data
.x86_vendor
) {
1481 case X86_VENDOR_AMD
:
1482 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1483 (boot_cpu_data
.x86
>= 15))
1486 case X86_VENDOR_INTEL
:
1487 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1488 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1495 if (!cpu_has_apic
) {
1497 * Over-ride BIOS and try to enable the local APIC only if
1498 * "lapic" specified.
1500 if (!force_enable_local_apic
) {
1501 pr_info("Local APIC disabled by BIOS -- "
1502 "you can enable it with \"lapic\"\n");
1506 * Some BIOSes disable the local APIC in the APIC_BASE
1507 * MSR. This can only be done in software for Intel P6 or later
1508 * and AMD K7 (Model > 1) or later.
1510 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1511 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1512 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1513 l
&= ~MSR_IA32_APICBASE_BASE
;
1514 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1515 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1516 enabled_via_apicbase
= 1;
1520 * The APIC feature bit should now be enabled
1523 features
= cpuid_edx(1);
1524 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1525 pr_warning("Could not enable APIC!\n");
1528 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1529 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1531 /* The BIOS may have set up the APIC at some other address */
1532 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1533 if (l
& MSR_IA32_APICBASE_ENABLE
)
1534 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1536 pr_info("Found and enabled local APIC!\n");
1543 pr_info("No local APIC present or hardware disabled\n");
1548 #ifdef CONFIG_X86_64
1549 void __init
early_init_lapic_mapping(void)
1551 unsigned long phys_addr
;
1554 * If no local APIC can be found then go out
1555 * : it means there is no mpatable and MADT
1557 if (!smp_found_config
)
1560 phys_addr
= mp_lapic_addr
;
1562 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1563 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1564 APIC_BASE
, phys_addr
);
1567 * Fetch the APIC ID of the BSP in case we have a
1568 * default configuration (or the MP table is broken).
1570 boot_cpu_physical_apicid
= read_apic_id();
1575 * init_apic_mappings - initialize APIC mappings
1577 void __init
init_apic_mappings(void)
1580 boot_cpu_physical_apicid
= read_apic_id();
1585 * If no local APIC can be found then set up a fake all
1586 * zeroes page to simulate the local APIC and another
1587 * one for the IO-APIC.
1589 if (!smp_found_config
&& detect_init_APIC()) {
1590 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1591 apic_phys
= __pa(apic_phys
);
1593 apic_phys
= mp_lapic_addr
;
1595 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1596 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1597 APIC_BASE
, apic_phys
);
1600 * Fetch the APIC ID of the BSP in case we have a
1601 * default configuration (or the MP table is broken).
1603 if (boot_cpu_physical_apicid
== -1U)
1604 boot_cpu_physical_apicid
= read_apic_id();
1606 /* lets check if we may to NOP'ify apic operations */
1607 if (!cpu_has_apic
) {
1608 pr_info("APIC: disable apic facility\n");
1614 * This initializes the IO-APIC and APIC hardware if this is
1617 int apic_version
[MAX_APICS
];
1619 int __init
APIC_init_uniprocessor(void)
1622 pr_info("Apic disabled\n");
1625 #ifdef CONFIG_X86_64
1626 if (!cpu_has_apic
) {
1628 pr_info("Apic disabled by BIOS\n");
1632 if (!smp_found_config
&& !cpu_has_apic
)
1636 * Complain if the BIOS pretends there is one.
1638 if (!cpu_has_apic
&&
1639 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1640 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1641 boot_cpu_physical_apicid
);
1642 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1648 #ifdef CONFIG_X86_64
1649 default_setup_apic_routing();
1652 verify_local_APIC();
1655 #ifdef CONFIG_X86_64
1656 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1659 * Hack: In case of kdump, after a crash, kernel might be booting
1660 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1661 * might be zero if read from MP tables. Get it from LAPIC.
1663 # ifdef CONFIG_CRASH_DUMP
1664 boot_cpu_physical_apicid
= read_apic_id();
1667 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1670 #ifdef CONFIG_X86_IO_APIC
1672 * Now enable IO-APICs, actually call clear_IO_APIC
1673 * We need clear_IO_APIC before enabling error vector
1675 if (!skip_ioapic_setup
&& nr_ioapics
)
1679 end_local_APIC_setup();
1681 #ifdef CONFIG_X86_IO_APIC
1682 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1686 localise_nmi_watchdog();
1689 localise_nmi_watchdog();
1693 #ifdef CONFIG_X86_64
1694 check_nmi_watchdog();
1701 * Local APIC interrupts
1705 * This interrupt should _never_ happen with our APIC/SMP architecture
1707 void smp_spurious_interrupt(struct pt_regs
*regs
)
1714 * Check if this really is a spurious interrupt and ACK it
1715 * if it is a vectored one. Just in case...
1716 * Spurious interrupts should not be ACKed.
1718 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1719 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1722 inc_irq_stat(irq_spurious_count
);
1724 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1725 pr_info("spurious APIC interrupt on CPU#%d, "
1726 "should never happen.\n", smp_processor_id());
1731 * This interrupt should never happen with our APIC/SMP architecture
1733 void smp_error_interrupt(struct pt_regs
*regs
)
1739 /* First tickle the hardware, only then report what went on. -- REW */
1740 v
= apic_read(APIC_ESR
);
1741 apic_write(APIC_ESR
, 0);
1742 v1
= apic_read(APIC_ESR
);
1744 atomic_inc(&irq_err_count
);
1747 * Here is what the APIC error bits mean:
1749 * 1: Receive CS error
1750 * 2: Send accept error
1751 * 3: Receive accept error
1753 * 5: Send illegal vector
1754 * 6: Received illegal vector
1755 * 7: Illegal register address
1757 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1758 smp_processor_id(), v
, v1
);
1763 * connect_bsp_APIC - attach the APIC to the interrupt system
1765 void __init
connect_bsp_APIC(void)
1767 #ifdef CONFIG_X86_32
1770 * Do not trust the local APIC being empty at bootup.
1774 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1775 * local APIC to INT and NMI lines.
1777 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1778 "enabling APIC mode.\n");
1782 if (apic
->enable_apic_mode
)
1783 apic
->enable_apic_mode();
1787 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1788 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1790 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1793 void disconnect_bsp_APIC(int virt_wire_setup
)
1797 #ifdef CONFIG_X86_32
1800 * Put the board back into PIC mode (has an effect only on
1801 * certain older boards). Note that APIC interrupts, including
1802 * IPIs, won't work beyond this point! The only exception are
1805 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1806 "entering PIC mode.\n");
1812 /* Go back to Virtual Wire compatibility mode */
1814 /* For the spurious interrupt use vector F, and enable it */
1815 value
= apic_read(APIC_SPIV
);
1816 value
&= ~APIC_VECTOR_MASK
;
1817 value
|= APIC_SPIV_APIC_ENABLED
;
1819 apic_write(APIC_SPIV
, value
);
1821 if (!virt_wire_setup
) {
1823 * For LVT0 make it edge triggered, active high,
1824 * external and enabled
1826 value
= apic_read(APIC_LVT0
);
1827 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1828 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1829 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1830 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1831 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1832 apic_write(APIC_LVT0
, value
);
1835 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1839 * For LVT1 make it edge triggered, active high,
1842 value
= apic_read(APIC_LVT1
);
1843 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1844 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1845 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1846 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1847 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1848 apic_write(APIC_LVT1
, value
);
1851 void __cpuinit
generic_processor_info(int apicid
, int version
)
1858 if (version
== 0x0) {
1859 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1860 "fixing up to 0x10. (tell your hw vendor)\n",
1864 apic_version
[apicid
] = version
;
1866 if (num_processors
>= nr_cpu_ids
) {
1867 int max
= nr_cpu_ids
;
1868 int thiscpu
= max
+ disabled_cpus
;
1871 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1872 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1879 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1881 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1883 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1884 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1886 physid_set(apicid
, phys_cpu_present_map
);
1887 if (apicid
== boot_cpu_physical_apicid
) {
1889 * x86_bios_cpu_apicid is required to have processors listed
1890 * in same order as logical cpu numbers. Hence the first
1891 * entry is BSP, and so on.
1895 if (apicid
> max_physical_apicid
)
1896 max_physical_apicid
= apicid
;
1898 #ifdef CONFIG_X86_32
1900 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1901 * but we need to work other dependencies like SMP_SUSPEND etc
1902 * before this can be done without some confusion.
1903 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1904 * - Ashok Raj <ashok.raj@intel.com>
1906 if (max_physical_apicid
>= 8) {
1907 switch (boot_cpu_data
.x86_vendor
) {
1908 case X86_VENDOR_INTEL
:
1909 if (!APIC_XAPIC(version
)) {
1913 /* If P4 and above fall through */
1914 case X86_VENDOR_AMD
:
1920 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1921 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1922 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1925 set_cpu_possible(cpu
, true);
1926 set_cpu_present(cpu
, true);
1929 int hard_smp_processor_id(void)
1931 return read_apic_id();
1934 void default_init_apic_ldr(void)
1938 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1939 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1940 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1941 apic_write(APIC_LDR
, val
);
1944 #ifdef CONFIG_X86_32
1945 int default_apicid_to_node(int logical_apicid
)
1948 return apicid_2_node
[hard_smp_processor_id()];
1962 * 'active' is true if the local APIC was enabled by us and
1963 * not the BIOS; this signifies that we are also responsible
1964 * for disabling it before entering apm/acpi suspend
1967 /* r/w apic fields */
1968 unsigned int apic_id
;
1969 unsigned int apic_taskpri
;
1970 unsigned int apic_ldr
;
1971 unsigned int apic_dfr
;
1972 unsigned int apic_spiv
;
1973 unsigned int apic_lvtt
;
1974 unsigned int apic_lvtpc
;
1975 unsigned int apic_lvt0
;
1976 unsigned int apic_lvt1
;
1977 unsigned int apic_lvterr
;
1978 unsigned int apic_tmict
;
1979 unsigned int apic_tdcr
;
1980 unsigned int apic_thmr
;
1983 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1985 unsigned long flags
;
1988 if (!apic_pm_state
.active
)
1991 maxlvt
= lapic_get_maxlvt();
1993 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1994 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1995 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1996 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1997 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1998 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2000 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2001 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2002 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2003 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2004 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2005 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2006 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2008 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2011 local_irq_save(flags
);
2012 disable_local_APIC();
2013 #ifdef CONFIG_INTR_REMAP
2014 if (intr_remapping_enabled
)
2015 disable_intr_remapping();
2017 local_irq_restore(flags
);
2021 static int lapic_resume(struct sys_device
*dev
)
2024 unsigned long flags
;
2027 #ifdef CONFIG_INTR_REMAP
2029 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2031 if (!apic_pm_state
.active
)
2034 local_irq_save(flags
);
2036 ioapic_entries
= alloc_ioapic_entries();
2037 if (!ioapic_entries
) {
2038 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2042 ret
= save_IO_APIC_setup(ioapic_entries
);
2044 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2045 free_ioapic_entries(ioapic_entries
);
2049 mask_IO_APIC_setup(ioapic_entries
);
2054 if (!apic_pm_state
.active
)
2057 local_irq_save(flags
);
2064 * Make sure the APICBASE points to the right address
2066 * FIXME! This will be wrong if we ever support suspend on
2067 * SMP! We'll need to do this as part of the CPU restore!
2069 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2070 l
&= ~MSR_IA32_APICBASE_BASE
;
2071 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2072 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2075 maxlvt
= lapic_get_maxlvt();
2076 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2077 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2078 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2079 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2080 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2081 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2082 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2083 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2084 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2086 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2089 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2090 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2091 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2092 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2093 apic_write(APIC_ESR
, 0);
2094 apic_read(APIC_ESR
);
2095 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2096 apic_write(APIC_ESR
, 0);
2097 apic_read(APIC_ESR
);
2099 #ifdef CONFIG_INTR_REMAP
2100 if (intr_remapping_enabled
)
2101 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2105 restore_IO_APIC_setup(ioapic_entries
);
2106 free_ioapic_entries(ioapic_entries
);
2110 local_irq_restore(flags
);
2117 * This device has no shutdown method - fully functioning local APICs
2118 * are needed on every CPU up until machine_halt/restart/poweroff.
2121 static struct sysdev_class lapic_sysclass
= {
2123 .resume
= lapic_resume
,
2124 .suspend
= lapic_suspend
,
2127 static struct sys_device device_lapic
= {
2129 .cls
= &lapic_sysclass
,
2132 static void __cpuinit
apic_pm_activate(void)
2134 apic_pm_state
.active
= 1;
2137 static int __init
init_lapic_sysfs(void)
2143 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2145 error
= sysdev_class_register(&lapic_sysclass
);
2147 error
= sysdev_register(&device_lapic
);
2151 /* local apic needs to resume before other devices access its registers. */
2152 core_initcall(init_lapic_sysfs
);
2154 #else /* CONFIG_PM */
2156 static void apic_pm_activate(void) { }
2158 #endif /* CONFIG_PM */
2160 #ifdef CONFIG_X86_64
2162 * apic_is_clustered_box() -- Check if we can expect good TSC
2164 * Thus far, the major user of this is IBM's Summit2 series:
2166 * Clustered boxes may have unsynced TSC problems if they are
2167 * multi-chassis. Use available data to take a good guess.
2168 * If in doubt, go HPET.
2170 __cpuinit
int apic_is_clustered_box(void)
2172 int i
, clusters
, zeros
;
2174 u16
*bios_cpu_apicid
;
2175 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2178 * there is not this kind of box with AMD CPU yet.
2179 * Some AMD box with quadcore cpu and 8 sockets apicid
2180 * will be [4, 0x23] or [8, 0x27] could be thought to
2181 * vsmp box still need checking...
2183 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2186 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2187 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2189 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2190 /* are we being called early in kernel startup? */
2191 if (bios_cpu_apicid
) {
2192 id
= bios_cpu_apicid
[i
];
2193 } else if (i
< nr_cpu_ids
) {
2195 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2201 if (id
!= BAD_APICID
)
2202 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2205 /* Problem: Partially populated chassis may not have CPUs in some of
2206 * the APIC clusters they have been allocated. Only present CPUs have
2207 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2208 * Since clusters are allocated sequentially, count zeros only if
2209 * they are bounded by ones.
2213 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2214 if (test_bit(i
, clustermap
)) {
2215 clusters
+= 1 + zeros
;
2221 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2222 * not guaranteed to be synced between boards
2224 if (is_vsmp_box() && clusters
> 1)
2228 * If clusters > 2, then should be multi-chassis.
2229 * May have to revisit this when multi-core + hyperthreaded CPUs come
2230 * out, but AFAIK this will work even for them.
2232 return (clusters
> 2);
2237 * APIC command line parameters
2239 static int __init
setup_disableapic(char *arg
)
2242 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2245 early_param("disableapic", setup_disableapic
);
2247 /* same as disableapic, for compatibility */
2248 static int __init
setup_nolapic(char *arg
)
2250 return setup_disableapic(arg
);
2252 early_param("nolapic", setup_nolapic
);
2254 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2256 local_apic_timer_c2_ok
= 1;
2259 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2261 static int __init
parse_disable_apic_timer(char *arg
)
2263 disable_apic_timer
= 1;
2266 early_param("noapictimer", parse_disable_apic_timer
);
2268 static int __init
parse_nolapic_timer(char *arg
)
2270 disable_apic_timer
= 1;
2273 early_param("nolapic_timer", parse_nolapic_timer
);
2275 static int __init
apic_set_verbosity(char *arg
)
2278 #ifdef CONFIG_X86_64
2279 skip_ioapic_setup
= 0;
2285 if (strcmp("debug", arg
) == 0)
2286 apic_verbosity
= APIC_DEBUG
;
2287 else if (strcmp("verbose", arg
) == 0)
2288 apic_verbosity
= APIC_VERBOSE
;
2290 pr_warning("APIC Verbosity level %s not recognised"
2291 " use apic=verbose or apic=debug\n", arg
);
2297 early_param("apic", apic_set_verbosity
);
2299 static int __init
lapic_insert_resource(void)
2304 /* Put local APIC into the resource map. */
2305 lapic_resource
.start
= apic_phys
;
2306 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2307 insert_resource(&iomem_resource
, &lapic_resource
);
2313 * need call insert after e820_reserve_resources()
2314 * that is using request_resource
2316 late_initcall(lapic_insert_resource
);