arch/mips/jmr3927/rbhma3100/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ahennessy@mvista.com
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  *
  10  * Copyright (C) 2000-2001 Toshiba Corporation
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32 #include <linux/init.h>
  33
  34 #include <linux/errno.h>
  35 #include <linux/irq.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/signal.h>
  38 #include <linux/sched.h>
  39 #include <linux/types.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/ioport.h>
  42 #include <linux/timex.h>
  43 #include <linux/slab.h>
  44 #include <linux/random.h>
  45 #include <linux/smp.h>
  46 #include <linux/smp_lock.h>
  47 #include <linux/bitops.h>
  48
  49 #include <asm/irq_regs.h>
  50 #include <asm/io.h>
  51 #include <asm/mipsregs.h>
  52 #include <asm/system.h>
  53
  54 #include <asm/ptrace.h>
  55 #include <asm/processor.h>
  56 #include <asm/jmr3927/irq.h>
  57 #include <asm/debug.h>
  58 #include <asm/jmr3927/jmr3927.h>
  59
  60 #if JMR3927_IRQ_END > NR_IRQS
  61 #error JMR3927_IRQ_END > NR_IRQS
  62 #endif
  63
  64 struct tb_irq_space* tb_irq_spaces;
  65
  66 static int jmr3927_irq_base = -1;
  67
  68 #ifdef CONFIG_PCI
  69 static int jmr3927_gen_iack(void)
  70 {
  71         /* generate ACK cycle */
  72 #ifdef __BIG_ENDIAN
  73         return (tx3927_pcicptr->iiadp >> 24) & 0xff;
  74 #else
  75         return tx3927_pcicptr->iiadp & 0xff;
  76 #endif
  77 }
  78 #endif
  79
  80 #define irc_dlevel      0
  81 #define irc_elevel      1
  82
  83 static unsigned char irc_level[TX3927_NUM_IR] = {
  84         5, 5, 5, 5, 5, 5,       /* INT[5:0] */
  85         7, 7,                   /* SIO */
  86         5, 5, 5, 0, 0,          /* DMA, PIO, PCI */
  87         6, 6, 6                 /* TMR */
  88 };
  89
  90 static void jmr3927_irq_disable(unsigned int irq_nr);
  91 static void jmr3927_irq_enable(unsigned int irq_nr);
  92
  93 static DEFINE_SPINLOCK(jmr3927_irq_lock);
  94
  95 static unsigned int jmr3927_irq_startup(unsigned int irq)
  96 {
  97         jmr3927_irq_enable(irq);
  98
  99         return 0;
 100 }
 101
 102 #define jmr3927_irq_shutdown    jmr3927_irq_disable
 103
 104 static void jmr3927_irq_ack(unsigned int irq)
 105 {
 106         if (irq == JMR3927_IRQ_IRC_TMR0)
 107                 jmr3927_tmrptr->tisr = 0;       /* ack interrupt */
 108
 109         jmr3927_irq_disable(irq);
 110 }
 111
 112 static void jmr3927_irq_end(unsigned int irq)
 113 {
 114         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 115                 jmr3927_irq_enable(irq);
 116 }
 117
 118 static void jmr3927_irq_disable(unsigned int irq_nr)
 119 {
 120         struct tb_irq_space* sp;
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&jmr3927_irq_lock, flags);
 124         for (sp = tb_irq_spaces; sp; sp = sp->next) {
 125                 if (sp->start_irqno <= irq_nr &&
 126                     irq_nr < sp->start_irqno + sp->nr_irqs) {
 127                         if (sp->mask_func)
 128                                 sp->mask_func(irq_nr - sp->start_irqno,
 129                                               sp->space_id);
 130                         break;
 131                 }
 132         }
 133         spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
 134 }
 135
 136 static void jmr3927_irq_enable(unsigned int irq_nr)
 137 {
 138         struct tb_irq_space* sp;
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&jmr3927_irq_lock, flags);
 142         for (sp = tb_irq_spaces; sp; sp = sp->next) {
 143                 if (sp->start_irqno <= irq_nr &&
 144                     irq_nr < sp->start_irqno + sp->nr_irqs) {
 145                         if (sp->unmask_func)
 146                                 sp->unmask_func(irq_nr - sp->start_irqno,
 147                                                 sp->space_id);
 148                         break;
 149                 }
 150         }
 151         spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
 152 }
 153
 154 /*
 155  * CP0_STATUS is a thread's resource (saved/restored on context switch).
 156  * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
 157  */
 158 static void mask_irq_isac(int irq_nr, int space_id)
 159 {
 160         /* 0: mask */
 161         unsigned char imask =
 162                 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 163         unsigned int bit  = 1 << irq_nr;
 164         jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
 165         /* flush write buffer */
 166         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 167 }
 168 static void unmask_irq_isac(int irq_nr, int space_id)
 169 {
 170         /* 0: mask */
 171         unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 172         unsigned int bit  = 1 << irq_nr;
 173         jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
 174         /* flush write buffer */
 175         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 176 }
 177
 178 static void mask_irq_ioc(int irq_nr, int space_id)
 179 {
 180         /* 0: mask */
 181         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 182         unsigned int bit = 1 << irq_nr;
 183         jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
 184         /* flush write buffer */
 185         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 186 }
 187 static void unmask_irq_ioc(int irq_nr, int space_id)
 188 {
 189         /* 0: mask */
 190         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 191         unsigned int bit = 1 << irq_nr;
 192         jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
 193         /* flush write buffer */
 194         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 195 }
 196
 197 static void mask_irq_irc(int irq_nr, int space_id)
 198 {
 199         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 200         if (irq_nr & 1)
 201                 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
 202         else
 203                 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
 204         /* update IRCSR */
 205         tx3927_ircptr->imr = 0;
 206         tx3927_ircptr->imr = irc_elevel;
 207         /* flush write buffer */
 208         (void)tx3927_ircptr->ssr;
 209 }
 210
 211 static void unmask_irq_irc(int irq_nr, int space_id)
 212 {
 213         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 214         if (irq_nr & 1)
 215                 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
 216         else
 217                 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
 218         /* update IRCSR */
 219         tx3927_ircptr->imr = 0;
 220         tx3927_ircptr->imr = irc_elevel;
 221 }
 222
 223 struct tb_irq_space jmr3927_isac_irqspace = {
 224         .next = NULL,
 225         .start_irqno = JMR3927_IRQ_ISAC,
 226         nr_irqs : JMR3927_NR_IRQ_ISAC,
 227         .mask_func = mask_irq_isac,
 228         .unmask_func = unmask_irq_isac,
 229         .name = "ISAC",
 230         .space_id = 0,
 231         can_share : 0
 232 };
 233 struct tb_irq_space jmr3927_ioc_irqspace = {
 234         .next = NULL,
 235         .start_irqno = JMR3927_IRQ_IOC,
 236         nr_irqs : JMR3927_NR_IRQ_IOC,
 237         .mask_func = mask_irq_ioc,
 238         .unmask_func = unmask_irq_ioc,
 239         .name = "IOC",
 240         .space_id = 0,
 241         can_share : 1
 242 };
 243
 244 struct tb_irq_space jmr3927_irc_irqspace = {
 245         .next           = NULL,
 246         .start_irqno    = JMR3927_IRQ_IRC,
 247         .nr_irqs        = JMR3927_NR_IRQ_IRC,
 248         .mask_func      = mask_irq_irc,
 249         .unmask_func    = unmask_irq_irc,
 250         .name           = "on-chip",
 251         .space_id       = 0,
 252         .can_share      = 0
 253 };
 254
 255
 256 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 257 static int tx_branch_likely_bug_count = 0;
 258 static int have_tx_branch_likely_bug = 0;
 259
 260 static void tx_branch_likely_bug_fixup(void)
 261 {
 262         struct pt_regs *regs = get_irq_regs();
 263
 264         /* TX39/49-BUG: Under this condition, the insn in delay slot
 265            of the branch likely insn is executed (not nullified) even
 266            the branch condition is false. */
 267         if (!have_tx_branch_likely_bug)
 268                 return;
 269         if ((regs->cp0_epc & 0xfff) == 0xffc &&
 270             KSEGX(regs->cp0_epc) != KSEG0 &&
 271             KSEGX(regs->cp0_epc) != KSEG1) {
 272                 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
 273                 /* beql,bnel,blezl,bgtzl */
 274                 /* bltzl,bgezl,blezall,bgezall */
 275                 /* bczfl, bcztl */
 276                 if ((insn & 0xf0000000) == 0x50000000 ||
 277                     (insn & 0xfc0e0000) == 0x04020000 ||
 278                     (insn & 0xf3fe0000) == 0x41020000) {
 279                         regs->cp0_epc -= 4;
 280                         tx_branch_likely_bug_count++;
 281                         printk(KERN_INFO
 282                                "fix branch-likery bug in %s (insn %08x)\n",
 283                                current->comm, insn);
 284                 }
 285         }
 286 }
 287 #endif
 288
 289 static void jmr3927_spurious(void)
 290 {
 291 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 292         tx_branch_likely_bug_fixup();
 293 #endif
 294         printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
 295                regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
 296 }
 297
 298 asmlinkage void plat_irq_dispatch(void)
 299 {
 300         int irq;
 301
 302 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 303         tx_branch_likely_bug_fixup();
 304 #endif
 305         if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
 306 #if 0
 307                 jmr3927_spurious();
 308 #endif
 309                 return;
 310         }
 311         irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
 312
 313         do_IRQ(irq + JMR3927_IRQ_IRC);
 314 }
 315
 316 static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
 317 {
 318         unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
 319         int i;
 320
 321         for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
 322                 if (istat & (1 << i)) {
 323                         irq = JMR3927_IRQ_IOC + i;
 324                         do_IRQ(irq);
 325                 }
 326         }
 327         return IRQ_HANDLED;
 328 }
 329
 330 static struct irqaction ioc_action = {
 331         jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
 332 };
 333
 334 static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
 335 {
 336         unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
 337         int i;
 338
 339         for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
 340                 if (istat & (1 << i)) {
 341                         irq = JMR3927_IRQ_ISAC + i;
 342                         do_IRQ(irq);
 343                 }
 344         }
 345         return IRQ_HANDLED;
 346 }
 347
 348 static struct irqaction isac_action = {
 349         jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
 350 };
 351
 352
 353 static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
 354 {
 355         printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
 356
 357         return IRQ_HANDLED;
 358 }
 359 static struct irqaction isaerr_action = {
 360         jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
 361 };
 362
 363 static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
 364 {
 365         printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
 366         printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
 367                tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
 368
 369         return IRQ_HANDLED;
 370 }
 371 static struct irqaction pcierr_action = {
 372         jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
 373 };
 374
 375 int jmr3927_ether1_irq = 0;
 376
 377 void jmr3927_irq_init(u32 irq_base);
 378
 379 void __init arch_init_irq(void)
 380 {
 381         /* look for io board's presence */
 382         int have_isac = jmr3927_have_isac();
 383
 384         /* Now, interrupt control disabled, */
 385         /* all IRC interrupts are masked, */
 386         /* all IRC interrupt mode are Low Active. */
 387
 388         if (have_isac) {
 389
 390                 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
 391                 /* temporary enable interrupt control */
 392                 tx3927_ircptr->cer = 1;
 393                 /* ETHER1 Int. Is High-Active. */
 394                 if (tx3927_ircptr->ssr & (1 << 0))
 395                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
 396 #if 0   /* INT3 may be asserted by ether0 (even after reboot...) */
 397                 else if (tx3927_ircptr->ssr & (1 << 3))
 398                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
 399 #endif
 400                 /* disable interrupt control */
 401                 tx3927_ircptr->cer = 0;
 402
 403                 /* Ether1: High Active */
 404                 if (jmr3927_ether1_irq) {
 405                         int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
 406                         tx3927_ircptr->cr[ether1_irc / 8] |=
 407                                 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
 408                 }
 409         }
 410
 411         /* mask all IOC interrupts */
 412         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
 413         /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
 414         jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
 415
 416         if (have_isac) {
 417                 /* mask all ISAC interrupts */
 418                 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
 419                 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
 420                 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
 421         }
 422
 423         /* clear PCI Soft interrupts */
 424         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
 425         /* clear PCI Reset interrupts */
 426         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 427
 428         /* enable interrupt control */
 429         tx3927_ircptr->cer = TX3927_IRCER_ICE;
 430         tx3927_ircptr->imr = irc_elevel;
 431
 432         jmr3927_irq_init(NR_ISA_IRQS);
 433
 434         /* setup irq space */
 435         add_tb_irq_space(&jmr3927_isac_irqspace);
 436         add_tb_irq_space(&jmr3927_ioc_irqspace);
 437         add_tb_irq_space(&jmr3927_irc_irqspace);
 438
 439         /* setup IOC interrupt 1 (PCI, MODEM) */
 440         setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
 441
 442         if (have_isac) {
 443                 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
 444                 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
 445         }
 446
 447 #ifdef CONFIG_PCI
 448         setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
 449 #endif
 450
 451         /* enable all CPU interrupt bits. */
 452         set_c0_status(ST0_IM);  /* IE bit is still 0. */
 453 }
 454
 455 static struct irq_chip jmr3927_irq_controller = {
 456         .typename = "jmr3927_irq",
 457         .startup = jmr3927_irq_startup,
 458         .shutdown = jmr3927_irq_shutdown,
 459         .enable = jmr3927_irq_enable,
 460         .disable = jmr3927_irq_disable,
 461         .ack = jmr3927_irq_ack,
 462         .end = jmr3927_irq_end,
 463 };
 464
 465 void jmr3927_irq_init(u32 irq_base)
 466 {
 467         u32 i;
 468
 469         for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
 470                 irq_desc[i].status = IRQ_DISABLED;
 471                 irq_desc[i].action = NULL;
 472                 irq_desc[i].depth = 1;
 473                 irq_desc[i].chip = &jmr3927_irq_controller;
 474         }
 475
 476         jmr3927_irq_base = irq_base;
 477 }