2 * icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
4 * Copyright (C) 2001-2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
25 * - New creation, NEC VR4122 and VR4131 are supported.
26 * - Added support for NEC VR4111 and VR4121.
28 * Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
29 * - Coped with INTASSIGN of NEC VR4133.
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
34 #include <linux/irq.h>
35 #include <linux/module.h>
36 #include <linux/smp.h>
37 #include <linux/types.h>
41 #include <asm/vr41xx/irq.h>
42 #include <asm/vr41xx/vr41xx.h>
44 static void __iomem
*icu1_base
;
45 static void __iomem
*icu2_base
;
47 static unsigned char sysint1_assign
[16] = {
48 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
49 static unsigned char sysint2_assign
[16] = {
50 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
52 #define ICU1_TYPE1_BASE 0x0b000080UL
53 #define ICU2_TYPE1_BASE 0x0b000200UL
55 #define ICU1_TYPE2_BASE 0x0f000080UL
56 #define ICU2_TYPE2_BASE 0x0f0000a0UL
58 #define ICU1_SIZE 0x20
59 #define ICU2_SIZE 0x1c
61 #define SYSINT1REG 0x00
62 #define PIUINTREG 0x02
63 #define INTASSIGN0 0x04
64 #define INTASSIGN1 0x06
65 #define GIUINTLREG 0x08
66 #define DSIUINTREG 0x0a
67 #define MSYSINT1REG 0x0c
68 #define MPIUINTREG 0x0e
69 #define MAIUINTREG 0x10
70 #define MKIUINTREG 0x12
71 #define MGIUINTLREG 0x14
72 #define MDSIUINTREG 0x16
75 #define INTASSIGN2 0x1c
76 #define INTASSIGN3 0x1e
78 #define SYSINT2REG 0x00
79 #define GIUINTHREG 0x02
80 #define FIRINTREG 0x04
81 #define MSYSINT2REG 0x06
82 #define MGIUINTHREG 0x08
83 #define MFIRINTREG 0x0a
84 #define PCIINTREG 0x0c
85 #define PCIINT0 0x0001
86 #define SCUINTREG 0x0e
87 #define SCUINT0 0x0001
88 #define CSIINTREG 0x10
89 #define MPCIINTREG 0x12
90 #define MSCUINTREG 0x14
91 #define MCSIINTREG 0x16
92 #define BCUINTREG 0x18
93 #define BCUINTR 0x0001
94 #define MBCUINTREG 0x1a
96 #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
97 #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
99 #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
101 #define icu1_read(offset) readw(icu1_base + (offset))
102 #define icu1_write(offset, value) writew((value), icu1_base + (offset))
104 #define icu2_read(offset) readw(icu2_base + (offset))
105 #define icu2_write(offset, value) writew((value), icu2_base + (offset))
107 #define INTASSIGN_MAX 4
108 #define INTASSIGN_MASK 0x0007
110 static inline uint16_t icu1_set(uint8_t offset
, uint16_t set
)
114 data
= icu1_read(offset
);
116 icu1_write(offset
, data
);
121 static inline uint16_t icu1_clear(uint8_t offset
, uint16_t clear
)
125 data
= icu1_read(offset
);
127 icu1_write(offset
, data
);
132 static inline uint16_t icu2_set(uint8_t offset
, uint16_t set
)
136 data
= icu2_read(offset
);
138 icu2_write(offset
, data
);
143 static inline uint16_t icu2_clear(uint8_t offset
, uint16_t clear
)
147 data
= icu2_read(offset
);
149 icu2_write(offset
, data
);
154 void vr41xx_enable_piuint(uint16_t mask
)
156 struct irq_desc
*desc
= irq_desc
+ PIU_IRQ
;
159 if (current_cpu_data
.cputype
== CPU_VR4111
||
160 current_cpu_data
.cputype
== CPU_VR4121
) {
161 spin_lock_irqsave(&desc
->lock
, flags
);
162 icu1_set(MPIUINTREG
, mask
);
163 spin_unlock_irqrestore(&desc
->lock
, flags
);
167 EXPORT_SYMBOL(vr41xx_enable_piuint
);
169 void vr41xx_disable_piuint(uint16_t mask
)
171 struct irq_desc
*desc
= irq_desc
+ PIU_IRQ
;
174 if (current_cpu_data
.cputype
== CPU_VR4111
||
175 current_cpu_data
.cputype
== CPU_VR4121
) {
176 spin_lock_irqsave(&desc
->lock
, flags
);
177 icu1_clear(MPIUINTREG
, mask
);
178 spin_unlock_irqrestore(&desc
->lock
, flags
);
182 EXPORT_SYMBOL(vr41xx_disable_piuint
);
184 void vr41xx_enable_aiuint(uint16_t mask
)
186 struct irq_desc
*desc
= irq_desc
+ AIU_IRQ
;
189 if (current_cpu_data
.cputype
== CPU_VR4111
||
190 current_cpu_data
.cputype
== CPU_VR4121
) {
191 spin_lock_irqsave(&desc
->lock
, flags
);
192 icu1_set(MAIUINTREG
, mask
);
193 spin_unlock_irqrestore(&desc
->lock
, flags
);
197 EXPORT_SYMBOL(vr41xx_enable_aiuint
);
199 void vr41xx_disable_aiuint(uint16_t mask
)
201 struct irq_desc
*desc
= irq_desc
+ AIU_IRQ
;
204 if (current_cpu_data
.cputype
== CPU_VR4111
||
205 current_cpu_data
.cputype
== CPU_VR4121
) {
206 spin_lock_irqsave(&desc
->lock
, flags
);
207 icu1_clear(MAIUINTREG
, mask
);
208 spin_unlock_irqrestore(&desc
->lock
, flags
);
212 EXPORT_SYMBOL(vr41xx_disable_aiuint
);
214 void vr41xx_enable_kiuint(uint16_t mask
)
216 struct irq_desc
*desc
= irq_desc
+ KIU_IRQ
;
219 if (current_cpu_data
.cputype
== CPU_VR4111
||
220 current_cpu_data
.cputype
== CPU_VR4121
) {
221 spin_lock_irqsave(&desc
->lock
, flags
);
222 icu1_set(MKIUINTREG
, mask
);
223 spin_unlock_irqrestore(&desc
->lock
, flags
);
227 EXPORT_SYMBOL(vr41xx_enable_kiuint
);
229 void vr41xx_disable_kiuint(uint16_t mask
)
231 struct irq_desc
*desc
= irq_desc
+ KIU_IRQ
;
234 if (current_cpu_data
.cputype
== CPU_VR4111
||
235 current_cpu_data
.cputype
== CPU_VR4121
) {
236 spin_lock_irqsave(&desc
->lock
, flags
);
237 icu1_clear(MKIUINTREG
, mask
);
238 spin_unlock_irqrestore(&desc
->lock
, flags
);
242 EXPORT_SYMBOL(vr41xx_disable_kiuint
);
244 void vr41xx_enable_dsiuint(uint16_t mask
)
246 struct irq_desc
*desc
= irq_desc
+ DSIU_IRQ
;
249 spin_lock_irqsave(&desc
->lock
, flags
);
250 icu1_set(MDSIUINTREG
, mask
);
251 spin_unlock_irqrestore(&desc
->lock
, flags
);
254 EXPORT_SYMBOL(vr41xx_enable_dsiuint
);
256 void vr41xx_disable_dsiuint(uint16_t mask
)
258 struct irq_desc
*desc
= irq_desc
+ DSIU_IRQ
;
261 spin_lock_irqsave(&desc
->lock
, flags
);
262 icu1_clear(MDSIUINTREG
, mask
);
263 spin_unlock_irqrestore(&desc
->lock
, flags
);
266 EXPORT_SYMBOL(vr41xx_disable_dsiuint
);
268 void vr41xx_enable_firint(uint16_t mask
)
270 struct irq_desc
*desc
= irq_desc
+ FIR_IRQ
;
273 spin_lock_irqsave(&desc
->lock
, flags
);
274 icu2_set(MFIRINTREG
, mask
);
275 spin_unlock_irqrestore(&desc
->lock
, flags
);
278 EXPORT_SYMBOL(vr41xx_enable_firint
);
280 void vr41xx_disable_firint(uint16_t mask
)
282 struct irq_desc
*desc
= irq_desc
+ FIR_IRQ
;
285 spin_lock_irqsave(&desc
->lock
, flags
);
286 icu2_clear(MFIRINTREG
, mask
);
287 spin_unlock_irqrestore(&desc
->lock
, flags
);
290 EXPORT_SYMBOL(vr41xx_disable_firint
);
292 void vr41xx_enable_pciint(void)
294 struct irq_desc
*desc
= irq_desc
+ PCI_IRQ
;
297 if (current_cpu_data
.cputype
== CPU_VR4122
||
298 current_cpu_data
.cputype
== CPU_VR4131
||
299 current_cpu_data
.cputype
== CPU_VR4133
) {
300 spin_lock_irqsave(&desc
->lock
, flags
);
301 icu2_write(MPCIINTREG
, PCIINT0
);
302 spin_unlock_irqrestore(&desc
->lock
, flags
);
306 EXPORT_SYMBOL(vr41xx_enable_pciint
);
308 void vr41xx_disable_pciint(void)
310 struct irq_desc
*desc
= irq_desc
+ PCI_IRQ
;
313 if (current_cpu_data
.cputype
== CPU_VR4122
||
314 current_cpu_data
.cputype
== CPU_VR4131
||
315 current_cpu_data
.cputype
== CPU_VR4133
) {
316 spin_lock_irqsave(&desc
->lock
, flags
);
317 icu2_write(MPCIINTREG
, 0);
318 spin_unlock_irqrestore(&desc
->lock
, flags
);
322 EXPORT_SYMBOL(vr41xx_disable_pciint
);
324 void vr41xx_enable_scuint(void)
326 struct irq_desc
*desc
= irq_desc
+ SCU_IRQ
;
329 if (current_cpu_data
.cputype
== CPU_VR4122
||
330 current_cpu_data
.cputype
== CPU_VR4131
||
331 current_cpu_data
.cputype
== CPU_VR4133
) {
332 spin_lock_irqsave(&desc
->lock
, flags
);
333 icu2_write(MSCUINTREG
, SCUINT0
);
334 spin_unlock_irqrestore(&desc
->lock
, flags
);
338 EXPORT_SYMBOL(vr41xx_enable_scuint
);
340 void vr41xx_disable_scuint(void)
342 struct irq_desc
*desc
= irq_desc
+ SCU_IRQ
;
345 if (current_cpu_data
.cputype
== CPU_VR4122
||
346 current_cpu_data
.cputype
== CPU_VR4131
||
347 current_cpu_data
.cputype
== CPU_VR4133
) {
348 spin_lock_irqsave(&desc
->lock
, flags
);
349 icu2_write(MSCUINTREG
, 0);
350 spin_unlock_irqrestore(&desc
->lock
, flags
);
354 EXPORT_SYMBOL(vr41xx_disable_scuint
);
356 void vr41xx_enable_csiint(uint16_t mask
)
358 struct irq_desc
*desc
= irq_desc
+ CSI_IRQ
;
361 if (current_cpu_data
.cputype
== CPU_VR4122
||
362 current_cpu_data
.cputype
== CPU_VR4131
||
363 current_cpu_data
.cputype
== CPU_VR4133
) {
364 spin_lock_irqsave(&desc
->lock
, flags
);
365 icu2_set(MCSIINTREG
, mask
);
366 spin_unlock_irqrestore(&desc
->lock
, flags
);
370 EXPORT_SYMBOL(vr41xx_enable_csiint
);
372 void vr41xx_disable_csiint(uint16_t mask
)
374 struct irq_desc
*desc
= irq_desc
+ CSI_IRQ
;
377 if (current_cpu_data
.cputype
== CPU_VR4122
||
378 current_cpu_data
.cputype
== CPU_VR4131
||
379 current_cpu_data
.cputype
== CPU_VR4133
) {
380 spin_lock_irqsave(&desc
->lock
, flags
);
381 icu2_clear(MCSIINTREG
, mask
);
382 spin_unlock_irqrestore(&desc
->lock
, flags
);
386 EXPORT_SYMBOL(vr41xx_disable_csiint
);
388 void vr41xx_enable_bcuint(void)
390 struct irq_desc
*desc
= irq_desc
+ BCU_IRQ
;
393 if (current_cpu_data
.cputype
== CPU_VR4122
||
394 current_cpu_data
.cputype
== CPU_VR4131
||
395 current_cpu_data
.cputype
== CPU_VR4133
) {
396 spin_lock_irqsave(&desc
->lock
, flags
);
397 icu2_write(MBCUINTREG
, BCUINTR
);
398 spin_unlock_irqrestore(&desc
->lock
, flags
);
402 EXPORT_SYMBOL(vr41xx_enable_bcuint
);
404 void vr41xx_disable_bcuint(void)
406 struct irq_desc
*desc
= irq_desc
+ BCU_IRQ
;
409 if (current_cpu_data
.cputype
== CPU_VR4122
||
410 current_cpu_data
.cputype
== CPU_VR4131
||
411 current_cpu_data
.cputype
== CPU_VR4133
) {
412 spin_lock_irqsave(&desc
->lock
, flags
);
413 icu2_write(MBCUINTREG
, 0);
414 spin_unlock_irqrestore(&desc
->lock
, flags
);
418 EXPORT_SYMBOL(vr41xx_disable_bcuint
);
420 static unsigned int startup_sysint1_irq(unsigned int irq
)
422 icu1_set(MSYSINT1REG
, 1 << SYSINT1_IRQ_TO_PIN(irq
));
424 return 0; /* never anything pending */
427 static void shutdown_sysint1_irq(unsigned int irq
)
429 icu1_clear(MSYSINT1REG
, 1 << SYSINT1_IRQ_TO_PIN(irq
));
432 static void enable_sysint1_irq(unsigned int irq
)
434 icu1_set(MSYSINT1REG
, 1 << SYSINT1_IRQ_TO_PIN(irq
));
437 #define disable_sysint1_irq shutdown_sysint1_irq
438 #define ack_sysint1_irq shutdown_sysint1_irq
440 static void end_sysint1_irq(unsigned int irq
)
442 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
443 icu1_set(MSYSINT1REG
, 1 << SYSINT1_IRQ_TO_PIN(irq
));
446 static struct irq_chip sysint1_irq_type
= {
447 .typename
= "SYSINT1",
448 .startup
= startup_sysint1_irq
,
449 .shutdown
= shutdown_sysint1_irq
,
450 .enable
= enable_sysint1_irq
,
451 .disable
= disable_sysint1_irq
,
452 .ack
= ack_sysint1_irq
,
453 .end
= end_sysint1_irq
,
456 static unsigned int startup_sysint2_irq(unsigned int irq
)
458 icu2_set(MSYSINT2REG
, 1 << SYSINT2_IRQ_TO_PIN(irq
));
460 return 0; /* never anything pending */
463 static void shutdown_sysint2_irq(unsigned int irq
)
465 icu2_clear(MSYSINT2REG
, 1 << SYSINT2_IRQ_TO_PIN(irq
));
468 static void enable_sysint2_irq(unsigned int irq
)
470 icu2_set(MSYSINT2REG
, 1 << SYSINT2_IRQ_TO_PIN(irq
));
473 #define disable_sysint2_irq shutdown_sysint2_irq
474 #define ack_sysint2_irq shutdown_sysint2_irq
476 static void end_sysint2_irq(unsigned int irq
)
478 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
479 icu2_set(MSYSINT2REG
, 1 << SYSINT2_IRQ_TO_PIN(irq
));
482 static struct irq_chip sysint2_irq_type
= {
483 .typename
= "SYSINT2",
484 .startup
= startup_sysint2_irq
,
485 .shutdown
= shutdown_sysint2_irq
,
486 .enable
= enable_sysint2_irq
,
487 .disable
= disable_sysint2_irq
,
488 .ack
= ack_sysint2_irq
,
489 .end
= end_sysint2_irq
,
492 static inline int set_sysint1_assign(unsigned int irq
, unsigned char assign
)
494 struct irq_desc
*desc
= irq_desc
+ irq
;
495 uint16_t intassign0
, intassign1
;
498 pin
= SYSINT1_IRQ_TO_PIN(irq
);
500 spin_lock_irq(&desc
->lock
);
502 intassign0
= icu1_read(INTASSIGN0
);
503 intassign1
= icu1_read(INTASSIGN1
);
507 intassign0
&= ~INTASSIGN_MASK
;
508 intassign0
|= (uint16_t)assign
;
511 intassign0
&= ~(INTASSIGN_MASK
<< 3);
512 intassign0
|= (uint16_t)assign
<< 3;
515 intassign0
&= ~(INTASSIGN_MASK
<< 6);
516 intassign0
|= (uint16_t)assign
<< 6;
519 intassign0
&= ~(INTASSIGN_MASK
<< 9);
520 intassign0
|= (uint16_t)assign
<< 9;
523 intassign0
&= ~(INTASSIGN_MASK
<< 12);
524 intassign0
|= (uint16_t)assign
<< 12;
527 intassign1
&= ~INTASSIGN_MASK
;
528 intassign1
|= (uint16_t)assign
;
531 intassign1
&= ~(INTASSIGN_MASK
<< 6);
532 intassign1
|= (uint16_t)assign
<< 6;
535 intassign1
&= ~(INTASSIGN_MASK
<< 9);
536 intassign1
|= (uint16_t)assign
<< 9;
542 sysint1_assign
[pin
] = assign
;
543 icu1_write(INTASSIGN0
, intassign0
);
544 icu1_write(INTASSIGN1
, intassign1
);
546 spin_unlock_irq(&desc
->lock
);
551 static inline int set_sysint2_assign(unsigned int irq
, unsigned char assign
)
553 struct irq_desc
*desc
= irq_desc
+ irq
;
554 uint16_t intassign2
, intassign3
;
557 pin
= SYSINT2_IRQ_TO_PIN(irq
);
559 spin_lock_irq(&desc
->lock
);
561 intassign2
= icu1_read(INTASSIGN2
);
562 intassign3
= icu1_read(INTASSIGN3
);
566 intassign2
&= ~INTASSIGN_MASK
;
567 intassign2
|= (uint16_t)assign
;
570 intassign2
&= ~(INTASSIGN_MASK
<< 3);
571 intassign2
|= (uint16_t)assign
<< 3;
574 intassign2
&= ~(INTASSIGN_MASK
<< 6);
575 intassign2
|= (uint16_t)assign
<< 6;
578 intassign2
&= ~(INTASSIGN_MASK
<< 9);
579 intassign2
|= (uint16_t)assign
<< 9;
582 intassign2
&= ~(INTASSIGN_MASK
<< 12);
583 intassign2
|= (uint16_t)assign
<< 12;
586 intassign3
&= ~INTASSIGN_MASK
;
587 intassign3
|= (uint16_t)assign
;
590 intassign3
&= ~(INTASSIGN_MASK
<< 3);
591 intassign3
|= (uint16_t)assign
<< 3;
594 intassign3
&= ~(INTASSIGN_MASK
<< 6);
595 intassign3
|= (uint16_t)assign
<< 6;
598 intassign3
&= ~(INTASSIGN_MASK
<< 9);
599 intassign3
|= (uint16_t)assign
<< 9;
602 intassign3
&= ~(INTASSIGN_MASK
<< 12);
603 intassign3
|= (uint16_t)assign
<< 12;
609 sysint2_assign
[pin
] = assign
;
610 icu1_write(INTASSIGN2
, intassign2
);
611 icu1_write(INTASSIGN3
, intassign3
);
613 spin_unlock_irq(&desc
->lock
);
618 int vr41xx_set_intassign(unsigned int irq
, unsigned char intassign
)
620 int retval
= -EINVAL
;
622 if (current_cpu_data
.cputype
!= CPU_VR4133
)
625 if (intassign
> INTASSIGN_MAX
)
628 if (irq
>= SYSINT1_IRQ_BASE
&& irq
<= SYSINT1_IRQ_LAST
)
629 retval
= set_sysint1_assign(irq
, intassign
);
630 else if (irq
>= SYSINT2_IRQ_BASE
&& irq
<= SYSINT2_IRQ_LAST
)
631 retval
= set_sysint2_assign(irq
, intassign
);
636 EXPORT_SYMBOL(vr41xx_set_intassign
);
638 static int icu_get_irq(unsigned int irq
)
640 uint16_t pend1
, pend2
;
641 uint16_t mask1
, mask2
;
644 pend1
= icu1_read(SYSINT1REG
);
645 mask1
= icu1_read(MSYSINT1REG
);
647 pend2
= icu2_read(SYSINT2REG
);
648 mask2
= icu2_read(MSYSINT2REG
);
654 for (i
= 0; i
< 16; i
++) {
655 if (irq
== INT_TO_IRQ(sysint1_assign
[i
]) && (mask1
& (1 << i
)))
656 return SYSINT1_IRQ(i
);
661 for (i
= 0; i
< 16; i
++) {
662 if (irq
== INT_TO_IRQ(sysint2_assign
[i
]) && (mask2
& (1 << i
)))
663 return SYSINT2_IRQ(i
);
667 printk(KERN_ERR
"spurious ICU interrupt: %04x,%04x\n", pend1
, pend2
);
669 atomic_inc(&irq_err_count
);
674 static int __init
vr41xx_icu_init(void)
676 unsigned long icu1_start
, icu2_start
;
679 switch (current_cpu_data
.cputype
) {
682 icu1_start
= ICU1_TYPE1_BASE
;
683 icu2_start
= ICU2_TYPE1_BASE
;
688 icu1_start
= ICU1_TYPE2_BASE
;
689 icu2_start
= ICU2_TYPE2_BASE
;
692 printk(KERN_ERR
"ICU: Unexpected CPU of NEC VR4100 series\n");
696 if (request_mem_region(icu1_start
, ICU1_SIZE
, "ICU") == NULL
)
699 if (request_mem_region(icu2_start
, ICU2_SIZE
, "ICU") == NULL
) {
700 release_mem_region(icu1_start
, ICU1_SIZE
);
704 icu1_base
= ioremap(icu1_start
, ICU1_SIZE
);
705 if (icu1_base
== NULL
) {
706 release_mem_region(icu1_start
, ICU1_SIZE
);
707 release_mem_region(icu2_start
, ICU2_SIZE
);
711 icu2_base
= ioremap(icu2_start
, ICU2_SIZE
);
712 if (icu2_base
== NULL
) {
714 release_mem_region(icu1_start
, ICU1_SIZE
);
715 release_mem_region(icu2_start
, ICU2_SIZE
);
719 icu1_write(MSYSINT1REG
, 0);
720 icu1_write(MGIUINTLREG
, 0xffff);
722 icu2_write(MSYSINT2REG
, 0);
723 icu2_write(MGIUINTHREG
, 0xffff);
725 for (i
= SYSINT1_IRQ_BASE
; i
<= SYSINT1_IRQ_LAST
; i
++)
726 irq_desc
[i
].chip
= &sysint1_irq_type
;
728 for (i
= SYSINT2_IRQ_BASE
; i
<= SYSINT2_IRQ_LAST
; i
++)
729 irq_desc
[i
].chip
= &sysint2_irq_type
;
731 cascade_irq(INT0_IRQ
, icu_get_irq
);
732 cascade_irq(INT1_IRQ
, icu_get_irq
);
733 cascade_irq(INT2_IRQ
, icu_get_irq
);
734 cascade_irq(INT3_IRQ
, icu_get_irq
);
735 cascade_irq(INT4_IRQ
, icu_get_irq
);
740 core_initcall(vr41xx_icu_init
);