2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#134 $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
55 /***************************** Lookup Tables **********************************/
56 char *ahc_chip_names
[] =
73 static const u_int num_chip_names
= NUM_ELEMENTS(ahc_chip_names
);
76 * Hardware error codes.
78 struct ahc_hard_error_entry
{
83 static struct ahc_hard_error_entry ahc_hard_errors
[] = {
84 { ILLHADDR
, "Illegal Host Access" },
85 { ILLSADDR
, "Illegal Sequencer Address referrenced" },
86 { ILLOPCODE
, "Illegal Opcode in sequencer program" },
87 { SQPARERR
, "Sequencer Parity Error" },
88 { DPARERR
, "Data-path Parity Error" },
89 { MPARERR
, "Scratch or SCB Memory Parity Error" },
90 { PCIERRSTAT
, "PCI Error detected" },
91 { CIOPARERR
, "CIOBUS Parity Error" },
93 static const u_int num_errors
= NUM_ELEMENTS(ahc_hard_errors
);
95 static struct ahc_phase_table_entry ahc_phase_table
[] =
97 { P_DATAOUT
, MSG_NOOP
, "in Data-out phase" },
98 { P_DATAIN
, MSG_INITIATOR_DET_ERR
, "in Data-in phase" },
99 { P_DATAOUT_DT
, MSG_NOOP
, "in DT Data-out phase" },
100 { P_DATAIN_DT
, MSG_INITIATOR_DET_ERR
, "in DT Data-in phase" },
101 { P_COMMAND
, MSG_NOOP
, "in Command phase" },
102 { P_MESGOUT
, MSG_NOOP
, "in Message-out phase" },
103 { P_STATUS
, MSG_INITIATOR_DET_ERR
, "in Status phase" },
104 { P_MESGIN
, MSG_PARITY_ERROR
, "in Message-in phase" },
105 { P_BUSFREE
, MSG_NOOP
, "while idle" },
106 { 0, MSG_NOOP
, "in unknown phase" }
110 * In most cases we only wish to itterate over real phases, so
111 * exclude the last element from the count.
113 static const u_int num_phases
= NUM_ELEMENTS(ahc_phase_table
) - 1;
116 * Valid SCSIRATE values. (p. 3-17)
117 * Provides a mapping of tranfer periods in ns to the proper value to
118 * stick in the scsixfer reg.
120 static struct ahc_syncrate ahc_syncrates
[] =
122 /* ultra2 fast/ultra period rate */
123 { 0x42, 0x000, 9, "80.0" },
124 { 0x03, 0x000, 10, "40.0" },
125 { 0x04, 0x000, 11, "33.0" },
126 { 0x05, 0x100, 12, "20.0" },
127 { 0x06, 0x110, 15, "16.0" },
128 { 0x07, 0x120, 18, "13.4" },
129 { 0x08, 0x000, 25, "10.0" },
130 { 0x19, 0x010, 31, "8.0" },
131 { 0x1a, 0x020, 37, "6.67" },
132 { 0x1b, 0x030, 43, "5.7" },
133 { 0x1c, 0x040, 50, "5.0" },
134 { 0x00, 0x050, 56, "4.4" },
135 { 0x00, 0x060, 62, "4.0" },
136 { 0x00, 0x070, 68, "3.6" },
137 { 0x00, 0x000, 0, NULL
}
140 /* Our Sequencer Program */
141 #include "aic7xxx_seq.h"
143 /**************************** Function Declarations ***************************/
144 static void ahc_force_renegotiation(struct ahc_softc
*ahc
,
145 struct ahc_devinfo
*devinfo
);
146 static struct ahc_tmode_tstate
*
147 ahc_alloc_tstate(struct ahc_softc
*ahc
,
148 u_int scsi_id
, char channel
);
149 #ifdef AHC_TARGET_MODE
150 static void ahc_free_tstate(struct ahc_softc
*ahc
,
151 u_int scsi_id
, char channel
, int force
);
153 static struct ahc_syncrate
*
154 ahc_devlimited_syncrate(struct ahc_softc
*ahc
,
155 struct ahc_initiator_tinfo
*,
159 static void ahc_update_pending_scbs(struct ahc_softc
*ahc
);
160 static void ahc_fetch_devinfo(struct ahc_softc
*ahc
,
161 struct ahc_devinfo
*devinfo
);
162 static void ahc_scb_devinfo(struct ahc_softc
*ahc
,
163 struct ahc_devinfo
*devinfo
,
165 static void ahc_assert_atn(struct ahc_softc
*ahc
);
166 static void ahc_setup_initiator_msgout(struct ahc_softc
*ahc
,
167 struct ahc_devinfo
*devinfo
,
169 static void ahc_build_transfer_msg(struct ahc_softc
*ahc
,
170 struct ahc_devinfo
*devinfo
);
171 static void ahc_construct_sdtr(struct ahc_softc
*ahc
,
172 struct ahc_devinfo
*devinfo
,
173 u_int period
, u_int offset
);
174 static void ahc_construct_wdtr(struct ahc_softc
*ahc
,
175 struct ahc_devinfo
*devinfo
,
177 static void ahc_construct_ppr(struct ahc_softc
*ahc
,
178 struct ahc_devinfo
*devinfo
,
179 u_int period
, u_int offset
,
180 u_int bus_width
, u_int ppr_options
);
181 static void ahc_clear_msg_state(struct ahc_softc
*ahc
);
182 static void ahc_handle_proto_violation(struct ahc_softc
*ahc
);
183 static void ahc_handle_message_phase(struct ahc_softc
*ahc
);
189 static int ahc_sent_msg(struct ahc_softc
*ahc
, ahc_msgtype type
,
190 u_int msgval
, int full
);
191 static int ahc_parse_msg(struct ahc_softc
*ahc
,
192 struct ahc_devinfo
*devinfo
);
193 static int ahc_handle_msg_reject(struct ahc_softc
*ahc
,
194 struct ahc_devinfo
*devinfo
);
195 static void ahc_handle_ign_wide_residue(struct ahc_softc
*ahc
,
196 struct ahc_devinfo
*devinfo
);
197 static void ahc_reinitialize_dataptrs(struct ahc_softc
*ahc
);
198 static void ahc_handle_devreset(struct ahc_softc
*ahc
,
199 struct ahc_devinfo
*devinfo
,
200 cam_status status
, char *message
,
202 #ifdef AHC_TARGET_MODE
203 static void ahc_setup_target_msgin(struct ahc_softc
*ahc
,
204 struct ahc_devinfo
*devinfo
,
208 static bus_dmamap_callback_t ahc_dmamap_cb
;
209 static void ahc_build_free_scb_list(struct ahc_softc
*ahc
);
210 static int ahc_init_scbdata(struct ahc_softc
*ahc
);
211 static void ahc_fini_scbdata(struct ahc_softc
*ahc
);
212 static void ahc_qinfifo_requeue(struct ahc_softc
*ahc
,
213 struct scb
*prev_scb
,
215 static int ahc_qinfifo_count(struct ahc_softc
*ahc
);
216 static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc
*ahc
,
217 u_int prev
, u_int scbptr
);
218 static void ahc_add_curscb_to_free_list(struct ahc_softc
*ahc
);
219 static u_int
ahc_rem_wscb(struct ahc_softc
*ahc
,
220 u_int scbpos
, u_int prev
);
221 static void ahc_reset_current_bus(struct ahc_softc
*ahc
);
223 static void ahc_dumpseq(struct ahc_softc
*ahc
);
225 static int ahc_loadseq(struct ahc_softc
*ahc
);
226 static int ahc_check_patch(struct ahc_softc
*ahc
,
227 struct patch
**start_patch
,
228 u_int start_instr
, u_int
*skip_addr
);
229 static void ahc_download_instr(struct ahc_softc
*ahc
,
230 u_int instrptr
, uint8_t *dconsts
);
231 #ifdef AHC_TARGET_MODE
232 static void ahc_queue_lstate_event(struct ahc_softc
*ahc
,
233 struct ahc_tmode_lstate
*lstate
,
237 static void ahc_update_scsiid(struct ahc_softc
*ahc
,
239 static int ahc_handle_target_cmd(struct ahc_softc
*ahc
,
240 struct target_cmd
*cmd
);
242 /************************* Sequencer Execution Control ************************/
244 * Restart the sequencer program from address zero
247 ahc_restart(struct ahc_softc
*ahc
)
252 /* No more pending messages. */
253 ahc_clear_msg_state(ahc
);
255 ahc_outb(ahc
, SCSISIGO
, 0); /* De-assert BSY */
256 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
); /* No message to send */
257 ahc_outb(ahc
, SXFRCTL1
, ahc_inb(ahc
, SXFRCTL1
) & ~BITBUCKET
);
258 ahc_outb(ahc
, LASTPHASE
, P_BUSFREE
);
259 ahc_outb(ahc
, SAVED_SCSIID
, 0xFF);
260 ahc_outb(ahc
, SAVED_LUN
, 0xFF);
263 * Ensure that the sequencer's idea of TQINPOS
264 * matches our own. The sequencer increments TQINPOS
265 * only after it sees a DMA complete and a reset could
266 * occur before the increment leaving the kernel to believe
267 * the command arrived but the sequencer to not.
269 ahc_outb(ahc
, TQINPOS
, ahc
->tqinfifonext
);
271 /* Always allow reselection */
272 ahc_outb(ahc
, SCSISEQ
,
273 ahc_inb(ahc
, SCSISEQ_TEMPLATE
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
274 if ((ahc
->features
& AHC_CMD_CHAN
) != 0) {
275 /* Ensure that no DMA operations are in progress */
276 ahc_outb(ahc
, CCSCBCNT
, 0);
277 ahc_outb(ahc
, CCSGCTL
, 0);
278 ahc_outb(ahc
, CCSCBCTL
, 0);
281 * If we were in the process of DMA'ing SCB data into
282 * an SCB, replace that SCB on the free list. This prevents
285 if ((ahc_inb(ahc
, SEQ_FLAGS2
) & SCB_DMA
) != 0) {
286 ahc_add_curscb_to_free_list(ahc
);
287 ahc_outb(ahc
, SEQ_FLAGS2
,
288 ahc_inb(ahc
, SEQ_FLAGS2
) & ~SCB_DMA
);
290 ahc_outb(ahc
, MWI_RESIDUAL
, 0);
291 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
);
292 ahc_outb(ahc
, SEQADDR0
, 0);
293 ahc_outb(ahc
, SEQADDR1
, 0);
297 /************************* Input/Output Queues ********************************/
299 ahc_run_qoutfifo(struct ahc_softc
*ahc
)
304 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_POSTREAD
);
305 while (ahc
->qoutfifo
[ahc
->qoutfifonext
] != SCB_LIST_NULL
) {
307 scb_index
= ahc
->qoutfifo
[ahc
->qoutfifonext
];
308 if ((ahc
->qoutfifonext
& 0x03) == 0x03) {
312 * Clear 32bits of QOUTFIFO at a time
313 * so that we don't clobber an incoming
314 * byte DMA to the array on architectures
315 * that only support 32bit load and store
318 modnext
= ahc
->qoutfifonext
& ~0x3;
319 *((uint32_t *)(&ahc
->qoutfifo
[modnext
])) = 0xFFFFFFFFUL
;
320 ahc_dmamap_sync(ahc
, ahc
->shared_data_dmat
,
321 ahc
->shared_data_dmamap
,
322 /*offset*/modnext
, /*len*/4,
323 BUS_DMASYNC_PREREAD
);
327 scb
= ahc_lookup_scb(ahc
, scb_index
);
329 printf("%s: WARNING no command for scb %d "
330 "(cmdcmplt)\nQOUTPOS = %d\n",
331 ahc_name(ahc
), scb_index
,
332 (ahc
->qoutfifonext
- 1) & 0xFF);
337 * Save off the residual
340 ahc_update_residual(ahc
, scb
);
346 ahc_run_untagged_queues(struct ahc_softc
*ahc
)
350 for (i
= 0; i
< 16; i
++)
351 ahc_run_untagged_queue(ahc
, &ahc
->untagged_queues
[i
]);
355 ahc_run_untagged_queue(struct ahc_softc
*ahc
, struct scb_tailq
*queue
)
359 if (ahc
->untagged_queue_lock
!= 0)
362 if ((scb
= TAILQ_FIRST(queue
)) != NULL
363 && (scb
->flags
& SCB_ACTIVE
) == 0) {
364 scb
->flags
|= SCB_ACTIVE
;
365 ahc_queue_scb(ahc
, scb
);
369 /************************* Interrupt Handling *********************************/
371 ahc_handle_brkadrint(struct ahc_softc
*ahc
)
374 * We upset the sequencer :-(
375 * Lookup the error message
380 error
= ahc_inb(ahc
, ERROR
);
381 for (i
= 0; error
!= 1 && i
< num_errors
; i
++)
383 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
384 ahc_name(ahc
), ahc_hard_errors
[i
].errmesg
,
385 ahc_inb(ahc
, SEQADDR0
) |
386 (ahc_inb(ahc
, SEQADDR1
) << 8));
388 ahc_dump_card_state(ahc
);
390 /* Tell everyone that this HBA is no longer available */
391 ahc_abort_scbs(ahc
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
392 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, ROLE_UNKNOWN
,
395 /* Disable all interrupt sources by resetting the controller */
400 ahc_handle_seqint(struct ahc_softc
*ahc
, u_int intstat
)
403 struct ahc_devinfo devinfo
;
405 ahc_fetch_devinfo(ahc
, &devinfo
);
408 * Clear the upper byte that holds SEQINT status
409 * codes and clear the SEQINT bit. We will unpause
410 * the sequencer, if appropriate, after servicing
413 ahc_outb(ahc
, CLRINT
, CLRSEQINT
);
414 switch (intstat
& SEQINT_MASK
) {
418 struct hardware_scb
*hscb
;
421 * Set the default return value to 0 (don't
422 * send sense). The sense code will change
425 ahc_outb(ahc
, RETURN_1
, 0);
428 * The sequencer will notify us when a command
429 * has an error that would be of interest to
430 * the kernel. This allows us to leave the sequencer
431 * running in the common case of command completes
432 * without error. The sequencer will already have
433 * dma'd the SCB back up to us, so we can reference
434 * the in kernel copy directly.
436 scb_index
= ahc_inb(ahc
, SCB_TAG
);
437 scb
= ahc_lookup_scb(ahc
, scb_index
);
439 ahc_print_devinfo(ahc
, &devinfo
);
440 printf("ahc_intr - referenced scb "
441 "not valid during seqint 0x%x scb(%d)\n",
443 ahc_dump_card_state(ahc
);
450 /* Don't want to clobber the original sense code */
451 if ((scb
->flags
& SCB_SENSE
) != 0) {
453 * Clear the SCB_SENSE Flag and have
454 * the sequencer do a normal command
457 scb
->flags
&= ~SCB_SENSE
;
458 ahc_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
461 ahc_set_transaction_status(scb
, CAM_SCSI_STATUS_ERROR
);
462 /* Freeze the queue until the client sees the error. */
463 ahc_freeze_devq(ahc
, scb
);
465 ahc_set_scsi_status(scb
, hscb
->shared_data
.status
.scsi_status
);
466 switch (hscb
->shared_data
.status
.scsi_status
) {
468 printf("%s: Interrupted for staus of 0???\n",
471 case SCSI_STATUS_CMD_TERMINATED
:
472 case SCSI_STATUS_CHECK_COND
:
474 struct ahc_dma_seg
*sg
;
475 struct scsi_sense
*sc
;
476 struct ahc_initiator_tinfo
*targ_info
;
477 struct ahc_tmode_tstate
*tstate
;
478 struct ahc_transinfo
*tinfo
;
480 if (ahc_debug
& AHC_SHOW_SENSE
) {
481 ahc_print_path(ahc
, scb
);
482 printf("SCB %d: requests Check Status\n",
487 if (ahc_perform_autosense(scb
) == 0)
490 targ_info
= ahc_fetch_transinfo(ahc
,
495 tinfo
= &targ_info
->curr
;
497 sc
= (struct scsi_sense
*)(&hscb
->shared_data
.cdb
);
499 * Save off the residual if there is one.
501 ahc_update_residual(ahc
, scb
);
503 if (ahc_debug
& AHC_SHOW_SENSE
) {
504 ahc_print_path(ahc
, scb
);
505 printf("Sending Sense\n");
508 sg
->addr
= ahc_get_sense_bufaddr(ahc
, scb
);
509 sg
->len
= ahc_get_sense_bufsize(ahc
, scb
);
510 sg
->len
|= AHC_DMA_LAST_SEG
;
512 /* Fixup byte order */
513 sg
->addr
= ahc_htole32(sg
->addr
);
514 sg
->len
= ahc_htole32(sg
->len
);
516 sc
->opcode
= REQUEST_SENSE
;
518 if (tinfo
->protocol_version
<= SCSI_REV_2
519 && SCB_GET_LUN(scb
) < 8)
520 sc
->byte2
= SCB_GET_LUN(scb
) << 5;
523 sc
->length
= sg
->len
;
527 * We can't allow the target to disconnect.
528 * This will be an untagged transaction and
529 * having the target disconnect will make this
530 * transaction indestinguishable from outstanding
531 * tagged transactions.
536 * This request sense could be because the
537 * the device lost power or in some other
538 * way has lost our transfer negotiations.
539 * Renegotiate if appropriate. Unit attention
540 * errors will be reported before any data
543 if (ahc_get_residual(scb
)
544 == ahc_get_transfer_length(scb
)) {
545 ahc_update_neg_request(ahc
, &devinfo
,
547 AHC_NEG_IF_NON_ASYNC
);
549 if (tstate
->auto_negotiate
& devinfo
.target_mask
) {
550 hscb
->control
|= MK_MESSAGE
;
551 scb
->flags
&= ~SCB_NEGOTIATE
;
552 scb
->flags
|= SCB_AUTO_NEGOTIATE
;
554 hscb
->cdb_len
= sizeof(*sc
);
555 hscb
->dataptr
= sg
->addr
;
556 hscb
->datacnt
= sg
->len
;
557 hscb
->sgptr
= scb
->sg_list_phys
| SG_FULL_RESID
;
558 hscb
->sgptr
= ahc_htole32(hscb
->sgptr
);
560 scb
->flags
|= SCB_SENSE
;
561 ahc_qinfifo_requeue_tail(ahc
, scb
);
562 ahc_outb(ahc
, RETURN_1
, SEND_SENSE
);
564 * Ensure we have enough time to actually
565 * retrieve the sense.
567 ahc_scb_timer_reset(scb
, 5 * 1000000);
577 /* Ensure we don't leave the selection hardware on */
578 ahc_outb(ahc
, SCSISEQ
,
579 ahc_inb(ahc
, SCSISEQ
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
581 printf("%s:%c:%d: no active SCB for reconnecting "
582 "target - issuing BUS DEVICE RESET\n",
583 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
);
584 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
585 "ARG_1 == 0x%x ACCUM = 0x%x\n",
586 ahc_inb(ahc
, SAVED_SCSIID
), ahc_inb(ahc
, SAVED_LUN
),
587 ahc_inb(ahc
, ARG_1
), ahc_inb(ahc
, ACCUM
));
588 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
590 ahc_inb(ahc
, SEQ_FLAGS
), ahc_inb(ahc
, SCBPTR
),
591 ahc_index_busy_tcl(ahc
,
592 BUILD_TCL(ahc_inb(ahc
, SAVED_SCSIID
),
593 ahc_inb(ahc
, SAVED_LUN
))),
594 ahc_inb(ahc
, SINDEX
));
595 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
596 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
597 ahc_inb(ahc
, SCSIID
), ahc_inb(ahc
, SCB_SCSIID
),
598 ahc_inb(ahc
, SCB_LUN
), ahc_inb(ahc
, SCB_TAG
),
599 ahc_inb(ahc
, SCB_CONTROL
));
600 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
601 ahc_inb(ahc
, SCSIBUSL
), ahc_inb(ahc
, SCSISIGI
));
602 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc
, SXFRCTL0
));
603 printf("SEQCTL == 0x%x\n", ahc_inb(ahc
, SEQCTL
));
604 ahc_dump_card_state(ahc
);
605 ahc
->msgout_buf
[0] = MSG_BUS_DEV_RESET
;
607 ahc
->msgout_index
= 0;
608 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
609 ahc_outb(ahc
, MSG_OUT
, HOST_MSG
);
615 u_int rejbyte
= ahc_inb(ahc
, ACCUM
);
616 printf("%s:%c:%d: Warning - unknown message received from "
617 "target (0x%x). Rejecting\n",
618 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
, rejbyte
);
621 case PROTO_VIOLATION
:
623 ahc_handle_proto_violation(ahc
);
627 ahc_handle_ign_wide_residue(ahc
, &devinfo
);
630 ahc_reinitialize_dataptrs(ahc
);
636 lastphase
= ahc_inb(ahc
, LASTPHASE
);
637 printf("%s:%c:%d: unknown scsi bus phase %x, "
638 "lastphase = 0x%x. Attempting to continue\n",
639 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
640 lastphase
, ahc_inb(ahc
, SCSISIGI
));
647 lastphase
= ahc_inb(ahc
, LASTPHASE
);
648 printf("%s:%c:%d: Missed busfree. "
649 "Lastphase = 0x%x, Curphase = 0x%x\n",
650 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
651 lastphase
, ahc_inb(ahc
, SCSISIGI
));
658 * The sequencer has encountered a message phase
659 * that requires host assistance for completion.
660 * While handling the message phase(s), we will be
661 * notified by the sequencer after each byte is
662 * transfered so we can track bus phase changes.
664 * If this is the first time we've seen a HOST_MSG_LOOP
665 * interrupt, initialize the state of the host message
668 if (ahc
->msg_type
== MSG_TYPE_NONE
) {
673 bus_phase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
674 if (bus_phase
!= P_MESGIN
675 && bus_phase
!= P_MESGOUT
) {
676 printf("ahc_intr: HOST_MSG_LOOP bad "
680 * Probably transitioned to bus free before
681 * we got here. Just punt the message.
683 ahc_clear_intstat(ahc
);
688 scb_index
= ahc_inb(ahc
, SCB_TAG
);
689 scb
= ahc_lookup_scb(ahc
, scb_index
);
690 if (devinfo
.role
== ROLE_INITIATOR
) {
692 panic("HOST_MSG_LOOP with "
693 "invalid SCB %x\n", scb_index
);
695 if (bus_phase
== P_MESGOUT
)
696 ahc_setup_initiator_msgout(ahc
,
701 MSG_TYPE_INITIATOR_MSGIN
;
702 ahc
->msgin_index
= 0;
705 #ifdef AHC_TARGET_MODE
707 if (bus_phase
== P_MESGOUT
) {
709 MSG_TYPE_TARGET_MSGOUT
;
710 ahc
->msgin_index
= 0;
713 ahc_setup_target_msgin(ahc
,
720 ahc_handle_message_phase(ahc
);
726 * If we've cleared the parity error interrupt
727 * but the sequencer still believes that SCSIPERR
728 * is true, it must be that the parity error is
729 * for the currently presented byte on the bus,
730 * and we are not in a phase (data-in) where we will
731 * eventually ack this byte. Ack the byte and
732 * throw it away in the hope that the target will
733 * take us to message out to deliver the appropriate
736 if ((intstat
& SCSIINT
) == 0
737 && (ahc_inb(ahc
, SSTAT1
) & SCSIPERR
) != 0) {
739 if ((ahc
->features
& AHC_DT
) == 0) {
743 * The hardware will only let you ack bytes
744 * if the expected phase in SCSISIGO matches
745 * the current phase. Make sure this is
746 * currently the case.
748 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
749 ahc_outb(ahc
, LASTPHASE
, curphase
);
750 ahc_outb(ahc
, SCSISIGO
, curphase
);
752 if ((ahc_inb(ahc
, SCSISIGI
) & (CDI
|MSGI
)) == 0) {
756 * In a data phase. Faster to bitbucket
757 * the data than to individually ack each
758 * byte. This is also the only strategy
759 * that will work with AUTOACK enabled.
761 ahc_outb(ahc
, SXFRCTL1
,
762 ahc_inb(ahc
, SXFRCTL1
) | BITBUCKET
);
764 while (--wait
!= 0) {
765 if ((ahc_inb(ahc
, SCSISIGI
)
770 ahc_outb(ahc
, SXFRCTL1
,
771 ahc_inb(ahc
, SXFRCTL1
) & ~BITBUCKET
);
776 ahc_print_devinfo(ahc
, &devinfo
);
777 printf("Unable to clear parity error. "
779 scb_index
= ahc_inb(ahc
, SCB_TAG
);
780 scb
= ahc_lookup_scb(ahc
, scb_index
);
782 ahc_set_transaction_status(scb
,
784 ahc_reset_channel(ahc
, devinfo
.channel
,
788 ahc_inb(ahc
, SCSIDATL
);
796 * When the sequencer detects an overrun, it
797 * places the controller in "BITBUCKET" mode
798 * and allows the target to complete its transfer.
799 * Unfortunately, none of the counters get updated
800 * when the controller is in this mode, so we have
801 * no way of knowing how large the overrun was.
803 u_int scbindex
= ahc_inb(ahc
, SCB_TAG
);
804 u_int lastphase
= ahc_inb(ahc
, LASTPHASE
);
807 scb
= ahc_lookup_scb(ahc
, scbindex
);
808 for (i
= 0; i
< num_phases
; i
++) {
809 if (lastphase
== ahc_phase_table
[i
].phase
)
812 ahc_print_path(ahc
, scb
);
813 printf("data overrun detected %s."
815 ahc_phase_table
[i
].phasemsg
,
817 ahc_print_path(ahc
, scb
);
818 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
819 ahc_inb(ahc
, SEQ_FLAGS
) & DPHASE
? "Have" : "Haven't",
820 ahc_get_transfer_length(scb
), scb
->sg_count
);
821 if (scb
->sg_count
> 0) {
822 for (i
= 0; i
< scb
->sg_count
; i
++) {
824 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
826 (ahc_le32toh(scb
->sg_list
[i
].len
) >> 24
827 & SG_HIGH_ADDR_BITS
),
828 ahc_le32toh(scb
->sg_list
[i
].addr
),
829 ahc_le32toh(scb
->sg_list
[i
].len
)
834 * Set this and it will take effect when the
835 * target does a command complete.
837 ahc_freeze_devq(ahc
, scb
);
838 if ((scb
->flags
& SCB_SENSE
) == 0) {
839 ahc_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
841 scb
->flags
&= ~SCB_SENSE
;
842 ahc_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
846 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
848 * Clear the channel in case we return
849 * to data phase later.
851 ahc_outb(ahc
, SXFRCTL0
,
852 ahc_inb(ahc
, SXFRCTL0
) | CLRSTCNT
|CLRCHN
);
853 ahc_outb(ahc
, SXFRCTL0
,
854 ahc_inb(ahc
, SXFRCTL0
) | CLRSTCNT
|CLRCHN
);
856 if ((ahc
->flags
& AHC_39BIT_ADDRESSING
) != 0) {
859 /* Ensure HHADDR is 0 for future DMA operations. */
860 dscommand1
= ahc_inb(ahc
, DSCOMMAND1
);
861 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
| HADDLDSEL0
);
862 ahc_outb(ahc
, HADDR
, 0);
863 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
);
871 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
872 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
874 scbindex
= ahc_inb(ahc
, SCB_TAG
);
875 scb
= ahc_lookup_scb(ahc
, scbindex
);
877 && (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
879 * Ensure that we didn't put a second instance of this
880 * SCB into the QINFIFO.
882 ahc_search_qinfifo(ahc
, SCB_GET_TARGET(ahc
, scb
),
883 SCB_GET_CHANNEL(ahc
, scb
),
884 SCB_GET_LUN(scb
), scb
->hscb
->tag
,
885 ROLE_INITIATOR
, /*status*/0,
891 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc
));
892 ahc_dump_card_state(ahc
);
900 scbptr
= ahc_inb(ahc
, SCBPTR
);
901 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
902 scbptr
, ahc_inb(ahc
, ARG_1
),
903 ahc
->scb_data
->hscbs
[scbptr
].tag
);
904 ahc_dump_card_state(ahc
);
910 printf("%s: BTT calculation out of range\n", ahc_name(ahc
));
911 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
912 "ARG_1 == 0x%x ACCUM = 0x%x\n",
913 ahc_inb(ahc
, SAVED_SCSIID
), ahc_inb(ahc
, SAVED_LUN
),
914 ahc_inb(ahc
, ARG_1
), ahc_inb(ahc
, ACCUM
));
915 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
916 "SINDEX == 0x%x\n, A == 0x%x\n",
917 ahc_inb(ahc
, SEQ_FLAGS
), ahc_inb(ahc
, SCBPTR
),
918 ahc_index_busy_tcl(ahc
,
919 BUILD_TCL(ahc_inb(ahc
, SAVED_SCSIID
),
920 ahc_inb(ahc
, SAVED_LUN
))),
921 ahc_inb(ahc
, SINDEX
),
922 ahc_inb(ahc
, ACCUM
));
923 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
924 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
925 ahc_inb(ahc
, SCSIID
), ahc_inb(ahc
, SCB_SCSIID
),
926 ahc_inb(ahc
, SCB_LUN
), ahc_inb(ahc
, SCB_TAG
),
927 ahc_inb(ahc
, SCB_CONTROL
));
928 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
929 ahc_inb(ahc
, SCSIBUSL
), ahc_inb(ahc
, SCSISIGI
));
930 ahc_dump_card_state(ahc
);
935 printf("ahc_intr: seqint, "
936 "intstat == 0x%x, scsisigi = 0x%x\n",
937 intstat
, ahc_inb(ahc
, SCSISIGI
));
942 * The sequencer is paused immediately on
943 * a SEQINT, so we should restart it when
950 ahc_handle_scsiint(struct ahc_softc
*ahc
, u_int intstat
)
959 if ((ahc
->features
& AHC_TWIN
) != 0
960 && ((ahc_inb(ahc
, SBLKCTL
) & SELBUSB
) != 0))
964 intr_channel
= cur_channel
;
966 if ((ahc
->features
& AHC_ULTRA2
) != 0)
967 status0
= ahc_inb(ahc
, SSTAT0
) & IOERR
;
970 status
= ahc_inb(ahc
, SSTAT1
) & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
971 if (status
== 0 && status0
== 0) {
972 if ((ahc
->features
& AHC_TWIN
) != 0) {
973 /* Try the other channel */
974 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) ^ SELBUSB
);
975 status
= ahc_inb(ahc
, SSTAT1
)
976 & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
977 intr_channel
= (cur_channel
== 'A') ? 'B' : 'A';
980 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc
));
981 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
987 /* Make sure the sequencer is in a safe location. */
988 ahc_clear_critical_section(ahc
);
990 scb_index
= ahc_inb(ahc
, SCB_TAG
);
991 scb
= ahc_lookup_scb(ahc
, scb_index
);
993 && (ahc_inb(ahc
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
996 if ((ahc
->features
& AHC_ULTRA2
) != 0
997 && (status0
& IOERR
) != 0) {
1000 now_lvd
= ahc_inb(ahc
, SBLKCTL
) & ENAB40
;
1001 printf("%s: Transceiver State Has Changed to %s mode\n",
1002 ahc_name(ahc
), now_lvd
? "LVD" : "SE");
1003 ahc_outb(ahc
, CLRSINT0
, CLRIOERR
);
1005 * When transitioning to SE mode, the reset line
1006 * glitches, triggering an arbitration bug in some
1007 * Ultra2 controllers. This bug is cleared when we
1008 * assert the reset line. Since a reset glitch has
1009 * already occurred with this transition and a
1010 * transceiver state change is handled just like
1011 * a bus reset anyway, asserting the reset line
1012 * ourselves is safe.
1014 ahc_reset_channel(ahc
, intr_channel
,
1015 /*Initiate Reset*/now_lvd
== 0);
1016 } else if ((status
& SCSIRSTI
) != 0) {
1017 printf("%s: Someone reset channel %c\n",
1018 ahc_name(ahc
), intr_channel
);
1019 if (intr_channel
!= cur_channel
)
1020 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) ^ SELBUSB
);
1021 ahc_reset_channel(ahc
, intr_channel
, /*Initiate Reset*/FALSE
);
1022 } else if ((status
& SCSIPERR
) != 0) {
1024 * Determine the bus phase and queue an appropriate message.
1025 * SCSIPERR is latched true as soon as a parity error
1026 * occurs. If the sequencer acked the transfer that
1027 * caused the parity error and the currently presented
1028 * transfer on the bus has correct parity, SCSIPERR will
1029 * be cleared by CLRSCSIPERR. Use this to determine if
1030 * we should look at the last phase the sequencer recorded,
1031 * or the current phase presented on the bus.
1033 struct ahc_devinfo devinfo
;
1043 lastphase
= ahc_inb(ahc
, LASTPHASE
);
1044 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
1045 sstat2
= ahc_inb(ahc
, SSTAT2
);
1046 ahc_outb(ahc
, CLRSINT1
, CLRSCSIPERR
);
1048 * For all phases save DATA, the sequencer won't
1049 * automatically ack a byte that has a parity error
1050 * in it. So the only way that the current phase
1051 * could be 'data-in' is if the parity error is for
1052 * an already acked byte in the data phase. During
1053 * synchronous data-in transfers, we may actually
1054 * ack bytes before latching the current phase in
1055 * LASTPHASE, leading to the discrepancy between
1056 * curphase and lastphase.
1058 if ((ahc_inb(ahc
, SSTAT1
) & SCSIPERR
) != 0
1059 || curphase
== P_DATAIN
|| curphase
== P_DATAIN_DT
)
1060 errorphase
= curphase
;
1062 errorphase
= lastphase
;
1064 for (i
= 0; i
< num_phases
; i
++) {
1065 if (errorphase
== ahc_phase_table
[i
].phase
)
1068 mesg_out
= ahc_phase_table
[i
].mesg_out
;
1071 if (SCB_IS_SILENT(scb
))
1074 ahc_print_path(ahc
, scb
);
1075 scb
->flags
|= SCB_TRANSMISSION_ERROR
;
1077 printf("%s:%c:%d: ", ahc_name(ahc
), intr_channel
,
1078 SCSIID_TARGET(ahc
, ahc_inb(ahc
, SAVED_SCSIID
)));
1079 scsirate
= ahc_inb(ahc
, SCSIRATE
);
1080 if (silent
== FALSE
) {
1081 printf("parity error detected %s. "
1082 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1083 ahc_phase_table
[i
].phasemsg
,
1084 ahc_inw(ahc
, SEQADDR0
),
1086 if ((ahc
->features
& AHC_DT
) != 0) {
1087 if ((sstat2
& CRCVALERR
) != 0)
1088 printf("\tCRC Value Mismatch\n");
1089 if ((sstat2
& CRCENDERR
) != 0)
1090 printf("\tNo terminal CRC packet "
1092 if ((sstat2
& CRCREQERR
) != 0)
1093 printf("\tIllegal CRC packet "
1095 if ((sstat2
& DUAL_EDGE_ERR
) != 0)
1096 printf("\tUnexpected %sDT Data Phase\n",
1097 (scsirate
& SINGLE_EDGE
)
1102 if ((ahc
->features
& AHC_DT
) != 0
1103 && (sstat2
& DUAL_EDGE_ERR
) != 0) {
1105 * This error applies regardless of
1106 * data direction, so ignore the value
1107 * in the phase table.
1109 mesg_out
= MSG_INITIATOR_DET_ERR
;
1113 * We've set the hardware to assert ATN if we
1114 * get a parity error on "in" phases, so all we
1115 * need to do is stuff the message buffer with
1116 * the appropriate message. "In" phases have set
1117 * mesg_out to something other than MSG_NOP.
1119 if (mesg_out
!= MSG_NOOP
) {
1120 if (ahc
->msg_type
!= MSG_TYPE_NONE
)
1121 ahc
->send_msg_perror
= TRUE
;
1123 ahc_outb(ahc
, MSG_OUT
, mesg_out
);
1126 * Force a renegotiation with this target just in
1127 * case we are out of sync for some external reason
1128 * unknown (or unreported) by the target.
1130 ahc_fetch_devinfo(ahc
, &devinfo
);
1131 ahc_force_renegotiation(ahc
, &devinfo
);
1133 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1135 } else if ((status
& SELTO
) != 0) {
1138 /* Stop the selection */
1139 ahc_outb(ahc
, SCSISEQ
, 0);
1141 /* No more pending messages */
1142 ahc_clear_msg_state(ahc
);
1144 /* Clear interrupt state */
1145 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENBUSFREE
);
1146 ahc_outb(ahc
, CLRSINT1
, CLRSELTIMEO
|CLRBUSFREE
|CLRSCSIPERR
);
1149 * Although the driver does not care about the
1150 * 'Selection in Progress' status bit, the busy
1151 * LED does. SELINGO is only cleared by a sucessfull
1152 * selection, so we must manually clear it to insure
1153 * the LED turns off just incase no future successful
1154 * selections occur (e.g. no devices on the bus).
1156 ahc_outb(ahc
, CLRSINT0
, CLRSELINGO
);
1158 scbptr
= ahc_inb(ahc
, WAITING_SCBH
);
1159 ahc_outb(ahc
, SCBPTR
, scbptr
);
1160 scb_index
= ahc_inb(ahc
, SCB_TAG
);
1162 scb
= ahc_lookup_scb(ahc
, scb_index
);
1164 printf("%s: ahc_intr - referenced scb not "
1165 "valid during SELTO scb(%d, %d)\n",
1166 ahc_name(ahc
), scbptr
, scb_index
);
1167 ahc_dump_card_state(ahc
);
1169 struct ahc_devinfo devinfo
;
1171 if ((ahc_debug
& AHC_SHOW_SELTO
) != 0) {
1172 ahc_print_path(ahc
, scb
);
1173 printf("Saw Selection Timeout for SCB 0x%x\n",
1178 * Force a renegotiation with this target just in
1179 * case the cable was pulled and will later be
1180 * re-attached. The target may forget its negotiation
1181 * settings with us should it attempt to reselect
1182 * during the interruption. The target will not issue
1183 * a unit attention in this case, so we must always
1186 ahc_scb_devinfo(ahc
, &devinfo
, scb
);
1187 ahc_force_renegotiation(ahc
, &devinfo
);
1188 ahc_set_transaction_status(scb
, CAM_SEL_TIMEOUT
);
1189 ahc_freeze_devq(ahc
, scb
);
1191 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1193 } else if ((status
& BUSFREE
) != 0
1194 && (ahc_inb(ahc
, SIMODE1
) & ENBUSFREE
) != 0) {
1195 struct ahc_devinfo devinfo
;
1200 u_int initiator_role_id
;
1205 * Clear our selection hardware as soon as possible.
1206 * We may have an entry in the waiting Q for this target,
1207 * that is affected by this busfree and we don't want to
1208 * go about selecting the target while we handle the event.
1210 ahc_outb(ahc
, SCSISEQ
,
1211 ahc_inb(ahc
, SCSISEQ
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
1214 * Disable busfree interrupts and clear the busfree
1215 * interrupt status. We do this here so that several
1216 * bus transactions occur prior to clearing the SCSIINT
1217 * latch. It can take a bit for the clearing to take effect.
1219 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENBUSFREE
);
1220 ahc_outb(ahc
, CLRSINT1
, CLRBUSFREE
|CLRSCSIPERR
);
1223 * Look at what phase we were last in.
1224 * If its message out, chances are pretty good
1225 * that the busfree was in response to one of
1226 * our abort requests.
1228 lastphase
= ahc_inb(ahc
, LASTPHASE
);
1229 saved_scsiid
= ahc_inb(ahc
, SAVED_SCSIID
);
1230 saved_lun
= ahc_inb(ahc
, SAVED_LUN
);
1231 target
= SCSIID_TARGET(ahc
, saved_scsiid
);
1232 initiator_role_id
= SCSIID_OUR_ID(saved_scsiid
);
1233 channel
= SCSIID_CHANNEL(ahc
, saved_scsiid
);
1234 ahc_compile_devinfo(&devinfo
, initiator_role_id
,
1235 target
, saved_lun
, channel
, ROLE_INITIATOR
);
1238 if (lastphase
== P_MESGOUT
) {
1241 tag
= SCB_LIST_NULL
;
1242 if (ahc_sent_msg(ahc
, AHCMSG_1B
, MSG_ABORT_TAG
, TRUE
)
1243 || ahc_sent_msg(ahc
, AHCMSG_1B
, MSG_ABORT
, TRUE
)) {
1244 if (ahc
->msgout_buf
[ahc
->msgout_index
- 1]
1246 tag
= scb
->hscb
->tag
;
1247 ahc_print_path(ahc
, scb
);
1248 printf("SCB %d - Abort%s Completed.\n",
1249 scb
->hscb
->tag
, tag
== SCB_LIST_NULL
?
1251 ahc_abort_scbs(ahc
, target
, channel
,
1256 } else if (ahc_sent_msg(ahc
, AHCMSG_1B
,
1257 MSG_BUS_DEV_RESET
, TRUE
)) {
1260 * Don't mark the user's request for this BDR
1261 * as completing with CAM_BDR_SENT. CAM3
1262 * specifies CAM_REQ_CMP.
1265 && scb
->io_ctx
->ccb_h
.func_code
== XPT_RESET_DEV
1266 && ahc_match_scb(ahc
, scb
, target
, channel
,
1270 ahc_set_transaction_status(scb
, CAM_REQ_CMP
);
1273 ahc_compile_devinfo(&devinfo
,
1279 ahc_handle_devreset(ahc
, &devinfo
,
1282 /*verbose_level*/0);
1284 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1285 MSG_EXT_PPR
, FALSE
)) {
1286 struct ahc_initiator_tinfo
*tinfo
;
1287 struct ahc_tmode_tstate
*tstate
;
1290 * PPR Rejected. Try non-ppr negotiation
1291 * and retry command.
1293 tinfo
= ahc_fetch_transinfo(ahc
,
1298 tinfo
->curr
.transport_version
= 2;
1299 tinfo
->goal
.transport_version
= 2;
1300 tinfo
->goal
.ppr_options
= 0;
1301 ahc_qinfifo_requeue_tail(ahc
, scb
);
1303 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1304 MSG_EXT_WDTR
, FALSE
)) {
1306 * Negotiation Rejected. Go-narrow and
1309 ahc_set_width(ahc
, &devinfo
,
1310 MSG_EXT_WDTR_BUS_8_BIT
,
1311 AHC_TRANS_CUR
|AHC_TRANS_GOAL
,
1313 ahc_qinfifo_requeue_tail(ahc
, scb
);
1315 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1316 MSG_EXT_SDTR
, FALSE
)) {
1318 * Negotiation Rejected. Go-async and
1321 ahc_set_syncrate(ahc
, &devinfo
,
1323 /*period*/0, /*offset*/0,
1325 AHC_TRANS_CUR
|AHC_TRANS_GOAL
,
1327 ahc_qinfifo_requeue_tail(ahc
, scb
);
1331 if (printerror
!= 0) {
1337 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
1338 tag
= scb
->hscb
->tag
;
1340 tag
= SCB_LIST_NULL
;
1341 ahc_print_path(ahc
, scb
);
1342 ahc_abort_scbs(ahc
, target
, channel
,
1343 SCB_GET_LUN(scb
), tag
,
1348 * We had not fully identified this connection,
1349 * so we cannot abort anything.
1351 printf("%s: ", ahc_name(ahc
));
1353 for (i
= 0; i
< num_phases
; i
++) {
1354 if (lastphase
== ahc_phase_table
[i
].phase
)
1357 if (lastphase
!= P_BUSFREE
) {
1359 * Renegotiate with this device at the
1360 * next oportunity just in case this busfree
1361 * is due to a negotiation mismatch with the
1364 ahc_force_renegotiation(ahc
, &devinfo
);
1366 printf("Unexpected busfree %s\n"
1367 "SEQADDR == 0x%x\n",
1368 ahc_phase_table
[i
].phasemsg
,
1369 ahc_inb(ahc
, SEQADDR0
)
1370 | (ahc_inb(ahc
, SEQADDR1
) << 8));
1372 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1375 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1376 ahc_name(ahc
), status
);
1377 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1382 * Force renegotiation to occur the next time we initiate
1383 * a command to the current device.
1386 ahc_force_renegotiation(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
1388 struct ahc_initiator_tinfo
*targ_info
;
1389 struct ahc_tmode_tstate
*tstate
;
1391 targ_info
= ahc_fetch_transinfo(ahc
,
1393 devinfo
->our_scsiid
,
1396 ahc_update_neg_request(ahc
, devinfo
, tstate
,
1397 targ_info
, AHC_NEG_IF_NON_ASYNC
);
1400 #define AHC_MAX_STEPS 2000
1402 ahc_clear_critical_section(struct ahc_softc
*ahc
)
1409 if (ahc
->num_critical_sections
== 0)
1421 seqaddr
= ahc_inb(ahc
, SEQADDR0
)
1422 | (ahc_inb(ahc
, SEQADDR1
) << 8);
1425 * Seqaddr represents the next instruction to execute,
1426 * so we are really executing the instruction just
1431 cs
= ahc
->critical_sections
;
1432 for (i
= 0; i
< ahc
->num_critical_sections
; i
++, cs
++) {
1434 if (cs
->begin
< seqaddr
&& cs
->end
>= seqaddr
)
1438 if (i
== ahc
->num_critical_sections
)
1441 if (steps
> AHC_MAX_STEPS
) {
1442 printf("%s: Infinite loop in critical section\n",
1444 ahc_dump_card_state(ahc
);
1445 panic("critical section loop");
1449 if (stepping
== FALSE
) {
1452 * Disable all interrupt sources so that the
1453 * sequencer will not be stuck by a pausing
1454 * interrupt condition while we attempt to
1455 * leave a critical section.
1457 simode0
= ahc_inb(ahc
, SIMODE0
);
1458 ahc_outb(ahc
, SIMODE0
, 0);
1459 simode1
= ahc_inb(ahc
, SIMODE1
);
1460 if ((ahc
->features
& AHC_DT
) != 0)
1462 * On DT class controllers, we
1463 * use the enhanced busfree logic.
1464 * Unfortunately we cannot re-enable
1465 * busfree detection within the
1466 * current connection, so we must
1467 * leave it on while single stepping.
1469 ahc_outb(ahc
, SIMODE1
, simode1
& ENBUSFREE
);
1471 ahc_outb(ahc
, SIMODE1
, 0);
1472 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1473 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
| STEP
);
1476 if ((ahc
->features
& AHC_DT
) != 0) {
1477 ahc_outb(ahc
, CLRSINT1
, CLRBUSFREE
);
1478 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1480 ahc_outb(ahc
, HCNTRL
, ahc
->unpause
);
1481 while (!ahc_is_paused(ahc
))
1485 ahc_outb(ahc
, SIMODE0
, simode0
);
1486 ahc_outb(ahc
, SIMODE1
, simode1
);
1487 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
);
1492 * Clear any pending interrupt status.
1495 ahc_clear_intstat(struct ahc_softc
*ahc
)
1497 /* Clear any interrupt conditions this may have caused */
1498 ahc_outb(ahc
, CLRSINT1
, CLRSELTIMEO
|CLRATNO
|CLRSCSIRSTI
1499 |CLRBUSFREE
|CLRSCSIPERR
|CLRPHASECHG
|
1501 ahc_flush_device_writes(ahc
);
1502 ahc_outb(ahc
, CLRSINT0
, CLRSELDO
|CLRSELDI
|CLRSELINGO
);
1503 ahc_flush_device_writes(ahc
);
1504 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1505 ahc_flush_device_writes(ahc
);
1508 /**************************** Debugging Routines ******************************/
1510 uint32_t ahc_debug
= AHC_DEBUG_OPTS
;
1514 ahc_print_scb(struct scb
*scb
)
1518 struct hardware_scb
*hscb
= scb
->hscb
;
1520 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1526 printf("Shared Data: ");
1527 for (i
= 0; i
< sizeof(hscb
->shared_data
.cdb
); i
++)
1528 printf("%#02x", hscb
->shared_data
.cdb
[i
]);
1529 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1530 ahc_le32toh(hscb
->dataptr
),
1531 ahc_le32toh(hscb
->datacnt
),
1532 ahc_le32toh(hscb
->sgptr
),
1534 if (scb
->sg_count
> 0) {
1535 for (i
= 0; i
< scb
->sg_count
; i
++) {
1536 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1538 (ahc_le32toh(scb
->sg_list
[i
].len
) >> 24
1539 & SG_HIGH_ADDR_BITS
),
1540 ahc_le32toh(scb
->sg_list
[i
].addr
),
1541 ahc_le32toh(scb
->sg_list
[i
].len
));
1546 /************************* Transfer Negotiation *******************************/
1548 * Allocate per target mode instance (ID we respond to as a target)
1549 * transfer negotiation data structures.
1551 static struct ahc_tmode_tstate
*
1552 ahc_alloc_tstate(struct ahc_softc
*ahc
, u_int scsi_id
, char channel
)
1554 struct ahc_tmode_tstate
*master_tstate
;
1555 struct ahc_tmode_tstate
*tstate
;
1558 master_tstate
= ahc
->enabled_targets
[ahc
->our_id
];
1559 if (channel
== 'B') {
1561 master_tstate
= ahc
->enabled_targets
[ahc
->our_id_b
+ 8];
1563 if (ahc
->enabled_targets
[scsi_id
] != NULL
1564 && ahc
->enabled_targets
[scsi_id
] != master_tstate
)
1565 panic("%s: ahc_alloc_tstate - Target already allocated",
1567 tstate
= (struct ahc_tmode_tstate
*)malloc(sizeof(*tstate
),
1568 M_DEVBUF
, M_NOWAIT
);
1573 * If we have allocated a master tstate, copy user settings from
1574 * the master tstate (taken from SRAM or the EEPROM) for this
1575 * channel, but reset our current and goal settings to async/narrow
1576 * until an initiator talks to us.
1578 if (master_tstate
!= NULL
) {
1579 memcpy(tstate
, master_tstate
, sizeof(*tstate
));
1580 memset(tstate
->enabled_luns
, 0, sizeof(tstate
->enabled_luns
));
1581 tstate
->ultraenb
= 0;
1582 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++) {
1583 memset(&tstate
->transinfo
[i
].curr
, 0,
1584 sizeof(tstate
->transinfo
[i
].curr
));
1585 memset(&tstate
->transinfo
[i
].goal
, 0,
1586 sizeof(tstate
->transinfo
[i
].goal
));
1589 memset(tstate
, 0, sizeof(*tstate
));
1590 ahc
->enabled_targets
[scsi_id
] = tstate
;
1594 #ifdef AHC_TARGET_MODE
1596 * Free per target mode instance (ID we respond to as a target)
1597 * transfer negotiation data structures.
1600 ahc_free_tstate(struct ahc_softc
*ahc
, u_int scsi_id
, char channel
, int force
)
1602 struct ahc_tmode_tstate
*tstate
;
1605 * Don't clean up our "master" tstate.
1606 * It has our default user settings.
1608 if (((channel
== 'B' && scsi_id
== ahc
->our_id_b
)
1609 || (channel
== 'A' && scsi_id
== ahc
->our_id
))
1615 tstate
= ahc
->enabled_targets
[scsi_id
];
1617 free(tstate
, M_DEVBUF
);
1618 ahc
->enabled_targets
[scsi_id
] = NULL
;
1623 * Called when we have an active connection to a target on the bus,
1624 * this function finds the nearest syncrate to the input period limited
1625 * by the capabilities of the bus connectivity of and sync settings for
1628 struct ahc_syncrate
*
1629 ahc_devlimited_syncrate(struct ahc_softc
*ahc
,
1630 struct ahc_initiator_tinfo
*tinfo
,
1631 u_int
*period
, u_int
*ppr_options
, role_t role
)
1633 struct ahc_transinfo
*transinfo
;
1636 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1637 if ((ahc_inb(ahc
, SBLKCTL
) & ENAB40
) != 0
1638 && (ahc_inb(ahc
, SSTAT2
) & EXP_ACTIVE
) == 0) {
1639 maxsync
= AHC_SYNCRATE_DT
;
1641 maxsync
= AHC_SYNCRATE_ULTRA
;
1642 /* Can't do DT on an SE bus */
1643 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1645 } else if ((ahc
->features
& AHC_ULTRA
) != 0) {
1646 maxsync
= AHC_SYNCRATE_ULTRA
;
1648 maxsync
= AHC_SYNCRATE_FAST
;
1651 * Never allow a value higher than our current goal
1652 * period otherwise we may allow a target initiated
1653 * negotiation to go above the limit as set by the
1654 * user. In the case of an initiator initiated
1655 * sync negotiation, we limit based on the user
1656 * setting. This allows the system to still accept
1657 * incoming negotiations even if target initiated
1658 * negotiation is not performed.
1660 if (role
== ROLE_TARGET
)
1661 transinfo
= &tinfo
->user
;
1663 transinfo
= &tinfo
->goal
;
1664 *ppr_options
&= transinfo
->ppr_options
;
1665 if (transinfo
->width
== MSG_EXT_WDTR_BUS_8_BIT
) {
1666 maxsync
= MAX(maxsync
, AHC_SYNCRATE_ULTRA2
);
1667 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1669 if (transinfo
->period
== 0) {
1674 *period
= MAX(*period
, transinfo
->period
);
1675 return (ahc_find_syncrate(ahc
, period
, ppr_options
, maxsync
));
1679 * Look up the valid period to SCSIRATE conversion in our table.
1680 * Return the period and offset that should be sent to the target
1681 * if this was the beginning of an SDTR.
1683 struct ahc_syncrate
*
1684 ahc_find_syncrate(struct ahc_softc
*ahc
, u_int
*period
,
1685 u_int
*ppr_options
, u_int maxsync
)
1687 struct ahc_syncrate
*syncrate
;
1689 if ((ahc
->features
& AHC_DT
) == 0)
1690 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1692 /* Skip all DT only entries if DT is not available */
1693 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
1694 && maxsync
< AHC_SYNCRATE_ULTRA2
)
1695 maxsync
= AHC_SYNCRATE_ULTRA2
;
1697 for (syncrate
= &ahc_syncrates
[maxsync
];
1698 syncrate
->rate
!= NULL
;
1702 * The Ultra2 table doesn't go as low
1703 * as for the Fast/Ultra cards.
1705 if ((ahc
->features
& AHC_ULTRA2
) != 0
1706 && (syncrate
->sxfr_u2
== 0))
1709 if (*period
<= syncrate
->period
) {
1711 * When responding to a target that requests
1712 * sync, the requested rate may fall between
1713 * two rates that we can output, but still be
1714 * a rate that we can receive. Because of this,
1715 * we want to respond to the target with
1716 * the same rate that it sent to us even
1717 * if the period we use to send data to it
1718 * is lower. Only lower the response period
1721 if (syncrate
== &ahc_syncrates
[maxsync
])
1722 *period
= syncrate
->period
;
1725 * At some speeds, we only support
1728 if ((syncrate
->sxfr_u2
& ST_SXFR
) != 0)
1729 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1735 || (syncrate
->rate
== NULL
)
1736 || ((ahc
->features
& AHC_ULTRA2
) != 0
1737 && (syncrate
->sxfr_u2
== 0))) {
1738 /* Use asynchronous transfers. */
1741 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1747 * Convert from an entry in our syncrate table to the SCSI equivalent
1748 * sync "period" factor.
1751 ahc_find_period(struct ahc_softc
*ahc
, u_int scsirate
, u_int maxsync
)
1753 struct ahc_syncrate
*syncrate
;
1755 if ((ahc
->features
& AHC_ULTRA2
) != 0)
1756 scsirate
&= SXFR_ULTRA2
;
1760 syncrate
= &ahc_syncrates
[maxsync
];
1761 while (syncrate
->rate
!= NULL
) {
1763 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1764 if (syncrate
->sxfr_u2
== 0)
1766 else if (scsirate
== (syncrate
->sxfr_u2
& SXFR_ULTRA2
))
1767 return (syncrate
->period
);
1768 } else if (scsirate
== (syncrate
->sxfr
& SXFR
)) {
1769 return (syncrate
->period
);
1773 return (0); /* async */
1777 * Truncate the given synchronous offset to a value the
1778 * current adapter type and syncrate are capable of.
1781 ahc_validate_offset(struct ahc_softc
*ahc
,
1782 struct ahc_initiator_tinfo
*tinfo
,
1783 struct ahc_syncrate
*syncrate
,
1784 u_int
*offset
, int wide
, role_t role
)
1788 /* Limit offset to what we can do */
1789 if (syncrate
== NULL
) {
1791 } else if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1792 maxoffset
= MAX_OFFSET_ULTRA2
;
1795 maxoffset
= MAX_OFFSET_16BIT
;
1797 maxoffset
= MAX_OFFSET_8BIT
;
1799 *offset
= MIN(*offset
, maxoffset
);
1800 if (tinfo
!= NULL
) {
1801 if (role
== ROLE_TARGET
)
1802 *offset
= MIN(*offset
, tinfo
->user
.offset
);
1804 *offset
= MIN(*offset
, tinfo
->goal
.offset
);
1809 * Truncate the given transfer width parameter to a value the
1810 * current adapter type is capable of.
1813 ahc_validate_width(struct ahc_softc
*ahc
, struct ahc_initiator_tinfo
*tinfo
,
1814 u_int
*bus_width
, role_t role
)
1816 switch (*bus_width
) {
1818 if (ahc
->features
& AHC_WIDE
) {
1820 *bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
1824 case MSG_EXT_WDTR_BUS_8_BIT
:
1825 *bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
1828 if (tinfo
!= NULL
) {
1829 if (role
== ROLE_TARGET
)
1830 *bus_width
= MIN(tinfo
->user
.width
, *bus_width
);
1832 *bus_width
= MIN(tinfo
->goal
.width
, *bus_width
);
1837 * Update the bitmask of targets for which the controller should
1838 * negotiate with at the next convenient oportunity. This currently
1839 * means the next time we send the initial identify messages for
1840 * a new transaction.
1843 ahc_update_neg_request(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
1844 struct ahc_tmode_tstate
*tstate
,
1845 struct ahc_initiator_tinfo
*tinfo
, ahc_neg_type neg_type
)
1847 u_int auto_negotiate_orig
;
1849 auto_negotiate_orig
= tstate
->auto_negotiate
;
1850 if (neg_type
== AHC_NEG_ALWAYS
) {
1852 * Force our "current" settings to be
1853 * unknown so that unless a bus reset
1854 * occurs the need to renegotiate is
1855 * recorded persistently.
1857 if ((ahc
->features
& AHC_WIDE
) != 0)
1858 tinfo
->curr
.width
= AHC_WIDTH_UNKNOWN
;
1859 tinfo
->curr
.period
= AHC_PERIOD_UNKNOWN
;
1860 tinfo
->curr
.offset
= AHC_OFFSET_UNKNOWN
;
1862 if (tinfo
->curr
.period
!= tinfo
->goal
.period
1863 || tinfo
->curr
.width
!= tinfo
->goal
.width
1864 || tinfo
->curr
.offset
!= tinfo
->goal
.offset
1865 || tinfo
->curr
.ppr_options
!= tinfo
->goal
.ppr_options
1866 || (neg_type
== AHC_NEG_IF_NON_ASYNC
1867 && (tinfo
->goal
.offset
!= 0
1868 || tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
1869 || tinfo
->goal
.ppr_options
!= 0)))
1870 tstate
->auto_negotiate
|= devinfo
->target_mask
;
1872 tstate
->auto_negotiate
&= ~devinfo
->target_mask
;
1874 return (auto_negotiate_orig
!= tstate
->auto_negotiate
);
1878 * Update the user/goal/curr tables of synchronous negotiation
1879 * parameters as well as, in the case of a current or active update,
1880 * any data structures on the host controller. In the case of an
1881 * active update, the specified target is currently talking to us on
1882 * the bus, so the transfer parameter update must take effect
1886 ahc_set_syncrate(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
1887 struct ahc_syncrate
*syncrate
, u_int period
,
1888 u_int offset
, u_int ppr_options
, u_int type
, int paused
)
1890 struct ahc_initiator_tinfo
*tinfo
;
1891 struct ahc_tmode_tstate
*tstate
;
1898 active
= (type
& AHC_TRANS_ACTIVE
) == AHC_TRANS_ACTIVE
;
1901 if (syncrate
== NULL
) {
1906 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
1907 devinfo
->target
, &tstate
);
1909 if ((type
& AHC_TRANS_USER
) != 0) {
1910 tinfo
->user
.period
= period
;
1911 tinfo
->user
.offset
= offset
;
1912 tinfo
->user
.ppr_options
= ppr_options
;
1915 if ((type
& AHC_TRANS_GOAL
) != 0) {
1916 tinfo
->goal
.period
= period
;
1917 tinfo
->goal
.offset
= offset
;
1918 tinfo
->goal
.ppr_options
= ppr_options
;
1921 old_period
= tinfo
->curr
.period
;
1922 old_offset
= tinfo
->curr
.offset
;
1923 old_ppr
= tinfo
->curr
.ppr_options
;
1925 if ((type
& AHC_TRANS_CUR
) != 0
1926 && (old_period
!= period
1927 || old_offset
!= offset
1928 || old_ppr
!= ppr_options
)) {
1932 scsirate
= tinfo
->scsirate
;
1933 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1935 scsirate
&= ~(SXFR_ULTRA2
|SINGLE_EDGE
|ENABLE_CRC
);
1936 if (syncrate
!= NULL
) {
1937 scsirate
|= syncrate
->sxfr_u2
;
1938 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0)
1939 scsirate
|= ENABLE_CRC
;
1941 scsirate
|= SINGLE_EDGE
;
1945 scsirate
&= ~(SXFR
|SOFS
);
1947 * Ensure Ultra mode is set properly for
1950 tstate
->ultraenb
&= ~devinfo
->target_mask
;
1951 if (syncrate
!= NULL
) {
1952 if (syncrate
->sxfr
& ULTRA_SXFR
) {
1954 devinfo
->target_mask
;
1956 scsirate
|= syncrate
->sxfr
& SXFR
;
1957 scsirate
|= offset
& SOFS
;
1962 sxfrctl0
= ahc_inb(ahc
, SXFRCTL0
);
1963 sxfrctl0
&= ~FAST20
;
1964 if (tstate
->ultraenb
& devinfo
->target_mask
)
1966 ahc_outb(ahc
, SXFRCTL0
, sxfrctl0
);
1970 ahc_outb(ahc
, SCSIRATE
, scsirate
);
1971 if ((ahc
->features
& AHC_ULTRA2
) != 0)
1972 ahc_outb(ahc
, SCSIOFFSET
, offset
);
1975 tinfo
->scsirate
= scsirate
;
1976 tinfo
->curr
.period
= period
;
1977 tinfo
->curr
.offset
= offset
;
1978 tinfo
->curr
.ppr_options
= ppr_options
;
1980 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
1981 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
1984 printf("%s: target %d synchronous at %sMHz%s, "
1985 "offset = 0x%x\n", ahc_name(ahc
),
1986 devinfo
->target
, syncrate
->rate
,
1987 (ppr_options
& MSG_EXT_PPR_DT_REQ
)
1988 ? " DT" : "", offset
);
1990 printf("%s: target %d using "
1991 "asynchronous transfers\n",
1992 ahc_name(ahc
), devinfo
->target
);
1997 update_needed
+= ahc_update_neg_request(ahc
, devinfo
, tstate
,
1998 tinfo
, AHC_NEG_TO_GOAL
);
2001 ahc_update_pending_scbs(ahc
);
2005 * Update the user/goal/curr tables of wide negotiation
2006 * parameters as well as, in the case of a current or active update,
2007 * any data structures on the host controller. In the case of an
2008 * active update, the specified target is currently talking to us on
2009 * the bus, so the transfer parameter update must take effect
2013 ahc_set_width(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2014 u_int width
, u_int type
, int paused
)
2016 struct ahc_initiator_tinfo
*tinfo
;
2017 struct ahc_tmode_tstate
*tstate
;
2022 active
= (type
& AHC_TRANS_ACTIVE
) == AHC_TRANS_ACTIVE
;
2024 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
2025 devinfo
->target
, &tstate
);
2027 if ((type
& AHC_TRANS_USER
) != 0)
2028 tinfo
->user
.width
= width
;
2030 if ((type
& AHC_TRANS_GOAL
) != 0)
2031 tinfo
->goal
.width
= width
;
2033 oldwidth
= tinfo
->curr
.width
;
2034 if ((type
& AHC_TRANS_CUR
) != 0 && oldwidth
!= width
) {
2038 scsirate
= tinfo
->scsirate
;
2039 scsirate
&= ~WIDEXFER
;
2040 if (width
== MSG_EXT_WDTR_BUS_16_BIT
)
2041 scsirate
|= WIDEXFER
;
2043 tinfo
->scsirate
= scsirate
;
2046 ahc_outb(ahc
, SCSIRATE
, scsirate
);
2048 tinfo
->curr
.width
= width
;
2050 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
2051 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
2053 printf("%s: target %d using %dbit transfers\n",
2054 ahc_name(ahc
), devinfo
->target
,
2055 8 * (0x01 << width
));
2059 update_needed
+= ahc_update_neg_request(ahc
, devinfo
, tstate
,
2060 tinfo
, AHC_NEG_TO_GOAL
);
2062 ahc_update_pending_scbs(ahc
);
2066 * Update the current state of tagged queuing for a given target.
2069 ahc_set_tags(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2072 ahc_platform_set_tags(ahc
, devinfo
, alg
);
2073 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
2074 devinfo
->lun
, AC_TRANSFER_NEG
, &alg
);
2078 * When the transfer settings for a connection change, update any
2079 * in-transit SCBs to contain the new data so the hardware will
2080 * be set correctly during future (re)selections.
2083 ahc_update_pending_scbs(struct ahc_softc
*ahc
)
2085 struct scb
*pending_scb
;
2086 int pending_scb_count
;
2092 * Traverse the pending SCB list and ensure that all of the
2093 * SCBs there have the proper settings.
2095 pending_scb_count
= 0;
2096 LIST_FOREACH(pending_scb
, &ahc
->pending_scbs
, pending_links
) {
2097 struct ahc_devinfo devinfo
;
2098 struct hardware_scb
*pending_hscb
;
2099 struct ahc_initiator_tinfo
*tinfo
;
2100 struct ahc_tmode_tstate
*tstate
;
2102 ahc_scb_devinfo(ahc
, &devinfo
, pending_scb
);
2103 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
.channel
,
2105 devinfo
.target
, &tstate
);
2106 pending_hscb
= pending_scb
->hscb
;
2107 pending_hscb
->control
&= ~ULTRAENB
;
2108 if ((tstate
->ultraenb
& devinfo
.target_mask
) != 0)
2109 pending_hscb
->control
|= ULTRAENB
;
2110 pending_hscb
->scsirate
= tinfo
->scsirate
;
2111 pending_hscb
->scsioffset
= tinfo
->curr
.offset
;
2112 if ((tstate
->auto_negotiate
& devinfo
.target_mask
) == 0
2113 && (pending_scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0) {
2114 pending_scb
->flags
&= ~SCB_AUTO_NEGOTIATE
;
2115 pending_hscb
->control
&= ~MK_MESSAGE
;
2117 ahc_sync_scb(ahc
, pending_scb
,
2118 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
2119 pending_scb_count
++;
2122 if (pending_scb_count
== 0)
2125 if (ahc_is_paused(ahc
)) {
2132 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
2133 /* Ensure that the hscbs down on the card match the new information */
2134 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
2135 struct hardware_scb
*pending_hscb
;
2139 ahc_outb(ahc
, SCBPTR
, i
);
2140 scb_tag
= ahc_inb(ahc
, SCB_TAG
);
2141 pending_scb
= ahc_lookup_scb(ahc
, scb_tag
);
2142 if (pending_scb
== NULL
)
2145 pending_hscb
= pending_scb
->hscb
;
2146 control
= ahc_inb(ahc
, SCB_CONTROL
);
2147 control
&= ~(ULTRAENB
|MK_MESSAGE
);
2148 control
|= pending_hscb
->control
& (ULTRAENB
|MK_MESSAGE
);
2149 ahc_outb(ahc
, SCB_CONTROL
, control
);
2150 ahc_outb(ahc
, SCB_SCSIRATE
, pending_hscb
->scsirate
);
2151 ahc_outb(ahc
, SCB_SCSIOFFSET
, pending_hscb
->scsioffset
);
2153 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
2159 /**************************** Pathing Information *****************************/
2161 ahc_fetch_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2167 if (ahc_inb(ahc
, SSTAT0
) & TARGET
)
2170 role
= ROLE_INITIATOR
;
2172 if (role
== ROLE_TARGET
2173 && (ahc
->features
& AHC_MULTI_TID
) != 0
2174 && (ahc_inb(ahc
, SEQ_FLAGS
)
2175 & (CMDPHASE_PENDING
|TARG_CMD_PENDING
|NO_DISCONNECT
)) != 0) {
2176 /* We were selected, so pull our id from TARGIDIN */
2177 our_id
= ahc_inb(ahc
, TARGIDIN
) & OID
;
2178 } else if ((ahc
->features
& AHC_ULTRA2
) != 0)
2179 our_id
= ahc_inb(ahc
, SCSIID_ULTRA2
) & OID
;
2181 our_id
= ahc_inb(ahc
, SCSIID
) & OID
;
2183 saved_scsiid
= ahc_inb(ahc
, SAVED_SCSIID
);
2184 ahc_compile_devinfo(devinfo
,
2186 SCSIID_TARGET(ahc
, saved_scsiid
),
2187 ahc_inb(ahc
, SAVED_LUN
),
2188 SCSIID_CHANNEL(ahc
, saved_scsiid
),
2192 struct ahc_phase_table_entry
*
2193 ahc_lookup_phase_entry(int phase
)
2195 struct ahc_phase_table_entry
*entry
;
2196 struct ahc_phase_table_entry
*last_entry
;
2199 * num_phases doesn't include the default entry which
2200 * will be returned if the phase doesn't match.
2202 last_entry
= &ahc_phase_table
[num_phases
];
2203 for (entry
= ahc_phase_table
; entry
< last_entry
; entry
++) {
2204 if (phase
== entry
->phase
)
2211 ahc_compile_devinfo(struct ahc_devinfo
*devinfo
, u_int our_id
, u_int target
,
2212 u_int lun
, char channel
, role_t role
)
2214 devinfo
->our_scsiid
= our_id
;
2215 devinfo
->target
= target
;
2217 devinfo
->target_offset
= target
;
2218 devinfo
->channel
= channel
;
2219 devinfo
->role
= role
;
2221 devinfo
->target_offset
+= 8;
2222 devinfo
->target_mask
= (0x01 << devinfo
->target_offset
);
2226 ahc_print_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2228 printf("%s:%c:%d:%d: ", ahc_name(ahc
), devinfo
->channel
,
2229 devinfo
->target
, devinfo
->lun
);
2233 ahc_scb_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2239 our_id
= SCSIID_OUR_ID(scb
->hscb
->scsiid
);
2240 role
= ROLE_INITIATOR
;
2241 if ((scb
->flags
& SCB_TARGET_SCB
) != 0)
2243 ahc_compile_devinfo(devinfo
, our_id
, SCB_GET_TARGET(ahc
, scb
),
2244 SCB_GET_LUN(scb
), SCB_GET_CHANNEL(ahc
, scb
), role
);
2248 /************************ Message Phase Processing ****************************/
2250 ahc_assert_atn(struct ahc_softc
*ahc
)
2255 if ((ahc
->features
& AHC_DT
) == 0)
2256 scsisigo
|= ahc_inb(ahc
, SCSISIGI
);
2257 ahc_outb(ahc
, SCSISIGO
, scsisigo
);
2261 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2262 * or enters the initial message out phase, we are interrupted. Fill our
2263 * outgoing message buffer with the appropriate message and beging handing
2264 * the message phase(s) manually.
2267 ahc_setup_initiator_msgout(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2271 * To facilitate adding multiple messages together,
2272 * each routine should increment the index and len
2273 * variables instead of setting them explicitly.
2275 ahc
->msgout_index
= 0;
2276 ahc
->msgout_len
= 0;
2278 if ((scb
->flags
& SCB_DEVICE_RESET
) == 0
2279 && ahc_inb(ahc
, MSG_OUT
) == MSG_IDENTIFYFLAG
) {
2282 identify_msg
= MSG_IDENTIFYFLAG
| SCB_GET_LUN(scb
);
2283 if ((scb
->hscb
->control
& DISCENB
) != 0)
2284 identify_msg
|= MSG_IDENTIFY_DISCFLAG
;
2285 ahc
->msgout_buf
[ahc
->msgout_index
++] = identify_msg
;
2288 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
2289 ahc
->msgout_buf
[ahc
->msgout_index
++] =
2290 scb
->hscb
->control
& (TAG_ENB
|SCB_TAG_TYPE
);
2291 ahc
->msgout_buf
[ahc
->msgout_index
++] = scb
->hscb
->tag
;
2292 ahc
->msgout_len
+= 2;
2296 if (scb
->flags
& SCB_DEVICE_RESET
) {
2297 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_BUS_DEV_RESET
;
2299 ahc_print_path(ahc
, scb
);
2300 printf("Bus Device Reset Message Sent\n");
2302 * Clear our selection hardware in advance of
2303 * the busfree. We may have an entry in the waiting
2304 * Q for this target, and we don't want to go about
2305 * selecting while we handle the busfree and blow it
2308 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
2309 } else if ((scb
->flags
& SCB_ABORT
) != 0) {
2310 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
2311 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_ABORT_TAG
;
2313 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_ABORT
;
2315 ahc_print_path(ahc
, scb
);
2316 printf("Abort%s Message Sent\n",
2317 (scb
->hscb
->control
& TAG_ENB
) != 0 ? " Tag" : "");
2319 * Clear our selection hardware in advance of
2320 * the busfree. We may have an entry in the waiting
2321 * Q for this target, and we don't want to go about
2322 * selecting while we handle the busfree and blow it
2325 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
2326 } else if ((scb
->flags
& (SCB_AUTO_NEGOTIATE
|SCB_NEGOTIATE
)) != 0) {
2327 ahc_build_transfer_msg(ahc
, devinfo
);
2329 printf("ahc_intr: AWAITING_MSG for an SCB that "
2330 "does not have a waiting message\n");
2331 printf("SCSIID = %x, target_mask = %x\n", scb
->hscb
->scsiid
,
2332 devinfo
->target_mask
);
2333 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2334 "SCB flags = %x", scb
->hscb
->tag
, scb
->hscb
->control
,
2335 ahc_inb(ahc
, MSG_OUT
), scb
->flags
);
2339 * Clear the MK_MESSAGE flag from the SCB so we aren't
2340 * asked to send this message again.
2342 ahc_outb(ahc
, SCB_CONTROL
, ahc_inb(ahc
, SCB_CONTROL
) & ~MK_MESSAGE
);
2343 scb
->hscb
->control
&= ~MK_MESSAGE
;
2344 ahc
->msgout_index
= 0;
2345 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2349 * Build an appropriate transfer negotiation message for the
2350 * currently active target.
2353 ahc_build_transfer_msg(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2356 * We need to initiate transfer negotiations.
2357 * If our current and goal settings are identical,
2358 * we want to renegotiate due to a check condition.
2360 struct ahc_initiator_tinfo
*tinfo
;
2361 struct ahc_tmode_tstate
*tstate
;
2362 struct ahc_syncrate
*rate
;
2370 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
2371 devinfo
->target
, &tstate
);
2373 * Filter our period based on the current connection.
2374 * If we can't perform DT transfers on this segment (not in LVD
2375 * mode for instance), then our decision to issue a PPR message
2378 period
= tinfo
->goal
.period
;
2379 offset
= tinfo
->goal
.offset
;
2380 ppr_options
= tinfo
->goal
.ppr_options
;
2381 /* Target initiated PPR is not allowed in the SCSI spec */
2382 if (devinfo
->role
== ROLE_TARGET
)
2384 rate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
2385 &ppr_options
, devinfo
->role
);
2386 dowide
= tinfo
->curr
.width
!= tinfo
->goal
.width
;
2387 dosync
= tinfo
->curr
.offset
!= offset
|| tinfo
->curr
.period
!= period
;
2389 * Only use PPR if we have options that need it, even if the device
2390 * claims to support it. There might be an expander in the way
2393 doppr
= ppr_options
!= 0;
2395 if (!dowide
&& !dosync
&& !doppr
) {
2396 dowide
= tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
;
2397 dosync
= tinfo
->goal
.offset
!= 0;
2400 if (!dowide
&& !dosync
&& !doppr
) {
2402 * Force async with a WDTR message if we have a wide bus,
2403 * or just issue an SDTR with a 0 offset.
2405 if ((ahc
->features
& AHC_WIDE
) != 0)
2411 ahc_print_devinfo(ahc
, devinfo
);
2412 printf("Ensuring async\n");
2416 /* Target initiated PPR is not allowed in the SCSI spec */
2417 if (devinfo
->role
== ROLE_TARGET
)
2421 * Both the PPR message and SDTR message require the
2422 * goal syncrate to be limited to what the target device
2423 * is capable of handling (based on whether an LVD->SE
2424 * expander is on the bus), so combine these two cases.
2425 * Regardless, guarantee that if we are using WDTR and SDTR
2426 * messages that WDTR comes first.
2428 if (doppr
|| (dosync
&& !dowide
)) {
2430 offset
= tinfo
->goal
.offset
;
2431 ahc_validate_offset(ahc
, tinfo
, rate
, &offset
,
2432 doppr
? tinfo
->goal
.width
2433 : tinfo
->curr
.width
,
2436 ahc_construct_ppr(ahc
, devinfo
, period
, offset
,
2437 tinfo
->goal
.width
, ppr_options
);
2439 ahc_construct_sdtr(ahc
, devinfo
, period
, offset
);
2442 ahc_construct_wdtr(ahc
, devinfo
, tinfo
->goal
.width
);
2447 * Build a synchronous negotiation message in our message
2448 * buffer based on the input parameters.
2451 ahc_construct_sdtr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2452 u_int period
, u_int offset
)
2455 period
= AHC_ASYNC_XFER_PERIOD
;
2456 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2457 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_SDTR_LEN
;
2458 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_SDTR
;
2459 ahc
->msgout_buf
[ahc
->msgout_index
++] = period
;
2460 ahc
->msgout_buf
[ahc
->msgout_index
++] = offset
;
2461 ahc
->msgout_len
+= 5;
2463 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2464 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
2465 devinfo
->lun
, period
, offset
);
2470 * Build a wide negotiation message in our message
2471 * buffer based on the input parameters.
2474 ahc_construct_wdtr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2477 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2478 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_WDTR_LEN
;
2479 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_WDTR
;
2480 ahc
->msgout_buf
[ahc
->msgout_index
++] = bus_width
;
2481 ahc
->msgout_len
+= 4;
2483 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2484 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
2485 devinfo
->lun
, bus_width
);
2490 * Build a parallel protocol request message in our message
2491 * buffer based on the input parameters.
2494 ahc_construct_ppr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2495 u_int period
, u_int offset
, u_int bus_width
,
2499 period
= AHC_ASYNC_XFER_PERIOD
;
2500 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2501 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_PPR_LEN
;
2502 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_PPR
;
2503 ahc
->msgout_buf
[ahc
->msgout_index
++] = period
;
2504 ahc
->msgout_buf
[ahc
->msgout_index
++] = 0;
2505 ahc
->msgout_buf
[ahc
->msgout_index
++] = offset
;
2506 ahc
->msgout_buf
[ahc
->msgout_index
++] = bus_width
;
2507 ahc
->msgout_buf
[ahc
->msgout_index
++] = ppr_options
;
2508 ahc
->msgout_len
+= 8;
2510 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2511 "offset %x, ppr_options %x\n", ahc_name(ahc
),
2512 devinfo
->channel
, devinfo
->target
, devinfo
->lun
,
2513 bus_width
, period
, offset
, ppr_options
);
2518 * Clear any active message state.
2521 ahc_clear_msg_state(struct ahc_softc
*ahc
)
2523 ahc
->msgout_len
= 0;
2524 ahc
->msgin_index
= 0;
2525 ahc
->msg_type
= MSG_TYPE_NONE
;
2526 if ((ahc_inb(ahc
, SCSISIGI
) & ATNI
) != 0) {
2528 * The target didn't care to respond to our
2529 * message request, so clear ATN.
2531 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2533 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
);
2534 ahc_outb(ahc
, SEQ_FLAGS2
,
2535 ahc_inb(ahc
, SEQ_FLAGS2
) & ~TARGET_MSG_PENDING
);
2539 ahc_handle_proto_violation(struct ahc_softc
*ahc
)
2541 struct ahc_devinfo devinfo
;
2549 ahc_fetch_devinfo(ahc
, &devinfo
);
2550 scbid
= ahc_inb(ahc
, SCB_TAG
);
2551 scb
= ahc_lookup_scb(ahc
, scbid
);
2552 seq_flags
= ahc_inb(ahc
, SEQ_FLAGS
);
2553 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
2554 lastphase
= ahc_inb(ahc
, LASTPHASE
);
2555 if ((seq_flags
& NOT_IDENTIFIED
) != 0) {
2558 * The reconnecting target either did not send an
2559 * identify message, or did, but we didn't find an SCB
2562 ahc_print_devinfo(ahc
, &devinfo
);
2563 printf("Target did not send an IDENTIFY message. "
2564 "LASTPHASE = 0x%x.\n", lastphase
);
2566 } else if (scb
== NULL
) {
2568 * We don't seem to have an SCB active for this
2569 * transaction. Print an error and reset the bus.
2571 ahc_print_devinfo(ahc
, &devinfo
);
2572 printf("No SCB found during protocol violation\n");
2573 goto proto_violation_reset
;
2575 ahc_set_transaction_status(scb
, CAM_SEQUENCE_FAIL
);
2576 if ((seq_flags
& NO_CDB_SENT
) != 0) {
2577 ahc_print_path(ahc
, scb
);
2578 printf("No or incomplete CDB sent to device.\n");
2579 } else if ((ahc_inb(ahc
, SCB_CONTROL
) & STATUS_RCVD
) == 0) {
2581 * The target never bothered to provide status to
2582 * us prior to completing the command. Since we don't
2583 * know the disposition of this command, we must attempt
2584 * to abort it. Assert ATN and prepare to send an abort
2587 ahc_print_path(ahc
, scb
);
2588 printf("Completed command without status.\n");
2590 ahc_print_path(ahc
, scb
);
2591 printf("Unknown protocol violation.\n");
2592 ahc_dump_card_state(ahc
);
2595 if ((lastphase
& ~P_DATAIN_DT
) == 0
2596 || lastphase
== P_COMMAND
) {
2597 proto_violation_reset
:
2599 * Target either went directly to data/command
2600 * phase or didn't respond to our ATN.
2601 * The only safe thing to do is to blow
2602 * it away with a bus reset.
2604 found
= ahc_reset_channel(ahc
, 'A', TRUE
);
2605 printf("%s: Issued Channel %c Bus Reset. "
2606 "%d SCBs aborted\n", ahc_name(ahc
), 'A', found
);
2609 * Leave the selection hardware off in case
2610 * this abort attempt will affect yet to
2613 ahc_outb(ahc
, SCSISEQ
,
2614 ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
);
2615 ahc_assert_atn(ahc
);
2616 ahc_outb(ahc
, MSG_OUT
, HOST_MSG
);
2618 ahc_print_devinfo(ahc
, &devinfo
);
2619 ahc
->msgout_buf
[0] = MSG_ABORT_TASK
;
2620 ahc
->msgout_len
= 1;
2621 ahc
->msgout_index
= 0;
2622 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2624 ahc_print_path(ahc
, scb
);
2625 scb
->flags
|= SCB_ABORT
;
2627 printf("Protocol violation %s. Attempting to abort.\n",
2628 ahc_lookup_phase_entry(curphase
)->phasemsg
);
2633 * Manual message loop handler.
2636 ahc_handle_message_phase(struct ahc_softc
*ahc
)
2638 struct ahc_devinfo devinfo
;
2642 ahc_fetch_devinfo(ahc
, &devinfo
);
2643 end_session
= FALSE
;
2644 bus_phase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
2647 switch (ahc
->msg_type
) {
2648 case MSG_TYPE_INITIATOR_MSGOUT
:
2654 if (ahc
->msgout_len
== 0)
2655 panic("HOST_MSG_LOOP interrupt with no active message");
2658 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2659 ahc_print_devinfo(ahc
, &devinfo
);
2660 printf("INITIATOR_MSG_OUT");
2663 phasemis
= bus_phase
!= P_MESGOUT
;
2666 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2667 printf(" PHASEMIS %s\n",
2668 ahc_lookup_phase_entry(bus_phase
)
2672 if (bus_phase
== P_MESGIN
) {
2674 * Change gears and see if
2675 * this messages is of interest to
2676 * us or should be passed back to
2679 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2680 ahc
->send_msg_perror
= FALSE
;
2681 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGIN
;
2682 ahc
->msgin_index
= 0;
2689 if (ahc
->send_msg_perror
) {
2690 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2691 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2693 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2694 printf(" byte 0x%x\n", ahc
->send_msg_perror
);
2696 ahc_outb(ahc
, SCSIDATL
, MSG_PARITY_ERROR
);
2700 msgdone
= ahc
->msgout_index
== ahc
->msgout_len
;
2703 * The target has requested a retry.
2704 * Re-assert ATN, reset our message index to
2707 ahc
->msgout_index
= 0;
2708 ahc_assert_atn(ahc
);
2711 lastbyte
= ahc
->msgout_index
== (ahc
->msgout_len
- 1);
2713 /* Last byte is signified by dropping ATN */
2714 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2718 * Clear our interrupt status and present
2719 * the next byte on the bus.
2721 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2723 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2724 printf(" byte 0x%x\n",
2725 ahc
->msgout_buf
[ahc
->msgout_index
]);
2727 ahc_outb(ahc
, SCSIDATL
, ahc
->msgout_buf
[ahc
->msgout_index
++]);
2730 case MSG_TYPE_INITIATOR_MSGIN
:
2736 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2737 ahc_print_devinfo(ahc
, &devinfo
);
2738 printf("INITIATOR_MSG_IN");
2741 phasemis
= bus_phase
!= P_MESGIN
;
2744 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2745 printf(" PHASEMIS %s\n",
2746 ahc_lookup_phase_entry(bus_phase
)
2750 ahc
->msgin_index
= 0;
2751 if (bus_phase
== P_MESGOUT
2752 && (ahc
->send_msg_perror
== TRUE
2753 || (ahc
->msgout_len
!= 0
2754 && ahc
->msgout_index
== 0))) {
2755 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2762 /* Pull the byte in without acking it */
2763 ahc
->msgin_buf
[ahc
->msgin_index
] = ahc_inb(ahc
, SCSIBUSL
);
2765 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2766 printf(" byte 0x%x\n",
2767 ahc
->msgin_buf
[ahc
->msgin_index
]);
2770 message_done
= ahc_parse_msg(ahc
, &devinfo
);
2774 * Clear our incoming message buffer in case there
2775 * is another message following this one.
2777 ahc
->msgin_index
= 0;
2780 * If this message illicited a response,
2781 * assert ATN so the target takes us to the
2782 * message out phase.
2784 if (ahc
->msgout_len
!= 0) {
2786 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2787 ahc_print_devinfo(ahc
, &devinfo
);
2788 printf("Asserting ATN for response\n");
2791 ahc_assert_atn(ahc
);
2796 if (message_done
== MSGLOOP_TERMINATED
) {
2800 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2801 ahc_inb(ahc
, SCSIDATL
);
2805 case MSG_TYPE_TARGET_MSGIN
:
2810 if (ahc
->msgout_len
== 0)
2811 panic("Target MSGIN with no active message");
2814 * If we interrupted a mesgout session, the initiator
2815 * will not know this until our first REQ. So, we
2816 * only honor mesgout requests after we've sent our
2819 if ((ahc_inb(ahc
, SCSISIGI
) & ATNI
) != 0
2820 && ahc
->msgout_index
> 0)
2821 msgout_request
= TRUE
;
2823 msgout_request
= FALSE
;
2825 if (msgout_request
) {
2828 * Change gears and see if
2829 * this messages is of interest to
2830 * us or should be passed back to
2833 ahc
->msg_type
= MSG_TYPE_TARGET_MSGOUT
;
2834 ahc_outb(ahc
, SCSISIGO
, P_MESGOUT
| BSYO
);
2835 ahc
->msgin_index
= 0;
2836 /* Dummy read to REQ for first byte */
2837 ahc_inb(ahc
, SCSIDATL
);
2838 ahc_outb(ahc
, SXFRCTL0
,
2839 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2843 msgdone
= ahc
->msgout_index
== ahc
->msgout_len
;
2845 ahc_outb(ahc
, SXFRCTL0
,
2846 ahc_inb(ahc
, SXFRCTL0
) & ~SPIOEN
);
2852 * Present the next byte on the bus.
2854 ahc_outb(ahc
, SXFRCTL0
, ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2855 ahc_outb(ahc
, SCSIDATL
, ahc
->msgout_buf
[ahc
->msgout_index
++]);
2858 case MSG_TYPE_TARGET_MSGOUT
:
2864 * The initiator signals that this is
2865 * the last byte by dropping ATN.
2867 lastbyte
= (ahc_inb(ahc
, SCSISIGI
) & ATNI
) == 0;
2870 * Read the latched byte, but turn off SPIOEN first
2871 * so that we don't inadvertently cause a REQ for the
2874 ahc_outb(ahc
, SXFRCTL0
, ahc_inb(ahc
, SXFRCTL0
) & ~SPIOEN
);
2875 ahc
->msgin_buf
[ahc
->msgin_index
] = ahc_inb(ahc
, SCSIDATL
);
2876 msgdone
= ahc_parse_msg(ahc
, &devinfo
);
2877 if (msgdone
== MSGLOOP_TERMINATED
) {
2879 * The message is *really* done in that it caused
2880 * us to go to bus free. The sequencer has already
2881 * been reset at this point, so pull the ejection
2890 * XXX Read spec about initiator dropping ATN too soon
2891 * and use msgdone to detect it.
2893 if (msgdone
== MSGLOOP_MSGCOMPLETE
) {
2894 ahc
->msgin_index
= 0;
2897 * If this message illicited a response, transition
2898 * to the Message in phase and send it.
2900 if (ahc
->msgout_len
!= 0) {
2901 ahc_outb(ahc
, SCSISIGO
, P_MESGIN
| BSYO
);
2902 ahc_outb(ahc
, SXFRCTL0
,
2903 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2904 ahc
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
2905 ahc
->msgin_index
= 0;
2913 /* Ask for the next byte. */
2914 ahc_outb(ahc
, SXFRCTL0
,
2915 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2921 panic("Unknown REQINIT message type");
2925 ahc_clear_msg_state(ahc
);
2926 ahc_outb(ahc
, RETURN_1
, EXIT_MSG_LOOP
);
2928 ahc_outb(ahc
, RETURN_1
, CONT_MSG_LOOP
);
2932 * See if we sent a particular extended message to the target.
2933 * If "full" is true, return true only if the target saw the full
2934 * message. If "full" is false, return true if the target saw at
2935 * least the first byte of the message.
2938 ahc_sent_msg(struct ahc_softc
*ahc
, ahc_msgtype type
, u_int msgval
, int full
)
2946 while (index
< ahc
->msgout_len
) {
2947 if (ahc
->msgout_buf
[index
] == MSG_EXTENDED
) {
2950 end_index
= index
+ 1 + ahc
->msgout_buf
[index
+ 1];
2951 if (ahc
->msgout_buf
[index
+2] == msgval
2952 && type
== AHCMSG_EXT
) {
2955 if (ahc
->msgout_index
> end_index
)
2957 } else if (ahc
->msgout_index
> index
)
2961 } else if (ahc
->msgout_buf
[index
] >= MSG_SIMPLE_TASK
2962 && ahc
->msgout_buf
[index
] <= MSG_IGN_WIDE_RESIDUE
) {
2964 /* Skip tag type and tag id or residue param*/
2967 /* Single byte message */
2968 if (type
== AHCMSG_1B
2969 && ahc
->msgout_buf
[index
] == msgval
2970 && ahc
->msgout_index
> index
)
2982 * Wait for a complete incoming message, parse it, and respond accordingly.
2985 ahc_parse_msg(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2987 struct ahc_initiator_tinfo
*tinfo
;
2988 struct ahc_tmode_tstate
*tstate
;
2992 u_int targ_scsirate
;
2994 done
= MSGLOOP_IN_PROG
;
2997 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
2998 devinfo
->target
, &tstate
);
2999 targ_scsirate
= tinfo
->scsirate
;
3002 * Parse as much of the message as is available,
3003 * rejecting it if we don't support it. When
3004 * the entire message is available and has been
3005 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3006 * that we have parsed an entire message.
3008 * In the case of extended messages, we accept the length
3009 * byte outright and perform more checking once we know the
3010 * extended message type.
3012 switch (ahc
->msgin_buf
[0]) {
3013 case MSG_DISCONNECT
:
3014 case MSG_SAVEDATAPOINTER
:
3015 case MSG_CMDCOMPLETE
:
3016 case MSG_RESTOREPOINTERS
:
3017 case MSG_IGN_WIDE_RESIDUE
:
3019 * End our message loop as these are messages
3020 * the sequencer handles on its own.
3022 done
= MSGLOOP_TERMINATED
;
3024 case MSG_MESSAGE_REJECT
:
3025 response
= ahc_handle_msg_reject(ahc
, devinfo
);
3028 done
= MSGLOOP_MSGCOMPLETE
;
3032 /* Wait for enough of the message to begin validation */
3033 if (ahc
->msgin_index
< 2)
3035 switch (ahc
->msgin_buf
[2]) {
3038 struct ahc_syncrate
*syncrate
;
3044 if (ahc
->msgin_buf
[1] != MSG_EXT_SDTR_LEN
) {
3050 * Wait until we have both args before validating
3051 * and acting on this message.
3053 * Add one to MSG_EXT_SDTR_LEN to account for
3054 * the extended message preamble.
3056 if (ahc
->msgin_index
< (MSG_EXT_SDTR_LEN
+ 1))
3059 period
= ahc
->msgin_buf
[3];
3061 saved_offset
= offset
= ahc
->msgin_buf
[4];
3062 syncrate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
3065 ahc_validate_offset(ahc
, tinfo
, syncrate
, &offset
,
3066 targ_scsirate
& WIDEXFER
,
3069 printf("(%s:%c:%d:%d): Received "
3070 "SDTR period %x, offset %x\n\t"
3071 "Filtered to period %x, offset %x\n",
3072 ahc_name(ahc
), devinfo
->channel
,
3073 devinfo
->target
, devinfo
->lun
,
3074 ahc
->msgin_buf
[3], saved_offset
,
3077 ahc_set_syncrate(ahc
, devinfo
,
3079 offset
, ppr_options
,
3080 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3084 * See if we initiated Sync Negotiation
3085 * and didn't have to fall down to async
3088 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_SDTR
, TRUE
)) {
3090 if (saved_offset
!= offset
) {
3091 /* Went too low - force async */
3096 * Send our own SDTR in reply
3099 && devinfo
->role
== ROLE_INITIATOR
) {
3100 printf("(%s:%c:%d:%d): Target "
3102 ahc_name(ahc
), devinfo
->channel
,
3103 devinfo
->target
, devinfo
->lun
);
3105 ahc
->msgout_index
= 0;
3106 ahc
->msgout_len
= 0;
3107 ahc_construct_sdtr(ahc
, devinfo
,
3109 ahc
->msgout_index
= 0;
3112 done
= MSGLOOP_MSGCOMPLETE
;
3119 u_int sending_reply
;
3121 sending_reply
= FALSE
;
3122 if (ahc
->msgin_buf
[1] != MSG_EXT_WDTR_LEN
) {
3128 * Wait until we have our arg before validating
3129 * and acting on this message.
3131 * Add one to MSG_EXT_WDTR_LEN to account for
3132 * the extended message preamble.
3134 if (ahc
->msgin_index
< (MSG_EXT_WDTR_LEN
+ 1))
3137 bus_width
= ahc
->msgin_buf
[3];
3138 saved_width
= bus_width
;
3139 ahc_validate_width(ahc
, tinfo
, &bus_width
,
3142 printf("(%s:%c:%d:%d): Received WDTR "
3143 "%x filtered to %x\n",
3144 ahc_name(ahc
), devinfo
->channel
,
3145 devinfo
->target
, devinfo
->lun
,
3146 saved_width
, bus_width
);
3149 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_WDTR
, TRUE
)) {
3151 * Don't send a WDTR back to the
3152 * target, since we asked first.
3153 * If the width went higher than our
3154 * request, reject it.
3156 if (saved_width
> bus_width
) {
3158 printf("(%s:%c:%d:%d): requested %dBit "
3159 "transfers. Rejecting...\n",
3160 ahc_name(ahc
), devinfo
->channel
,
3161 devinfo
->target
, devinfo
->lun
,
3162 8 * (0x01 << bus_width
));
3167 * Send our own WDTR in reply
3170 && devinfo
->role
== ROLE_INITIATOR
) {
3171 printf("(%s:%c:%d:%d): Target "
3173 ahc_name(ahc
), devinfo
->channel
,
3174 devinfo
->target
, devinfo
->lun
);
3176 ahc
->msgout_index
= 0;
3177 ahc
->msgout_len
= 0;
3178 ahc_construct_wdtr(ahc
, devinfo
, bus_width
);
3179 ahc
->msgout_index
= 0;
3181 sending_reply
= TRUE
;
3184 * After a wide message, we are async, but
3185 * some devices don't seem to honor this portion
3186 * of the spec. Force a renegotiation of the
3187 * sync component of our transfer agreement even
3188 * if our goal is async. By updating our width
3189 * after forcing the negotiation, we avoid
3190 * renegotiating for width.
3192 ahc_update_neg_request(ahc
, devinfo
, tstate
,
3193 tinfo
, AHC_NEG_ALWAYS
);
3194 ahc_set_width(ahc
, devinfo
, bus_width
,
3195 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3197 if (sending_reply
== FALSE
&& reject
== FALSE
) {
3200 * We will always have an SDTR to send.
3202 ahc
->msgout_index
= 0;
3203 ahc
->msgout_len
= 0;
3204 ahc_build_transfer_msg(ahc
, devinfo
);
3205 ahc
->msgout_index
= 0;
3208 done
= MSGLOOP_MSGCOMPLETE
;
3213 struct ahc_syncrate
*syncrate
;
3220 u_int saved_ppr_options
;
3222 if (ahc
->msgin_buf
[1] != MSG_EXT_PPR_LEN
) {
3228 * Wait until we have all args before validating
3229 * and acting on this message.
3231 * Add one to MSG_EXT_PPR_LEN to account for
3232 * the extended message preamble.
3234 if (ahc
->msgin_index
< (MSG_EXT_PPR_LEN
+ 1))
3237 period
= ahc
->msgin_buf
[3];
3238 offset
= ahc
->msgin_buf
[5];
3239 bus_width
= ahc
->msgin_buf
[6];
3240 saved_width
= bus_width
;
3241 ppr_options
= ahc
->msgin_buf
[7];
3243 * According to the spec, a DT only
3244 * period factor with no DT option
3245 * set implies async.
3247 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
3250 saved_ppr_options
= ppr_options
;
3251 saved_offset
= offset
;
3254 * Mask out any options we don't support
3255 * on any controller. Transfer options are
3256 * only available if we are negotiating wide.
3258 ppr_options
&= MSG_EXT_PPR_DT_REQ
;
3262 ahc_validate_width(ahc
, tinfo
, &bus_width
,
3264 syncrate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
3267 ahc_validate_offset(ahc
, tinfo
, syncrate
,
3271 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_PPR
, TRUE
)) {
3273 * If we are unable to do any of the
3274 * requested options (we went too low),
3275 * then we'll have to reject the message.
3277 if (saved_width
> bus_width
3278 || saved_offset
!= offset
3279 || saved_ppr_options
!= ppr_options
) {
3288 if (devinfo
->role
!= ROLE_TARGET
)
3289 printf("(%s:%c:%d:%d): Target "
3291 ahc_name(ahc
), devinfo
->channel
,
3292 devinfo
->target
, devinfo
->lun
);
3294 printf("(%s:%c:%d:%d): Initiator "
3296 ahc_name(ahc
), devinfo
->channel
,
3297 devinfo
->target
, devinfo
->lun
);
3298 ahc
->msgout_index
= 0;
3299 ahc
->msgout_len
= 0;
3300 ahc_construct_ppr(ahc
, devinfo
, period
, offset
,
3301 bus_width
, ppr_options
);
3302 ahc
->msgout_index
= 0;
3306 printf("(%s:%c:%d:%d): Received PPR width %x, "
3307 "period %x, offset %x,options %x\n"
3308 "\tFiltered to width %x, period %x, "
3309 "offset %x, options %x\n",
3310 ahc_name(ahc
), devinfo
->channel
,
3311 devinfo
->target
, devinfo
->lun
,
3312 saved_width
, ahc
->msgin_buf
[3],
3313 saved_offset
, saved_ppr_options
,
3314 bus_width
, period
, offset
, ppr_options
);
3316 ahc_set_width(ahc
, devinfo
, bus_width
,
3317 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3319 ahc_set_syncrate(ahc
, devinfo
,
3321 offset
, ppr_options
,
3322 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3324 done
= MSGLOOP_MSGCOMPLETE
;
3328 /* Unknown extended message. Reject it. */
3334 #ifdef AHC_TARGET_MODE
3335 case MSG_BUS_DEV_RESET
:
3336 ahc_handle_devreset(ahc
, devinfo
,
3338 "Bus Device Reset Received",
3339 /*verbose_level*/0);
3341 done
= MSGLOOP_TERMINATED
;
3345 case MSG_CLEAR_QUEUE
:
3349 /* Target mode messages */
3350 if (devinfo
->role
!= ROLE_TARGET
) {
3354 tag
= SCB_LIST_NULL
;
3355 if (ahc
->msgin_buf
[0] == MSG_ABORT_TAG
)
3356 tag
= ahc_inb(ahc
, INITIATOR_TAG
);
3357 ahc_abort_scbs(ahc
, devinfo
->target
, devinfo
->channel
,
3358 devinfo
->lun
, tag
, ROLE_TARGET
,
3361 tstate
= ahc
->enabled_targets
[devinfo
->our_scsiid
];
3362 if (tstate
!= NULL
) {
3363 struct ahc_tmode_lstate
* lstate
;
3365 lstate
= tstate
->enabled_luns
[devinfo
->lun
];
3366 if (lstate
!= NULL
) {
3367 ahc_queue_lstate_event(ahc
, lstate
,
3368 devinfo
->our_scsiid
,
3371 ahc_send_lstate_events(ahc
, lstate
);
3375 done
= MSGLOOP_TERMINATED
;
3379 case MSG_TERM_IO_PROC
:
3387 * Setup to reject the message.
3389 ahc
->msgout_index
= 0;
3390 ahc
->msgout_len
= 1;
3391 ahc
->msgout_buf
[0] = MSG_MESSAGE_REJECT
;
3392 done
= MSGLOOP_MSGCOMPLETE
;
3396 if (done
!= MSGLOOP_IN_PROG
&& !response
)
3397 /* Clear the outgoing message buffer */
3398 ahc
->msgout_len
= 0;
3404 * Process a message reject message.
3407 ahc_handle_msg_reject(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
3410 * What we care about here is if we had an
3411 * outstanding SDTR or WDTR message for this
3412 * target. If we did, this is a signal that
3413 * the target is refusing negotiation.
3416 struct ahc_initiator_tinfo
*tinfo
;
3417 struct ahc_tmode_tstate
*tstate
;
3422 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3423 scb
= ahc_lookup_scb(ahc
, scb_index
);
3424 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
,
3425 devinfo
->our_scsiid
,
3426 devinfo
->target
, &tstate
);
3427 /* Might be necessary */
3428 last_msg
= ahc_inb(ahc
, LAST_MSG
);
3430 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_PPR
, /*full*/FALSE
)) {
3432 * Target does not support the PPR message.
3433 * Attempt to negotiate SPI-2 style.
3436 printf("(%s:%c:%d:%d): PPR Rejected. "
3437 "Trying WDTR/SDTR\n",
3438 ahc_name(ahc
), devinfo
->channel
,
3439 devinfo
->target
, devinfo
->lun
);
3441 tinfo
->goal
.ppr_options
= 0;
3442 tinfo
->curr
.transport_version
= 2;
3443 tinfo
->goal
.transport_version
= 2;
3444 ahc
->msgout_index
= 0;
3445 ahc
->msgout_len
= 0;
3446 ahc_build_transfer_msg(ahc
, devinfo
);
3447 ahc
->msgout_index
= 0;
3449 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_WDTR
, /*full*/FALSE
)) {
3451 /* note 8bit xfers */
3452 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3453 "8bit transfers\n", ahc_name(ahc
),
3454 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
3455 ahc_set_width(ahc
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
3456 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3459 * No need to clear the sync rate. If the target
3460 * did not accept the command, our syncrate is
3461 * unaffected. If the target started the negotiation,
3462 * but rejected our response, we already cleared the
3463 * sync rate before sending our WDTR.
3465 if (tinfo
->goal
.offset
!= tinfo
->curr
.offset
) {
3467 /* Start the sync negotiation */
3468 ahc
->msgout_index
= 0;
3469 ahc
->msgout_len
= 0;
3470 ahc_build_transfer_msg(ahc
, devinfo
);
3471 ahc
->msgout_index
= 0;
3474 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_SDTR
, /*full*/FALSE
)) {
3475 /* note asynch xfers and clear flag */
3476 ahc_set_syncrate(ahc
, devinfo
, /*syncrate*/NULL
, /*period*/0,
3477 /*offset*/0, /*ppr_options*/0,
3478 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3480 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3481 "Using asynchronous transfers\n",
3482 ahc_name(ahc
), devinfo
->channel
,
3483 devinfo
->target
, devinfo
->lun
);
3484 } else if ((scb
->hscb
->control
& MSG_SIMPLE_TASK
) != 0) {
3488 tag_type
= (scb
->hscb
->control
& MSG_SIMPLE_TASK
);
3490 if (tag_type
== MSG_SIMPLE_TASK
) {
3491 printf("(%s:%c:%d:%d): refuses tagged commands. "
3492 "Performing non-tagged I/O\n", ahc_name(ahc
),
3493 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
3494 ahc_set_tags(ahc
, devinfo
, AHC_QUEUE_NONE
);
3497 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3498 "Performing simple queue tagged I/O only\n",
3499 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
3500 devinfo
->lun
, tag_type
== MSG_ORDERED_TASK
3501 ? "ordered" : "head of queue");
3502 ahc_set_tags(ahc
, devinfo
, AHC_QUEUE_BASIC
);
3507 * Resend the identify for this CCB as the target
3508 * may believe that the selection is invalid otherwise.
3510 ahc_outb(ahc
, SCB_CONTROL
,
3511 ahc_inb(ahc
, SCB_CONTROL
) & mask
);
3512 scb
->hscb
->control
&= mask
;
3513 ahc_set_transaction_tag(scb
, /*enabled*/FALSE
,
3514 /*type*/MSG_SIMPLE_TASK
);
3515 ahc_outb(ahc
, MSG_OUT
, MSG_IDENTIFYFLAG
);
3516 ahc_assert_atn(ahc
);
3519 * This transaction is now at the head of
3520 * the untagged queue for this target.
3522 if ((ahc
->flags
& AHC_SCB_BTT
) == 0) {
3523 struct scb_tailq
*untagged_q
;
3526 &(ahc
->untagged_queues
[devinfo
->target_offset
]);
3527 TAILQ_INSERT_HEAD(untagged_q
, scb
, links
.tqe
);
3528 scb
->flags
|= SCB_UNTAGGEDQ
;
3530 ahc_busy_tcl(ahc
, BUILD_TCL(scb
->hscb
->scsiid
, devinfo
->lun
),
3534 * Requeue all tagged commands for this target
3535 * currently in our posession so they can be
3536 * converted to untagged commands.
3538 ahc_search_qinfifo(ahc
, SCB_GET_TARGET(ahc
, scb
),
3539 SCB_GET_CHANNEL(ahc
, scb
),
3540 SCB_GET_LUN(scb
), /*tag*/SCB_LIST_NULL
,
3541 ROLE_INITIATOR
, CAM_REQUEUE_REQ
,
3545 * Otherwise, we ignore it.
3547 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3548 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
3555 * Process an ingnore wide residue message.
3558 ahc_handle_ign_wide_residue(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
3563 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3564 scb
= ahc_lookup_scb(ahc
, scb_index
);
3566 * XXX Actually check data direction in the sequencer?
3567 * Perhaps add datadir to some spare bits in the hscb?
3569 if ((ahc_inb(ahc
, SEQ_FLAGS
) & DPHASE
) == 0
3570 || ahc_get_transfer_dir(scb
) != CAM_DIR_IN
) {
3572 * Ignore the message if we haven't
3573 * seen an appropriate data phase yet.
3577 * If the residual occurred on the last
3578 * transfer and the transfer request was
3579 * expected to end on an odd count, do
3580 * nothing. Otherwise, subtract a byte
3581 * and update the residual count accordingly.
3585 sgptr
= ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
);
3586 if ((sgptr
& SG_LIST_NULL
) != 0
3587 && (ahc_inb(ahc
, SCB_LUN
) & SCB_XFERLEN_ODD
) != 0) {
3589 * If the residual occurred on the last
3590 * transfer and the transfer request was
3591 * expected to end on an odd count, do
3595 struct ahc_dma_seg
*sg
;
3600 /* Pull in all of the sgptr */
3601 sgptr
= ahc_inl(ahc
, SCB_RESIDUAL_SGPTR
);
3602 data_cnt
= ahc_inl(ahc
, SCB_RESIDUAL_DATACNT
);
3604 if ((sgptr
& SG_LIST_NULL
) != 0) {
3606 * The residual data count is not updated
3607 * for the command run to completion case.
3608 * Explicitly zero the count.
3610 data_cnt
&= ~AHC_SG_LEN_MASK
;
3613 data_addr
= ahc_inl(ahc
, SHADDR
);
3617 sgptr
&= SG_PTR_MASK
;
3619 sg
= ahc_sg_bus_to_virt(scb
, sgptr
);
3622 * The residual sg ptr points to the next S/G
3623 * to load so we must go back one.
3626 sglen
= ahc_le32toh(sg
->len
) & AHC_SG_LEN_MASK
;
3627 if (sg
!= scb
->sg_list
3628 && sglen
< (data_cnt
& AHC_SG_LEN_MASK
)) {
3631 sglen
= ahc_le32toh(sg
->len
);
3633 * Preserve High Address and SG_LIST bits
3634 * while setting the count to 1.
3636 data_cnt
= 1 | (sglen
& (~AHC_SG_LEN_MASK
));
3637 data_addr
= ahc_le32toh(sg
->addr
)
3638 + (sglen
& AHC_SG_LEN_MASK
) - 1;
3641 * Increment sg so it points to the
3645 sgptr
= ahc_sg_virt_to_bus(scb
, sg
);
3647 ahc_outl(ahc
, SCB_RESIDUAL_SGPTR
, sgptr
);
3648 ahc_outl(ahc
, SCB_RESIDUAL_DATACNT
, data_cnt
);
3650 * Toggle the "oddness" of the transfer length
3651 * to handle this mid-transfer ignore wide
3652 * residue. This ensures that the oddness is
3653 * correct for subsequent data transfers.
3655 ahc_outb(ahc
, SCB_LUN
,
3656 ahc_inb(ahc
, SCB_LUN
) ^ SCB_XFERLEN_ODD
);
3663 * Reinitialize the data pointers for the active transfer
3664 * based on its current residual.
3667 ahc_reinitialize_dataptrs(struct ahc_softc
*ahc
)
3670 struct ahc_dma_seg
*sg
;
3676 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3677 scb
= ahc_lookup_scb(ahc
, scb_index
);
3678 sgptr
= (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 3) << 24)
3679 | (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 2) << 16)
3680 | (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 1) << 8)
3681 | ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
);
3683 sgptr
&= SG_PTR_MASK
;
3684 sg
= ahc_sg_bus_to_virt(scb
, sgptr
);
3686 /* The residual sg_ptr always points to the next sg */
3689 resid
= (ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
+ 2) << 16)
3690 | (ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
+ 1) << 8)
3691 | ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
);
3693 dataptr
= ahc_le32toh(sg
->addr
)
3694 + (ahc_le32toh(sg
->len
) & AHC_SG_LEN_MASK
)
3696 if ((ahc
->flags
& AHC_39BIT_ADDRESSING
) != 0) {
3699 dscommand1
= ahc_inb(ahc
, DSCOMMAND1
);
3700 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
| HADDLDSEL0
);
3701 ahc_outb(ahc
, HADDR
,
3702 (ahc_le32toh(sg
->len
) >> 24) & SG_HIGH_ADDR_BITS
);
3703 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
);
3705 ahc_outb(ahc
, HADDR
+ 3, dataptr
>> 24);
3706 ahc_outb(ahc
, HADDR
+ 2, dataptr
>> 16);
3707 ahc_outb(ahc
, HADDR
+ 1, dataptr
>> 8);
3708 ahc_outb(ahc
, HADDR
, dataptr
);
3709 ahc_outb(ahc
, HCNT
+ 2, resid
>> 16);
3710 ahc_outb(ahc
, HCNT
+ 1, resid
>> 8);
3711 ahc_outb(ahc
, HCNT
, resid
);
3712 if ((ahc
->features
& AHC_ULTRA2
) == 0) {
3713 ahc_outb(ahc
, STCNT
+ 2, resid
>> 16);
3714 ahc_outb(ahc
, STCNT
+ 1, resid
>> 8);
3715 ahc_outb(ahc
, STCNT
, resid
);
3720 * Handle the effects of issuing a bus device reset message.
3723 ahc_handle_devreset(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
3724 cam_status status
, char *message
, int verbose_level
)
3726 #ifdef AHC_TARGET_MODE
3727 struct ahc_tmode_tstate
* tstate
;
3732 found
= ahc_abort_scbs(ahc
, devinfo
->target
, devinfo
->channel
,
3733 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, devinfo
->role
,
3736 #ifdef AHC_TARGET_MODE
3738 * Send an immediate notify ccb to all target mord peripheral
3739 * drivers affected by this action.
3741 tstate
= ahc
->enabled_targets
[devinfo
->our_scsiid
];
3742 if (tstate
!= NULL
) {
3743 for (lun
= 0; lun
< AHC_NUM_LUNS
; lun
++) {
3744 struct ahc_tmode_lstate
* lstate
;
3746 lstate
= tstate
->enabled_luns
[lun
];
3750 ahc_queue_lstate_event(ahc
, lstate
, devinfo
->our_scsiid
,
3751 MSG_BUS_DEV_RESET
, /*arg*/0);
3752 ahc_send_lstate_events(ahc
, lstate
);
3758 * Go back to async/narrow transfers and renegotiate.
3760 ahc_set_width(ahc
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
3761 AHC_TRANS_CUR
, /*paused*/TRUE
);
3762 ahc_set_syncrate(ahc
, devinfo
, /*syncrate*/NULL
,
3763 /*period*/0, /*offset*/0, /*ppr_options*/0,
3764 AHC_TRANS_CUR
, /*paused*/TRUE
);
3766 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
3767 CAM_LUN_WILDCARD
, AC_SENT_BDR
, NULL
);
3770 && (verbose_level
<= bootverbose
))
3771 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc
),
3772 message
, devinfo
->channel
, devinfo
->target
, found
);
3775 #ifdef AHC_TARGET_MODE
3777 ahc_setup_target_msgin(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
3782 * To facilitate adding multiple messages together,
3783 * each routine should increment the index and len
3784 * variables instead of setting them explicitly.
3786 ahc
->msgout_index
= 0;
3787 ahc
->msgout_len
= 0;
3789 if (scb
!= NULL
&& (scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0)
3790 ahc_build_transfer_msg(ahc
, devinfo
);
3792 panic("ahc_intr: AWAITING target message with no message");
3794 ahc
->msgout_index
= 0;
3795 ahc
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
3798 /**************************** Initialization **********************************/
3800 * Allocate a controller structure for a new device
3801 * and perform initial initializion.
3804 ahc_alloc(void *platform_arg
, char *name
)
3806 struct ahc_softc
*ahc
;
3810 ahc
= malloc(sizeof(*ahc
), M_DEVBUF
, M_NOWAIT
);
3812 printf("aic7xxx: cannot malloc softc!\n");
3813 free(name
, M_DEVBUF
);
3817 ahc
= device_get_softc((device_t
)platform_arg
);
3819 memset(ahc
, 0, sizeof(*ahc
));
3820 ahc
->seep_config
= malloc(sizeof(*ahc
->seep_config
),
3821 M_DEVBUF
, M_NOWAIT
);
3822 if (ahc
->seep_config
== NULL
) {
3824 free(ahc
, M_DEVBUF
);
3826 free(name
, M_DEVBUF
);
3829 LIST_INIT(&ahc
->pending_scbs
);
3830 /* We don't know our unit number until the OSM sets it */
3833 ahc
->description
= NULL
;
3835 ahc
->channel_b
= 'B';
3836 ahc
->chip
= AHC_NONE
;
3837 ahc
->features
= AHC_FENONE
;
3838 ahc
->bugs
= AHC_BUGNONE
;
3839 ahc
->flags
= AHC_FNONE
;
3841 * Default to all error reporting enabled with the
3842 * sequencer operating at its fastest speed.
3843 * The bus attach code may modify this.
3845 ahc
->seqctl
= FASTMODE
;
3847 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++)
3848 TAILQ_INIT(&ahc
->untagged_queues
[i
]);
3849 if (ahc_platform_alloc(ahc
, platform_arg
) != 0) {
3857 ahc_softc_init(struct ahc_softc
*ahc
)
3860 /* The IRQMS bit is only valid on VL and EISA chips */
3861 if ((ahc
->chip
& AHC_PCI
) == 0)
3862 ahc
->unpause
= ahc_inb(ahc
, HCNTRL
) & IRQMS
;
3865 ahc
->pause
= ahc
->unpause
| PAUSE
;
3866 /* XXX The shared scb data stuff should be deprecated */
3867 if (ahc
->scb_data
== NULL
) {
3868 ahc
->scb_data
= malloc(sizeof(*ahc
->scb_data
),
3869 M_DEVBUF
, M_NOWAIT
);
3870 if (ahc
->scb_data
== NULL
)
3872 memset(ahc
->scb_data
, 0, sizeof(*ahc
->scb_data
));
3879 ahc_set_unit(struct ahc_softc
*ahc
, int unit
)
3885 ahc_set_name(struct ahc_softc
*ahc
, char *name
)
3887 if (ahc
->name
!= NULL
)
3888 free(ahc
->name
, M_DEVBUF
);
3893 ahc_free(struct ahc_softc
*ahc
)
3897 switch (ahc
->init_level
) {
3903 ahc_dmamap_unload(ahc
, ahc
->shared_data_dmat
,
3904 ahc
->shared_data_dmamap
);
3907 ahc_dmamem_free(ahc
, ahc
->shared_data_dmat
, ahc
->qoutfifo
,
3908 ahc
->shared_data_dmamap
);
3909 ahc_dmamap_destroy(ahc
, ahc
->shared_data_dmat
,
3910 ahc
->shared_data_dmamap
);
3913 ahc_dma_tag_destroy(ahc
, ahc
->shared_data_dmat
);
3916 ahc_dma_tag_destroy(ahc
, ahc
->buffer_dmat
);
3924 ahc_dma_tag_destroy(ahc
, ahc
->parent_dmat
);
3926 ahc_platform_free(ahc
);
3927 ahc_fini_scbdata(ahc
);
3928 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++) {
3929 struct ahc_tmode_tstate
*tstate
;
3931 tstate
= ahc
->enabled_targets
[i
];
3932 if (tstate
!= NULL
) {
3933 #ifdef AHC_TARGET_MODE
3936 for (j
= 0; j
< AHC_NUM_LUNS
; j
++) {
3937 struct ahc_tmode_lstate
*lstate
;
3939 lstate
= tstate
->enabled_luns
[j
];
3940 if (lstate
!= NULL
) {
3941 xpt_free_path(lstate
->path
);
3942 free(lstate
, M_DEVBUF
);
3946 free(tstate
, M_DEVBUF
);
3949 #ifdef AHC_TARGET_MODE
3950 if (ahc
->black_hole
!= NULL
) {
3951 xpt_free_path(ahc
->black_hole
->path
);
3952 free(ahc
->black_hole
, M_DEVBUF
);
3955 if (ahc
->name
!= NULL
)
3956 free(ahc
->name
, M_DEVBUF
);
3957 if (ahc
->seep_config
!= NULL
)
3958 free(ahc
->seep_config
, M_DEVBUF
);
3960 free(ahc
, M_DEVBUF
);
3966 ahc_shutdown(void *arg
)
3968 struct ahc_softc
*ahc
;
3971 ahc
= (struct ahc_softc
*)arg
;
3973 /* This will reset most registers to 0, but not all */
3974 ahc_reset(ahc
, /*reinit*/FALSE
);
3975 ahc_outb(ahc
, SCSISEQ
, 0);
3976 ahc_outb(ahc
, SXFRCTL0
, 0);
3977 ahc_outb(ahc
, DSPCISTATUS
, 0);
3979 for (i
= TARG_SCSIRATE
; i
< SCSICONF
; i
++)
3980 ahc_outb(ahc
, i
, 0);
3984 * Reset the controller and record some information about it
3985 * that is only available just after a reset. If "reinit" is
3986 * non-zero, this reset occured after initial configuration
3987 * and the caller requests that the chip be fully reinitialized
3988 * to a runable state. Chip interrupts are *not* enabled after
3989 * a reinitialization. The caller must enable interrupts via
3990 * ahc_intr_enable().
3993 ahc_reset(struct ahc_softc
*ahc
, int reinit
)
3996 u_int sxfrctl1_a
, sxfrctl1_b
;
4001 * Preserve the value of the SXFRCTL1 register for all channels.
4002 * It contains settings that affect termination and we don't want
4003 * to disturb the integrity of the bus.
4006 if ((ahc_inb(ahc
, HCNTRL
) & CHIPRST
) != 0) {
4008 * The chip has not been initialized since
4009 * PCI/EISA/VLB bus reset. Don't trust
4010 * "left over BIOS data".
4012 ahc
->flags
|= AHC_NO_BIOS_INIT
;
4015 if ((ahc
->chip
& AHC_CHIPID_MASK
) == AHC_AIC7770
) {
4019 * Save channel B's settings in case this chip
4020 * is setup for TWIN channel operation.
4022 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
4023 ahc_outb(ahc
, SBLKCTL
, sblkctl
| SELBUSB
);
4024 sxfrctl1_b
= ahc_inb(ahc
, SXFRCTL1
);
4025 ahc_outb(ahc
, SBLKCTL
, sblkctl
& ~SELBUSB
);
4027 sxfrctl1_a
= ahc_inb(ahc
, SXFRCTL1
);
4029 ahc_outb(ahc
, HCNTRL
, CHIPRST
| ahc
->pause
);
4032 * Ensure that the reset has finished. We delay 1000us
4033 * prior to reading the register to make sure the chip
4034 * has sufficiently completed its reset to handle register
4040 } while (--wait
&& !(ahc_inb(ahc
, HCNTRL
) & CHIPRSTACK
));
4043 printf("%s: WARNING - Failed chip reset! "
4044 "Trying to initialize anyway.\n", ahc_name(ahc
));
4046 ahc_outb(ahc
, HCNTRL
, ahc
->pause
);
4048 /* Determine channel configuration */
4049 sblkctl
= ahc_inb(ahc
, SBLKCTL
) & (SELBUSB
|SELWIDE
);
4050 /* No Twin Channel PCI cards */
4051 if ((ahc
->chip
& AHC_PCI
) != 0)
4052 sblkctl
&= ~SELBUSB
;
4055 /* Single Narrow Channel */
4059 ahc
->features
|= AHC_WIDE
;
4063 ahc
->features
|= AHC_TWIN
;
4066 printf(" Unsupported adapter type. Ignoring\n");
4073 * We must always initialize STPWEN to 1 before we
4074 * restore the saved values. STPWEN is initialized
4075 * to a tri-state condition which can only be cleared
4078 if ((ahc
->features
& AHC_TWIN
) != 0) {
4081 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
4082 ahc_outb(ahc
, SBLKCTL
, sblkctl
| SELBUSB
);
4083 ahc_outb(ahc
, SXFRCTL1
, sxfrctl1_b
);
4084 ahc_outb(ahc
, SBLKCTL
, sblkctl
& ~SELBUSB
);
4086 ahc_outb(ahc
, SXFRCTL1
, sxfrctl1_a
);
4091 * If a recovery action has forced a chip reset,
4092 * re-initialize the chip to our liking.
4094 error
= ahc
->bus_chip_init(ahc
);
4104 * Determine the number of SCBs available on the controller
4107 ahc_probe_scbs(struct ahc_softc
*ahc
) {
4110 for (i
= 0; i
< AHC_SCB_MAX
; i
++) {
4112 ahc_outb(ahc
, SCBPTR
, i
);
4113 ahc_outb(ahc
, SCB_BASE
, i
);
4114 if (ahc_inb(ahc
, SCB_BASE
) != i
)
4116 ahc_outb(ahc
, SCBPTR
, 0);
4117 if (ahc_inb(ahc
, SCB_BASE
) != 0)
4124 ahc_dmamap_cb(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
4128 baddr
= (dma_addr_t
*)arg
;
4129 *baddr
= segs
->ds_addr
;
4133 ahc_build_free_scb_list(struct ahc_softc
*ahc
)
4139 if ((ahc
->flags
& AHC_LSCBS_ENABLED
) != 0)
4142 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
4145 ahc_outb(ahc
, SCBPTR
, i
);
4148 * Touch all SCB bytes to avoid parity errors
4149 * should one of our debugging routines read
4150 * an otherwise uninitiatlized byte.
4152 for (j
= 0; j
< scbsize
; j
++)
4153 ahc_outb(ahc
, SCB_BASE
+j
, 0xFF);
4155 /* Clear the control byte. */
4156 ahc_outb(ahc
, SCB_CONTROL
, 0);
4158 /* Set the next pointer */
4159 if ((ahc
->flags
& AHC_PAGESCBS
) != 0)
4160 ahc_outb(ahc
, SCB_NEXT
, i
+1);
4162 ahc_outb(ahc
, SCB_NEXT
, SCB_LIST_NULL
);
4164 /* Make the tag number, SCSIID, and lun invalid */
4165 ahc_outb(ahc
, SCB_TAG
, SCB_LIST_NULL
);
4166 ahc_outb(ahc
, SCB_SCSIID
, 0xFF);
4167 ahc_outb(ahc
, SCB_LUN
, 0xFF);
4170 if ((ahc
->flags
& AHC_PAGESCBS
) != 0) {
4171 /* SCB 0 heads the free list. */
4172 ahc_outb(ahc
, FREE_SCBH
, 0);
4175 ahc_outb(ahc
, FREE_SCBH
, SCB_LIST_NULL
);
4178 /* Make sure that the last SCB terminates the free list */
4179 ahc_outb(ahc
, SCBPTR
, i
-1);
4180 ahc_outb(ahc
, SCB_NEXT
, SCB_LIST_NULL
);
4184 ahc_init_scbdata(struct ahc_softc
*ahc
)
4186 struct scb_data
*scb_data
;
4188 scb_data
= ahc
->scb_data
;
4189 SLIST_INIT(&scb_data
->free_scbs
);
4190 SLIST_INIT(&scb_data
->sg_maps
);
4192 /* Allocate SCB resources */
4193 scb_data
->scbarray
=
4194 (struct scb
*)malloc(sizeof(struct scb
) * AHC_SCB_MAX_ALLOC
,
4195 M_DEVBUF
, M_NOWAIT
);
4196 if (scb_data
->scbarray
== NULL
)
4198 memset(scb_data
->scbarray
, 0, sizeof(struct scb
) * AHC_SCB_MAX_ALLOC
);
4200 /* Determine the number of hardware SCBs and initialize them */
4202 scb_data
->maxhscbs
= ahc_probe_scbs(ahc
);
4203 if (ahc
->scb_data
->maxhscbs
== 0) {
4204 printf("%s: No SCB space found\n", ahc_name(ahc
));
4209 * Create our DMA tags. These tags define the kinds of device
4210 * accessible memory allocations and memory mappings we will
4211 * need to perform during normal operation.
4213 * Unless we need to further restrict the allocation, we rely
4214 * on the restrictions of the parent dmat, hence the common
4215 * use of MAXADDR and MAXSIZE.
4218 /* DMA tag for our hardware scb structures */
4219 if (ahc_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4220 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4221 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4222 /*highaddr*/BUS_SPACE_MAXADDR
,
4223 /*filter*/NULL
, /*filterarg*/NULL
,
4224 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
),
4226 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4227 /*flags*/0, &scb_data
->hscb_dmat
) != 0) {
4231 scb_data
->init_level
++;
4233 /* Allocation for our hscbs */
4234 if (ahc_dmamem_alloc(ahc
, scb_data
->hscb_dmat
,
4235 (void **)&scb_data
->hscbs
,
4236 BUS_DMA_NOWAIT
, &scb_data
->hscb_dmamap
) != 0) {
4240 scb_data
->init_level
++;
4242 /* And permanently map them */
4243 ahc_dmamap_load(ahc
, scb_data
->hscb_dmat
, scb_data
->hscb_dmamap
,
4245 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
),
4246 ahc_dmamap_cb
, &scb_data
->hscb_busaddr
, /*flags*/0);
4248 scb_data
->init_level
++;
4250 /* DMA tag for our sense buffers */
4251 if (ahc_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4252 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4253 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4254 /*highaddr*/BUS_SPACE_MAXADDR
,
4255 /*filter*/NULL
, /*filterarg*/NULL
,
4256 AHC_SCB_MAX_ALLOC
* sizeof(struct scsi_sense_data
),
4258 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4259 /*flags*/0, &scb_data
->sense_dmat
) != 0) {
4263 scb_data
->init_level
++;
4266 if (ahc_dmamem_alloc(ahc
, scb_data
->sense_dmat
,
4267 (void **)&scb_data
->sense
,
4268 BUS_DMA_NOWAIT
, &scb_data
->sense_dmamap
) != 0) {
4272 scb_data
->init_level
++;
4274 /* And permanently map them */
4275 ahc_dmamap_load(ahc
, scb_data
->sense_dmat
, scb_data
->sense_dmamap
,
4277 AHC_SCB_MAX_ALLOC
* sizeof(struct scsi_sense_data
),
4278 ahc_dmamap_cb
, &scb_data
->sense_busaddr
, /*flags*/0);
4280 scb_data
->init_level
++;
4282 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4283 if (ahc_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/8,
4284 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4285 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4286 /*highaddr*/BUS_SPACE_MAXADDR
,
4287 /*filter*/NULL
, /*filterarg*/NULL
,
4288 PAGE_SIZE
, /*nsegments*/1,
4289 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4290 /*flags*/0, &scb_data
->sg_dmat
) != 0) {
4294 scb_data
->init_level
++;
4296 /* Perform initial CCB allocation */
4297 memset(scb_data
->hscbs
, 0,
4298 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
));
4299 ahc_alloc_scbs(ahc
);
4301 if (scb_data
->numscbs
== 0) {
4302 printf("%s: ahc_init_scbdata - "
4303 "Unable to allocate initial scbs\n",
4309 * Reserve the next queued SCB.
4311 ahc
->next_queued_scb
= ahc_get_scb(ahc
);
4314 * Note that we were successfull
4324 ahc_fini_scbdata(struct ahc_softc
*ahc
)
4326 struct scb_data
*scb_data
;
4328 scb_data
= ahc
->scb_data
;
4329 if (scb_data
== NULL
)
4332 switch (scb_data
->init_level
) {
4336 struct sg_map_node
*sg_map
;
4338 while ((sg_map
= SLIST_FIRST(&scb_data
->sg_maps
))!= NULL
) {
4339 SLIST_REMOVE_HEAD(&scb_data
->sg_maps
, links
);
4340 ahc_dmamap_unload(ahc
, scb_data
->sg_dmat
,
4342 ahc_dmamem_free(ahc
, scb_data
->sg_dmat
,
4345 free(sg_map
, M_DEVBUF
);
4347 ahc_dma_tag_destroy(ahc
, scb_data
->sg_dmat
);
4350 ahc_dmamap_unload(ahc
, scb_data
->sense_dmat
,
4351 scb_data
->sense_dmamap
);
4353 ahc_dmamem_free(ahc
, scb_data
->sense_dmat
, scb_data
->sense
,
4354 scb_data
->sense_dmamap
);
4355 ahc_dmamap_destroy(ahc
, scb_data
->sense_dmat
,
4356 scb_data
->sense_dmamap
);
4358 ahc_dma_tag_destroy(ahc
, scb_data
->sense_dmat
);
4360 ahc_dmamap_unload(ahc
, scb_data
->hscb_dmat
,
4361 scb_data
->hscb_dmamap
);
4363 ahc_dmamem_free(ahc
, scb_data
->hscb_dmat
, scb_data
->hscbs
,
4364 scb_data
->hscb_dmamap
);
4365 ahc_dmamap_destroy(ahc
, scb_data
->hscb_dmat
,
4366 scb_data
->hscb_dmamap
);
4368 ahc_dma_tag_destroy(ahc
, scb_data
->hscb_dmat
);
4373 if (scb_data
->scbarray
!= NULL
)
4374 free(scb_data
->scbarray
, M_DEVBUF
);
4378 ahc_alloc_scbs(struct ahc_softc
*ahc
)
4380 struct scb_data
*scb_data
;
4381 struct scb
*next_scb
;
4382 struct sg_map_node
*sg_map
;
4383 dma_addr_t physaddr
;
4384 struct ahc_dma_seg
*segs
;
4388 scb_data
= ahc
->scb_data
;
4389 if (scb_data
->numscbs
>= AHC_SCB_MAX_ALLOC
)
4390 /* Can't allocate any more */
4393 next_scb
= &scb_data
->scbarray
[scb_data
->numscbs
];
4395 sg_map
= malloc(sizeof(*sg_map
), M_DEVBUF
, M_NOWAIT
);
4400 /* Allocate S/G space for the next batch of SCBS */
4401 if (ahc_dmamem_alloc(ahc
, scb_data
->sg_dmat
,
4402 (void **)&sg_map
->sg_vaddr
,
4403 BUS_DMA_NOWAIT
, &sg_map
->sg_dmamap
) != 0) {
4404 free(sg_map
, M_DEVBUF
);
4408 SLIST_INSERT_HEAD(&scb_data
->sg_maps
, sg_map
, links
);
4410 ahc_dmamap_load(ahc
, scb_data
->sg_dmat
, sg_map
->sg_dmamap
,
4411 sg_map
->sg_vaddr
, PAGE_SIZE
, ahc_dmamap_cb
,
4412 &sg_map
->sg_physaddr
, /*flags*/0);
4414 segs
= sg_map
->sg_vaddr
;
4415 physaddr
= sg_map
->sg_physaddr
;
4417 newcount
= (PAGE_SIZE
/ (AHC_NSEG
* sizeof(struct ahc_dma_seg
)));
4418 newcount
= MIN(newcount
, (AHC_SCB_MAX_ALLOC
- scb_data
->numscbs
));
4419 for (i
= 0; i
< newcount
; i
++) {
4420 struct scb_platform_data
*pdata
;
4424 pdata
= (struct scb_platform_data
*)malloc(sizeof(*pdata
),
4425 M_DEVBUF
, M_NOWAIT
);
4428 next_scb
->platform_data
= pdata
;
4429 next_scb
->sg_map
= sg_map
;
4430 next_scb
->sg_list
= segs
;
4432 * The sequencer always starts with the second entry.
4433 * The first entry is embedded in the scb.
4435 next_scb
->sg_list_phys
= physaddr
+ sizeof(struct ahc_dma_seg
);
4436 next_scb
->ahc_softc
= ahc
;
4437 next_scb
->flags
= SCB_FREE
;
4439 error
= ahc_dmamap_create(ahc
, ahc
->buffer_dmat
, /*flags*/0,
4444 next_scb
->hscb
= &scb_data
->hscbs
[scb_data
->numscbs
];
4445 next_scb
->hscb
->tag
= ahc
->scb_data
->numscbs
;
4446 SLIST_INSERT_HEAD(&ahc
->scb_data
->free_scbs
,
4447 next_scb
, links
.sle
);
4449 physaddr
+= (AHC_NSEG
* sizeof(struct ahc_dma_seg
));
4451 ahc
->scb_data
->numscbs
++;
4456 ahc_controller_info(struct ahc_softc
*ahc
, char *buf
)
4460 len
= sprintf(buf
, "%s: ", ahc_chip_names
[ahc
->chip
& AHC_CHIPID_MASK
]);
4462 if ((ahc
->features
& AHC_TWIN
) != 0)
4463 len
= sprintf(buf
, "Twin Channel, A SCSI Id=%d, "
4464 "B SCSI Id=%d, primary %c, ",
4465 ahc
->our_id
, ahc
->our_id_b
,
4466 (ahc
->flags
& AHC_PRIMARY_CHANNEL
) + 'A');
4472 if ((ahc
->features
& AHC_ULTRA
) != 0) {
4474 } else if ((ahc
->features
& AHC_DT
) != 0) {
4475 speed
= "Ultra160 ";
4476 } else if ((ahc
->features
& AHC_ULTRA2
) != 0) {
4479 if ((ahc
->features
& AHC_WIDE
) != 0) {
4484 len
= sprintf(buf
, "%s%s Channel %c, SCSI Id=%d, ",
4485 speed
, type
, ahc
->channel
, ahc
->our_id
);
4489 if ((ahc
->flags
& AHC_PAGESCBS
) != 0)
4490 sprintf(buf
, "%d/%d SCBs",
4491 ahc
->scb_data
->maxhscbs
, AHC_MAX_QUEUE
);
4493 sprintf(buf
, "%d SCBs", ahc
->scb_data
->maxhscbs
);
4497 ahc_chip_init(struct ahc_softc
*ahc
)
4503 u_int scsiseq_template
;
4506 ahc_outb(ahc
, SEQ_FLAGS
, 0);
4507 ahc_outb(ahc
, SEQ_FLAGS2
, 0);
4509 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4510 if (ahc
->features
& AHC_TWIN
) {
4513 * Setup Channel B first.
4515 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) | SELBUSB
);
4516 term
= (ahc
->flags
& AHC_TERM_ENB_B
) != 0 ? STPWEN
: 0;
4517 ahc_outb(ahc
, SCSIID
, ahc
->our_id_b
);
4518 scsi_conf
= ahc_inb(ahc
, SCSICONF
+ 1);
4519 ahc_outb(ahc
, SXFRCTL1
, (scsi_conf
& (ENSPCHK
|STIMESEL
))
4520 |term
|ahc
->seltime_b
|ENSTIMER
|ACTNEGEN
);
4521 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4522 ahc_outb(ahc
, SIMODE0
, ahc_inb(ahc
, SIMODE0
)|ENIOERR
);
4523 ahc_outb(ahc
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
4524 ahc_outb(ahc
, SXFRCTL0
, DFON
|SPIOEN
);
4526 /* Select Channel A */
4527 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) & ~SELBUSB
);
4529 term
= (ahc
->flags
& AHC_TERM_ENB_A
) != 0 ? STPWEN
: 0;
4530 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4531 ahc_outb(ahc
, SCSIID_ULTRA2
, ahc
->our_id
);
4533 ahc_outb(ahc
, SCSIID
, ahc
->our_id
);
4534 scsi_conf
= ahc_inb(ahc
, SCSICONF
);
4535 ahc_outb(ahc
, SXFRCTL1
, (scsi_conf
& (ENSPCHK
|STIMESEL
))
4537 |ENSTIMER
|ACTNEGEN
);
4538 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4539 ahc_outb(ahc
, SIMODE0
, ahc_inb(ahc
, SIMODE0
)|ENIOERR
);
4540 ahc_outb(ahc
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
4541 ahc_outb(ahc
, SXFRCTL0
, DFON
|SPIOEN
);
4543 /* There are no untagged SCBs active yet. */
4544 for (i
= 0; i
< 16; i
++) {
4545 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, 0));
4546 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
4550 * The SCB based BTT allows an entry per
4551 * target and lun pair.
4553 for (lun
= 1; lun
< AHC_NUM_LUNS
; lun
++)
4554 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, lun
));
4558 /* All of our queues are empty */
4559 for (i
= 0; i
< 256; i
++)
4560 ahc
->qoutfifo
[i
] = SCB_LIST_NULL
;
4561 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_PREREAD
);
4563 for (i
= 0; i
< 256; i
++)
4564 ahc
->qinfifo
[i
] = SCB_LIST_NULL
;
4566 if ((ahc
->features
& AHC_MULTI_TID
) != 0) {
4567 ahc_outb(ahc
, TARGID
, 0);
4568 ahc_outb(ahc
, TARGID
+ 1, 0);
4572 * Tell the sequencer where it can find our arrays in memory.
4574 physaddr
= ahc
->scb_data
->hscb_busaddr
;
4575 ahc_outb(ahc
, HSCB_ADDR
, physaddr
& 0xFF);
4576 ahc_outb(ahc
, HSCB_ADDR
+ 1, (physaddr
>> 8) & 0xFF);
4577 ahc_outb(ahc
, HSCB_ADDR
+ 2, (physaddr
>> 16) & 0xFF);
4578 ahc_outb(ahc
, HSCB_ADDR
+ 3, (physaddr
>> 24) & 0xFF);
4580 physaddr
= ahc
->shared_data_busaddr
;
4581 ahc_outb(ahc
, SHARED_DATA_ADDR
, physaddr
& 0xFF);
4582 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 1, (physaddr
>> 8) & 0xFF);
4583 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 2, (physaddr
>> 16) & 0xFF);
4584 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 3, (physaddr
>> 24) & 0xFF);
4587 * Initialize the group code to command length table.
4588 * This overrides the values in TARG_SCSIRATE, so only
4589 * setup the table after we have processed that information.
4591 ahc_outb(ahc
, CMDSIZE_TABLE
, 5);
4592 ahc_outb(ahc
, CMDSIZE_TABLE
+ 1, 9);
4593 ahc_outb(ahc
, CMDSIZE_TABLE
+ 2, 9);
4594 ahc_outb(ahc
, CMDSIZE_TABLE
+ 3, 0);
4595 ahc_outb(ahc
, CMDSIZE_TABLE
+ 4, 15);
4596 ahc_outb(ahc
, CMDSIZE_TABLE
+ 5, 11);
4597 ahc_outb(ahc
, CMDSIZE_TABLE
+ 6, 0);
4598 ahc_outb(ahc
, CMDSIZE_TABLE
+ 7, 0);
4600 if ((ahc
->features
& AHC_HS_MAILBOX
) != 0)
4601 ahc_outb(ahc
, HS_MAILBOX
, 0);
4603 /* Tell the sequencer of our initial queue positions */
4604 if ((ahc
->features
& AHC_TARGETMODE
) != 0) {
4605 ahc
->tqinfifonext
= 1;
4606 ahc_outb(ahc
, KERNEL_TQINPOS
, ahc
->tqinfifonext
- 1);
4607 ahc_outb(ahc
, TQINPOS
, ahc
->tqinfifonext
);
4609 ahc
->qinfifonext
= 0;
4610 ahc
->qoutfifonext
= 0;
4611 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
4612 ahc_outb(ahc
, QOFF_CTLSTA
, SCB_QSIZE_256
);
4613 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
4614 ahc_outb(ahc
, SNSCB_QOFF
, ahc
->qinfifonext
);
4615 ahc_outb(ahc
, SDSCB_QOFF
, 0);
4617 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
4618 ahc_outb(ahc
, QINPOS
, ahc
->qinfifonext
);
4619 ahc_outb(ahc
, QOUTPOS
, ahc
->qoutfifonext
);
4622 /* We don't have any waiting selections */
4623 ahc_outb(ahc
, WAITING_SCBH
, SCB_LIST_NULL
);
4625 /* Our disconnection list is empty too */
4626 ahc_outb(ahc
, DISCONNECTED_SCBH
, SCB_LIST_NULL
);
4628 /* Message out buffer starts empty */
4629 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
);
4632 * Setup the allowed SCSI Sequences based on operational mode.
4633 * If we are a target, we'll enalbe select in operations once
4634 * we've had a lun enabled.
4636 scsiseq_template
= ENSELO
|ENAUTOATNO
|ENAUTOATNP
;
4637 if ((ahc
->flags
& AHC_INITIATORROLE
) != 0)
4638 scsiseq_template
|= ENRSELI
;
4639 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq_template
);
4641 /* Initialize our list of free SCBs. */
4642 ahc_build_free_scb_list(ahc
);
4645 * Tell the sequencer which SCB will be the next one it receives.
4647 ahc_outb(ahc
, NEXT_QUEUED_SCB
, ahc
->next_queued_scb
->hscb
->tag
);
4650 * Load the Sequencer program and Enable the adapter
4654 printf("%s: Downloading Sequencer Program...",
4657 error
= ahc_loadseq(ahc
);
4661 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
4665 * Wait for up to 500ms for our transceivers
4666 * to settle. If the adapter does not have
4667 * a cable attached, the transceivers may
4668 * never settle, so don't complain if we
4672 (ahc_inb(ahc
, SBLKCTL
) & (ENAB40
|ENAB20
)) == 0 && wait
;
4681 * Start the board, ready for normal operation
4684 ahc_init(struct ahc_softc
*ahc
)
4692 size_t driver_data_size
;
4695 if ((ahc_debug
& AHC_DEBUG_SEQUENCER
) != 0)
4696 ahc
->flags
|= AHC_SEQUENCER_DEBUG
;
4699 #ifdef AHC_PRINT_SRAM
4700 printf("Scratch Ram:");
4701 for (i
= 0x20; i
< 0x5f; i
++) {
4702 if (((i
% 8) == 0) && (i
!= 0)) {
4705 printf (" 0x%x", ahc_inb(ahc
, i
));
4707 if ((ahc
->features
& AHC_MORE_SRAM
) != 0) {
4708 for (i
= 0x70; i
< 0x7f; i
++) {
4709 if (((i
% 8) == 0) && (i
!= 0)) {
4712 printf (" 0x%x", ahc_inb(ahc
, i
));
4717 * Reading uninitialized scratch ram may
4718 * generate parity errors.
4720 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
4721 ahc_outb(ahc
, CLRINT
, CLRBRKADRINT
);
4726 * Assume we have a board at this stage and it has been reset.
4728 if ((ahc
->flags
& AHC_USEDEFAULTS
) != 0)
4729 ahc
->our_id
= ahc
->our_id_b
= 7;
4732 * Default to allowing initiator operations.
4734 ahc
->flags
|= AHC_INITIATORROLE
;
4737 * Only allow target mode features if this unit has them enabled.
4739 if ((AHC_TMODE_ENABLE
& (0x1 << ahc
->unit
)) == 0)
4740 ahc
->features
&= ~AHC_TARGETMODE
;
4743 /* DMA tag for mapping buffers into device visible space. */
4744 if (ahc_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4745 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4746 /*lowaddr*/ahc
->flags
& AHC_39BIT_ADDRESSING
4747 ? (dma_addr_t
)0x7FFFFFFFFFULL
4748 : BUS_SPACE_MAXADDR_32BIT
,
4749 /*highaddr*/BUS_SPACE_MAXADDR
,
4750 /*filter*/NULL
, /*filterarg*/NULL
,
4751 /*maxsize*/(AHC_NSEG
- 1) * PAGE_SIZE
,
4752 /*nsegments*/AHC_NSEG
,
4753 /*maxsegsz*/AHC_MAXTRANSFER_SIZE
,
4754 /*flags*/BUS_DMA_ALLOCNOW
,
4755 &ahc
->buffer_dmat
) != 0) {
4763 * DMA tag for our command fifos and other data in system memory
4764 * the card's sequencer must be able to access. For initiator
4765 * roles, we need to allocate space for the qinfifo and qoutfifo.
4766 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4767 * When providing for the target mode role, we must additionally
4768 * provide space for the incoming target command fifo and an extra
4769 * byte to deal with a dma bug in some chip versions.
4771 driver_data_size
= 2 * 256 * sizeof(uint8_t);
4772 if ((ahc
->features
& AHC_TARGETMODE
) != 0)
4773 driver_data_size
+= AHC_TMODE_CMDS
* sizeof(struct target_cmd
)
4774 + /*DMA WideOdd Bug Buffer*/1;
4775 if (ahc_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4776 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4777 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4778 /*highaddr*/BUS_SPACE_MAXADDR
,
4779 /*filter*/NULL
, /*filterarg*/NULL
,
4782 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4783 /*flags*/0, &ahc
->shared_data_dmat
) != 0) {
4789 /* Allocation of driver data */
4790 if (ahc_dmamem_alloc(ahc
, ahc
->shared_data_dmat
,
4791 (void **)&ahc
->qoutfifo
,
4792 BUS_DMA_NOWAIT
, &ahc
->shared_data_dmamap
) != 0) {
4798 /* And permanently map it in */
4799 ahc_dmamap_load(ahc
, ahc
->shared_data_dmat
, ahc
->shared_data_dmamap
,
4800 ahc
->qoutfifo
, driver_data_size
, ahc_dmamap_cb
,
4801 &ahc
->shared_data_busaddr
, /*flags*/0);
4803 if ((ahc
->features
& AHC_TARGETMODE
) != 0) {
4804 ahc
->targetcmds
= (struct target_cmd
*)ahc
->qoutfifo
;
4805 ahc
->qoutfifo
= (uint8_t *)&ahc
->targetcmds
[AHC_TMODE_CMDS
];
4806 ahc
->dma_bug_buf
= ahc
->shared_data_busaddr
4807 + driver_data_size
- 1;
4808 /* All target command blocks start out invalid. */
4809 for (i
= 0; i
< AHC_TMODE_CMDS
; i
++)
4810 ahc
->targetcmds
[i
].cmd_valid
= 0;
4811 ahc_sync_tqinfifo(ahc
, BUS_DMASYNC_PREREAD
);
4812 ahc
->qoutfifo
= (uint8_t *)&ahc
->targetcmds
[256];
4814 ahc
->qinfifo
= &ahc
->qoutfifo
[256];
4818 /* Allocate SCB data now that buffer_dmat is initialized */
4819 if (ahc
->scb_data
->maxhscbs
== 0)
4820 if (ahc_init_scbdata(ahc
) != 0)
4824 * Allocate a tstate to house information for our
4825 * initiator presence on the bus as well as the user
4826 * data for any target mode initiator.
4828 if (ahc_alloc_tstate(ahc
, ahc
->our_id
, 'A') == NULL
) {
4829 printf("%s: unable to allocate ahc_tmode_tstate. "
4830 "Failing attach\n", ahc_name(ahc
));
4834 if ((ahc
->features
& AHC_TWIN
) != 0) {
4835 if (ahc_alloc_tstate(ahc
, ahc
->our_id_b
, 'B') == NULL
) {
4836 printf("%s: unable to allocate ahc_tmode_tstate. "
4837 "Failing attach\n", ahc_name(ahc
));
4842 if (ahc
->scb_data
->maxhscbs
< AHC_SCB_MAX_ALLOC
) {
4843 ahc
->flags
|= AHC_PAGESCBS
;
4845 ahc
->flags
&= ~AHC_PAGESCBS
;
4849 if (ahc_debug
& AHC_SHOW_MISC
) {
4850 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4851 "ahc_dma %u bytes\n",
4853 (u_int
)sizeof(struct hardware_scb
),
4854 (u_int
)sizeof(struct scb
),
4855 (u_int
)sizeof(struct ahc_dma_seg
));
4857 #endif /* AHC_DEBUG */
4860 * Look at the information that board initialization or
4861 * the board bios has left us.
4863 if (ahc
->features
& AHC_TWIN
) {
4864 scsi_conf
= ahc_inb(ahc
, SCSICONF
+ 1);
4865 if ((scsi_conf
& RESET_SCSI
) != 0
4866 && (ahc
->flags
& AHC_INITIATORROLE
) != 0)
4867 ahc
->flags
|= AHC_RESET_BUS_B
;
4870 scsi_conf
= ahc_inb(ahc
, SCSICONF
);
4871 if ((scsi_conf
& RESET_SCSI
) != 0
4872 && (ahc
->flags
& AHC_INITIATORROLE
) != 0)
4873 ahc
->flags
|= AHC_RESET_BUS_A
;
4876 tagenable
= ALL_TARGETS_MASK
;
4878 /* Grab the disconnection disable table and invert it for our needs */
4879 if ((ahc
->flags
& AHC_USEDEFAULTS
) != 0) {
4880 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4881 "device parameters\n", ahc_name(ahc
));
4882 ahc
->flags
|= AHC_EXTENDED_TRANS_A
|AHC_EXTENDED_TRANS_B
|
4883 AHC_TERM_ENB_A
|AHC_TERM_ENB_B
;
4884 discenable
= ALL_TARGETS_MASK
;
4885 if ((ahc
->features
& AHC_ULTRA
) != 0)
4886 ultraenb
= ALL_TARGETS_MASK
;
4888 discenable
= ~((ahc_inb(ahc
, DISC_DSB
+ 1) << 8)
4889 | ahc_inb(ahc
, DISC_DSB
));
4890 if ((ahc
->features
& (AHC_ULTRA
|AHC_ULTRA2
)) != 0)
4891 ultraenb
= (ahc_inb(ahc
, ULTRA_ENB
+ 1) << 8)
4892 | ahc_inb(ahc
, ULTRA_ENB
);
4895 if ((ahc
->features
& (AHC_WIDE
|AHC_TWIN
)) == 0)
4898 for (i
= 0; i
<= max_targ
; i
++) {
4899 struct ahc_initiator_tinfo
*tinfo
;
4900 struct ahc_tmode_tstate
*tstate
;
4906 our_id
= ahc
->our_id
;
4908 if (i
> 7 && (ahc
->features
& AHC_TWIN
) != 0) {
4910 our_id
= ahc
->our_id_b
;
4913 tinfo
= ahc_fetch_transinfo(ahc
, channel
, our_id
,
4914 target_id
, &tstate
);
4915 /* Default to async narrow across the board */
4916 memset(tinfo
, 0, sizeof(*tinfo
));
4917 if (ahc
->flags
& AHC_USEDEFAULTS
) {
4918 if ((ahc
->features
& AHC_WIDE
) != 0)
4919 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
4922 * These will be truncated when we determine the
4923 * connection type we have with the target.
4925 tinfo
->user
.period
= ahc_syncrates
->period
;
4926 tinfo
->user
.offset
= MAX_OFFSET
;
4931 /* Take the settings leftover in scratch RAM. */
4932 scsirate
= ahc_inb(ahc
, TARG_SCSIRATE
+ i
);
4934 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
4938 if ((scsirate
& SOFS
) == 0x0F) {
4940 * Haven't negotiated yet,
4941 * so the format is different.
4943 scsirate
= (scsirate
& SXFR
) >> 4
4946 | (scsirate
& WIDEXFER
);
4947 offset
= MAX_OFFSET_ULTRA2
;
4949 offset
= ahc_inb(ahc
, TARG_OFFSET
+ i
);
4950 if ((scsirate
& ~WIDEXFER
) == 0 && offset
!= 0)
4951 /* Set to the lowest sync rate, 5MHz */
4953 maxsync
= AHC_SYNCRATE_ULTRA2
;
4954 if ((ahc
->features
& AHC_DT
) != 0)
4955 maxsync
= AHC_SYNCRATE_DT
;
4956 tinfo
->user
.period
=
4957 ahc_find_period(ahc
, scsirate
, maxsync
);
4959 tinfo
->user
.period
= 0;
4961 tinfo
->user
.offset
= MAX_OFFSET
;
4962 if ((scsirate
& SXFR_ULTRA2
) <= 8/*10MHz*/
4963 && (ahc
->features
& AHC_DT
) != 0)
4964 tinfo
->user
.ppr_options
=
4966 } else if ((scsirate
& SOFS
) != 0) {
4967 if ((scsirate
& SXFR
) == 0x40
4968 && (ultraenb
& mask
) != 0) {
4969 /* Treat 10MHz as a non-ultra speed */
4973 tinfo
->user
.period
=
4974 ahc_find_period(ahc
, scsirate
,
4976 ? AHC_SYNCRATE_ULTRA
4977 : AHC_SYNCRATE_FAST
);
4978 if (tinfo
->user
.period
!= 0)
4979 tinfo
->user
.offset
= MAX_OFFSET
;
4981 if (tinfo
->user
.period
== 0)
4982 tinfo
->user
.offset
= 0;
4983 if ((scsirate
& WIDEXFER
) != 0
4984 && (ahc
->features
& AHC_WIDE
) != 0)
4985 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
4986 tinfo
->user
.protocol_version
= 4;
4987 if ((ahc
->features
& AHC_DT
) != 0)
4988 tinfo
->user
.transport_version
= 3;
4990 tinfo
->user
.transport_version
= 2;
4991 tinfo
->goal
.protocol_version
= 2;
4992 tinfo
->goal
.transport_version
= 2;
4993 tinfo
->curr
.protocol_version
= 2;
4994 tinfo
->curr
.transport_version
= 2;
4996 tstate
->ultraenb
= 0;
4998 ahc
->user_discenable
= discenable
;
4999 ahc
->user_tagenable
= tagenable
;
5001 return (ahc
->bus_chip_init(ahc
));
5005 ahc_intr_enable(struct ahc_softc
*ahc
, int enable
)
5009 hcntrl
= ahc_inb(ahc
, HCNTRL
);
5011 ahc
->pause
&= ~INTEN
;
5012 ahc
->unpause
&= ~INTEN
;
5015 ahc
->pause
|= INTEN
;
5016 ahc
->unpause
|= INTEN
;
5018 ahc_outb(ahc
, HCNTRL
, hcntrl
);
5022 * Ensure that the card is paused in a location
5023 * outside of all critical sections and that all
5024 * pending work is completed prior to returning.
5025 * This routine should only be called from outside
5026 * an interrupt context.
5029 ahc_pause_and_flushwork(struct ahc_softc
*ahc
)
5036 ahc
->flags
|= AHC_ALL_INTERRUPTS
;
5044 ahc_outb(ahc
, SCSISEQ
, ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
);
5045 ahc_clear_critical_section(ahc
);
5046 intstat
= ahc_inb(ahc
, INTSTAT
);
5048 && (intstat
!= 0xFF || (ahc
->features
& AHC_REMOVABLE
) == 0)
5049 && ((intstat
& INT_PEND
) != 0
5050 || (ahc_inb(ahc
, SSTAT0
) & (SELDO
|SELINGO
)) != 0));
5051 if (maxloops
== 0) {
5052 printf("Infinite interrupt loop, INTSTAT = %x",
5053 ahc_inb(ahc
, INTSTAT
));
5055 ahc_platform_flushwork(ahc
);
5056 ahc
->flags
&= ~AHC_ALL_INTERRUPTS
;
5060 ahc_suspend(struct ahc_softc
*ahc
)
5063 ahc_pause_and_flushwork(ahc
);
5065 if (LIST_FIRST(&ahc
->pending_scbs
) != NULL
) {
5070 #ifdef AHC_TARGET_MODE
5072 * XXX What about ATIOs that have not yet been serviced?
5073 * Perhaps we should just refuse to be suspended if we
5074 * are acting in a target role.
5076 if (ahc
->pending_device
!= NULL
) {
5086 ahc_resume(struct ahc_softc
*ahc
)
5089 ahc_reset(ahc
, /*reinit*/TRUE
);
5090 ahc_intr_enable(ahc
, TRUE
);
5095 /************************** Busy Target Table *********************************/
5097 * Return the untagged transaction id for a given target/channel lun.
5098 * Optionally, clear the entry.
5101 ahc_index_busy_tcl(struct ahc_softc
*ahc
, u_int tcl
)
5104 u_int target_offset
;
5106 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5109 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5110 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5111 scbid
= ahc_inb(ahc
, SCB_64_BTT
+ TCL_TARGET_OFFSET(tcl
));
5112 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5114 target_offset
= TCL_TARGET_OFFSET(tcl
);
5115 scbid
= ahc_inb(ahc
, BUSY_TARGETS
+ target_offset
);
5122 ahc_unbusy_tcl(struct ahc_softc
*ahc
, u_int tcl
)
5124 u_int target_offset
;
5126 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5129 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5130 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5131 ahc_outb(ahc
, SCB_64_BTT
+TCL_TARGET_OFFSET(tcl
), SCB_LIST_NULL
);
5132 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5134 target_offset
= TCL_TARGET_OFFSET(tcl
);
5135 ahc_outb(ahc
, BUSY_TARGETS
+ target_offset
, SCB_LIST_NULL
);
5140 ahc_busy_tcl(struct ahc_softc
*ahc
, u_int tcl
, u_int scbid
)
5142 u_int target_offset
;
5144 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5147 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5148 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5149 ahc_outb(ahc
, SCB_64_BTT
+ TCL_TARGET_OFFSET(tcl
), scbid
);
5150 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5152 target_offset
= TCL_TARGET_OFFSET(tcl
);
5153 ahc_outb(ahc
, BUSY_TARGETS
+ target_offset
, scbid
);
5157 /************************** SCB and SCB queue management **********************/
5159 ahc_match_scb(struct ahc_softc
*ahc
, struct scb
*scb
, int target
,
5160 char channel
, int lun
, u_int tag
, role_t role
)
5162 int targ
= SCB_GET_TARGET(ahc
, scb
);
5163 char chan
= SCB_GET_CHANNEL(ahc
, scb
);
5164 int slun
= SCB_GET_LUN(scb
);
5167 match
= ((chan
== channel
) || (channel
== ALL_CHANNELS
));
5169 match
= ((targ
== target
) || (target
== CAM_TARGET_WILDCARD
));
5171 match
= ((lun
== slun
) || (lun
== CAM_LUN_WILDCARD
));
5173 #ifdef AHC_TARGET_MODE
5176 group
= XPT_FC_GROUP(scb
->io_ctx
->ccb_h
.func_code
);
5177 if (role
== ROLE_INITIATOR
) {
5178 match
= (group
!= XPT_FC_GROUP_TMODE
)
5179 && ((tag
== scb
->hscb
->tag
)
5180 || (tag
== SCB_LIST_NULL
));
5181 } else if (role
== ROLE_TARGET
) {
5182 match
= (group
== XPT_FC_GROUP_TMODE
)
5183 && ((tag
== scb
->io_ctx
->csio
.tag_id
)
5184 || (tag
== SCB_LIST_NULL
));
5186 #else /* !AHC_TARGET_MODE */
5187 match
= ((tag
== scb
->hscb
->tag
) || (tag
== SCB_LIST_NULL
));
5188 #endif /* AHC_TARGET_MODE */
5195 ahc_freeze_devq(struct ahc_softc
*ahc
, struct scb
*scb
)
5201 target
= SCB_GET_TARGET(ahc
, scb
);
5202 lun
= SCB_GET_LUN(scb
);
5203 channel
= SCB_GET_CHANNEL(ahc
, scb
);
5205 ahc_search_qinfifo(ahc
, target
, channel
, lun
,
5206 /*tag*/SCB_LIST_NULL
, ROLE_UNKNOWN
,
5207 CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
5209 ahc_platform_freeze_devq(ahc
, scb
);
5213 ahc_qinfifo_requeue_tail(struct ahc_softc
*ahc
, struct scb
*scb
)
5215 struct scb
*prev_scb
;
5218 if (ahc_qinfifo_count(ahc
) != 0) {
5222 prev_pos
= ahc
->qinfifonext
- 1;
5223 prev_tag
= ahc
->qinfifo
[prev_pos
];
5224 prev_scb
= ahc_lookup_scb(ahc
, prev_tag
);
5226 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5227 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5228 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
5230 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
5235 ahc_qinfifo_requeue(struct ahc_softc
*ahc
, struct scb
*prev_scb
,
5238 if (prev_scb
== NULL
) {
5239 ahc_outb(ahc
, NEXT_QUEUED_SCB
, scb
->hscb
->tag
);
5241 prev_scb
->hscb
->next
= scb
->hscb
->tag
;
5242 ahc_sync_scb(ahc
, prev_scb
,
5243 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
5245 ahc
->qinfifo
[ahc
->qinfifonext
++] = scb
->hscb
->tag
;
5246 scb
->hscb
->next
= ahc
->next_queued_scb
->hscb
->tag
;
5247 ahc_sync_scb(ahc
, scb
, BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
5251 ahc_qinfifo_count(struct ahc_softc
*ahc
)
5256 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5257 qinpos
= ahc_inb(ahc
, SNSCB_QOFF
);
5258 ahc_outb(ahc
, SNSCB_QOFF
, qinpos
);
5260 qinpos
= ahc_inb(ahc
, QINPOS
);
5261 diff
= ahc
->qinfifonext
- qinpos
;
5266 ahc_search_qinfifo(struct ahc_softc
*ahc
, int target
, char channel
,
5267 int lun
, u_int tag
, role_t role
, uint32_t status
,
5268 ahc_search_action action
)
5271 struct scb
*prev_scb
;
5281 qintail
= ahc
->qinfifonext
;
5282 have_qregs
= (ahc
->features
& AHC_QUEUE_REGS
) != 0;
5284 qinstart
= ahc_inb(ahc
, SNSCB_QOFF
);
5285 ahc_outb(ahc
, SNSCB_QOFF
, qinstart
);
5287 qinstart
= ahc_inb(ahc
, QINPOS
);
5292 if (action
== SEARCH_COMPLETE
) {
5294 * Don't attempt to run any queued untagged transactions
5295 * until we are done with the abort process.
5297 ahc_freeze_untagged_queues(ahc
);
5301 * Start with an empty queue. Entries that are not chosen
5302 * for removal will be re-added to the queue as we go.
5304 ahc
->qinfifonext
= qinpos
;
5305 ahc_outb(ahc
, NEXT_QUEUED_SCB
, ahc
->next_queued_scb
->hscb
->tag
);
5307 while (qinpos
!= qintail
) {
5308 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qinpos
]);
5310 printf("qinpos = %d, SCB index = %d\n",
5311 qinpos
, ahc
->qinfifo
[qinpos
]);
5315 if (ahc_match_scb(ahc
, scb
, target
, channel
, lun
, tag
, role
)) {
5317 * We found an scb that needs to be acted on.
5321 case SEARCH_COMPLETE
:
5326 ostat
= ahc_get_transaction_status(scb
);
5327 if (ostat
== CAM_REQ_INPROG
)
5328 ahc_set_transaction_status(scb
, status
);
5329 cstat
= ahc_get_transaction_status(scb
);
5330 if (cstat
!= CAM_REQ_CMP
)
5331 ahc_freeze_scb(scb
);
5332 if ((scb
->flags
& SCB_ACTIVE
) == 0)
5333 printf("Inactive SCB in qinfifo\n");
5341 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5346 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5352 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5353 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
5355 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
5358 if (action
!= SEARCH_COUNT
5360 && (qinstart
!= ahc
->qinfifonext
)) {
5362 * The sequencer may be in the process of dmaing
5363 * down the SCB at the beginning of the queue.
5364 * This could be problematic if either the first,
5365 * or the second SCB is removed from the queue
5366 * (the first SCB includes a pointer to the "next"
5367 * SCB to dma). If we have removed any entries, swap
5368 * the first element in the queue with the next HSCB
5369 * so the sequencer will notice that NEXT_QUEUED_SCB
5370 * has changed during its dma attempt and will retry
5373 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qinstart
]);
5376 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5377 found
, qinstart
, ahc
->qinfifonext
);
5378 panic("First/Second Qinfifo fixup\n");
5381 * ahc_swap_with_next_hscb forces our next pointer to
5382 * point to the reserved SCB for future commands. Save
5383 * and restore our original next pointer to maintain
5386 next
= scb
->hscb
->next
;
5387 ahc
->scb_data
->scbindex
[scb
->hscb
->tag
] = NULL
;
5388 ahc_swap_with_next_hscb(ahc
, scb
);
5389 scb
->hscb
->next
= next
;
5390 ahc
->qinfifo
[qinstart
] = scb
->hscb
->tag
;
5392 /* Tell the card about the new head of the qinfifo. */
5393 ahc_outb(ahc
, NEXT_QUEUED_SCB
, scb
->hscb
->tag
);
5395 /* Fixup the tail "next" pointer. */
5396 qintail
= ahc
->qinfifonext
- 1;
5397 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qintail
]);
5398 scb
->hscb
->next
= ahc
->next_queued_scb
->hscb
->tag
;
5402 * Search waiting for selection list.
5404 curscbptr
= ahc_inb(ahc
, SCBPTR
);
5405 next
= ahc_inb(ahc
, WAITING_SCBH
); /* Start at head of list. */
5406 prev
= SCB_LIST_NULL
;
5408 while (next
!= SCB_LIST_NULL
) {
5411 ahc_outb(ahc
, SCBPTR
, next
);
5412 scb_index
= ahc_inb(ahc
, SCB_TAG
);
5413 if (scb_index
>= ahc
->scb_data
->numscbs
) {
5414 printf("Waiting List inconsistency. "
5415 "SCB index == %d, yet numscbs == %d.",
5416 scb_index
, ahc
->scb_data
->numscbs
);
5417 ahc_dump_card_state(ahc
);
5418 panic("for safety");
5420 scb
= ahc_lookup_scb(ahc
, scb_index
);
5422 printf("scb_index = %d, next = %d\n",
5424 panic("Waiting List traversal\n");
5426 if (ahc_match_scb(ahc
, scb
, target
, channel
,
5427 lun
, SCB_LIST_NULL
, role
)) {
5429 * We found an scb that needs to be acted on.
5433 case SEARCH_COMPLETE
:
5438 ostat
= ahc_get_transaction_status(scb
);
5439 if (ostat
== CAM_REQ_INPROG
)
5440 ahc_set_transaction_status(scb
,
5442 cstat
= ahc_get_transaction_status(scb
);
5443 if (cstat
!= CAM_REQ_CMP
)
5444 ahc_freeze_scb(scb
);
5445 if ((scb
->flags
& SCB_ACTIVE
) == 0)
5446 printf("Inactive SCB in Waiting List\n");
5451 next
= ahc_rem_wscb(ahc
, next
, prev
);
5455 next
= ahc_inb(ahc
, SCB_NEXT
);
5461 next
= ahc_inb(ahc
, SCB_NEXT
);
5464 ahc_outb(ahc
, SCBPTR
, curscbptr
);
5466 found
+= ahc_search_untagged_queues(ahc
, /*ahc_io_ctx_t*/NULL
, target
,
5467 channel
, lun
, status
, action
);
5469 if (action
== SEARCH_COMPLETE
)
5470 ahc_release_untagged_queues(ahc
);
5475 ahc_search_untagged_queues(struct ahc_softc
*ahc
, ahc_io_ctx_t ctx
,
5476 int target
, char channel
, int lun
, uint32_t status
,
5477 ahc_search_action action
)
5484 if (action
== SEARCH_COMPLETE
) {
5486 * Don't attempt to run any queued untagged transactions
5487 * until we are done with the abort process.
5489 ahc_freeze_untagged_queues(ahc
);
5494 if ((ahc
->flags
& AHC_SCB_BTT
) == 0) {
5497 if (target
!= CAM_TARGET_WILDCARD
) {
5508 for (; i
< maxtarget
; i
++) {
5509 struct scb_tailq
*untagged_q
;
5510 struct scb
*next_scb
;
5512 untagged_q
= &(ahc
->untagged_queues
[i
]);
5513 next_scb
= TAILQ_FIRST(untagged_q
);
5514 while (next_scb
!= NULL
) {
5517 next_scb
= TAILQ_NEXT(scb
, links
.tqe
);
5520 * The head of the list may be the currently
5521 * active untagged command for a device.
5522 * We're only searching for commands that
5523 * have not been started. A transaction
5524 * marked active but still in the qinfifo
5525 * is removed by the qinfifo scanning code
5528 if ((scb
->flags
& SCB_ACTIVE
) != 0)
5531 if (ahc_match_scb(ahc
, scb
, target
, channel
, lun
,
5532 SCB_LIST_NULL
, ROLE_INITIATOR
) == 0
5533 || (ctx
!= NULL
&& ctx
!= scb
->io_ctx
))
5537 * We found an scb that needs to be acted on.
5541 case SEARCH_COMPLETE
:
5546 ostat
= ahc_get_transaction_status(scb
);
5547 if (ostat
== CAM_REQ_INPROG
)
5548 ahc_set_transaction_status(scb
, status
);
5549 cstat
= ahc_get_transaction_status(scb
);
5550 if (cstat
!= CAM_REQ_CMP
)
5551 ahc_freeze_scb(scb
);
5552 if ((scb
->flags
& SCB_ACTIVE
) == 0)
5553 printf("Inactive SCB in untaggedQ\n");
5558 scb
->flags
&= ~SCB_UNTAGGEDQ
;
5559 TAILQ_REMOVE(untagged_q
, scb
, links
.tqe
);
5567 if (action
== SEARCH_COMPLETE
)
5568 ahc_release_untagged_queues(ahc
);
5573 ahc_search_disc_list(struct ahc_softc
*ahc
, int target
, char channel
,
5574 int lun
, u_int tag
, int stop_on_first
, int remove
,
5584 next
= ahc_inb(ahc
, DISCONNECTED_SCBH
);
5585 prev
= SCB_LIST_NULL
;
5588 /* restore this when we're done */
5589 active_scb
= ahc_inb(ahc
, SCBPTR
);
5591 /* Silence compiler */
5592 active_scb
= SCB_LIST_NULL
;
5594 while (next
!= SCB_LIST_NULL
) {
5597 ahc_outb(ahc
, SCBPTR
, next
);
5598 scb_index
= ahc_inb(ahc
, SCB_TAG
);
5599 if (scb_index
>= ahc
->scb_data
->numscbs
) {
5600 printf("Disconnected List inconsistency. "
5601 "SCB index == %d, yet numscbs == %d.",
5602 scb_index
, ahc
->scb_data
->numscbs
);
5603 ahc_dump_card_state(ahc
);
5604 panic("for safety");
5608 panic("Disconnected List Loop. "
5609 "cur SCBPTR == %x, prev SCBPTR == %x.",
5612 scbp
= ahc_lookup_scb(ahc
, scb_index
);
5613 if (ahc_match_scb(ahc
, scbp
, target
, channel
, lun
,
5614 tag
, ROLE_INITIATOR
)) {
5618 ahc_rem_scb_from_disc_list(ahc
, prev
, next
);
5621 next
= ahc_inb(ahc
, SCB_NEXT
);
5627 next
= ahc_inb(ahc
, SCB_NEXT
);
5631 ahc_outb(ahc
, SCBPTR
, active_scb
);
5636 * Remove an SCB from the on chip list of disconnected transactions.
5637 * This is empty/unused if we are not performing SCB paging.
5640 ahc_rem_scb_from_disc_list(struct ahc_softc
*ahc
, u_int prev
, u_int scbptr
)
5644 ahc_outb(ahc
, SCBPTR
, scbptr
);
5645 next
= ahc_inb(ahc
, SCB_NEXT
);
5647 ahc_outb(ahc
, SCB_CONTROL
, 0);
5649 ahc_add_curscb_to_free_list(ahc
);
5651 if (prev
!= SCB_LIST_NULL
) {
5652 ahc_outb(ahc
, SCBPTR
, prev
);
5653 ahc_outb(ahc
, SCB_NEXT
, next
);
5655 ahc_outb(ahc
, DISCONNECTED_SCBH
, next
);
5661 * Add the SCB as selected by SCBPTR onto the on chip list of
5662 * free hardware SCBs. This list is empty/unused if we are not
5663 * performing SCB paging.
5666 ahc_add_curscb_to_free_list(struct ahc_softc
*ahc
)
5669 * Invalidate the tag so that our abort
5670 * routines don't think it's active.
5672 ahc_outb(ahc
, SCB_TAG
, SCB_LIST_NULL
);
5674 if ((ahc
->flags
& AHC_PAGESCBS
) != 0) {
5675 ahc_outb(ahc
, SCB_NEXT
, ahc_inb(ahc
, FREE_SCBH
));
5676 ahc_outb(ahc
, FREE_SCBH
, ahc_inb(ahc
, SCBPTR
));
5681 * Manipulate the waiting for selection list and return the
5682 * scb that follows the one that we remove.
5685 ahc_rem_wscb(struct ahc_softc
*ahc
, u_int scbpos
, u_int prev
)
5690 * Select the SCB we want to abort and
5691 * pull the next pointer out of it.
5693 curscb
= ahc_inb(ahc
, SCBPTR
);
5694 ahc_outb(ahc
, SCBPTR
, scbpos
);
5695 next
= ahc_inb(ahc
, SCB_NEXT
);
5697 /* Clear the necessary fields */
5698 ahc_outb(ahc
, SCB_CONTROL
, 0);
5700 ahc_add_curscb_to_free_list(ahc
);
5702 /* update the waiting list */
5703 if (prev
== SCB_LIST_NULL
) {
5704 /* First in the list */
5705 ahc_outb(ahc
, WAITING_SCBH
, next
);
5708 * Ensure we aren't attempting to perform
5709 * selection for this entry.
5711 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
5714 * Select the scb that pointed to us
5715 * and update its next pointer.
5717 ahc_outb(ahc
, SCBPTR
, prev
);
5718 ahc_outb(ahc
, SCB_NEXT
, next
);
5722 * Point us back at the original scb position.
5724 ahc_outb(ahc
, SCBPTR
, curscb
);
5728 /******************************** Error Handling ******************************/
5730 * Abort all SCBs that match the given description (target/channel/lun/tag),
5731 * setting their status to the passed in status if the status has not already
5732 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5733 * is paused before it is called.
5736 ahc_abort_scbs(struct ahc_softc
*ahc
, int target
, char channel
,
5737 int lun
, u_int tag
, role_t role
, uint32_t status
)
5740 struct scb
*scbp_next
;
5750 * Don't attempt to run any queued untagged transactions
5751 * until we are done with the abort process.
5753 ahc_freeze_untagged_queues(ahc
);
5755 /* restore this when we're done */
5756 active_scb
= ahc_inb(ahc
, SCBPTR
);
5758 found
= ahc_search_qinfifo(ahc
, target
, channel
, lun
, SCB_LIST_NULL
,
5759 role
, CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
5762 * Clean out the busy target table for any untagged commands.
5766 if (target
!= CAM_TARGET_WILDCARD
) {
5773 if (lun
== CAM_LUN_WILDCARD
) {
5776 * Unless we are using an SCB based
5777 * busy targets table, there is only
5778 * one table entry for all luns of
5783 if ((ahc
->flags
& AHC_SCB_BTT
) != 0)
5784 maxlun
= AHC_NUM_LUNS
;
5790 if (role
!= ROLE_TARGET
) {
5791 for (;i
< maxtarget
; i
++) {
5792 for (j
= minlun
;j
< maxlun
; j
++) {
5796 tcl
= BUILD_TCL(i
<< 4, j
);
5797 scbid
= ahc_index_busy_tcl(ahc
, tcl
);
5798 scbp
= ahc_lookup_scb(ahc
, scbid
);
5800 || ahc_match_scb(ahc
, scbp
, target
, channel
,
5801 lun
, tag
, role
) == 0)
5803 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, j
));
5808 * Go through the disconnected list and remove any entries we
5809 * have queued for completion, 0'ing their control byte too.
5810 * We save the active SCB and restore it ourselves, so there
5811 * is no reason for this search to restore it too.
5813 ahc_search_disc_list(ahc
, target
, channel
, lun
, tag
,
5814 /*stop_on_first*/FALSE
, /*remove*/TRUE
,
5815 /*save_state*/FALSE
);
5819 * Go through the hardware SCB array looking for commands that
5820 * were active but not on any list. In some cases, these remnants
5821 * might not still have mappings in the scbindex array (e.g. unexpected
5822 * bus free with the same scb queued for an abort). Don't hold this
5825 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
5828 ahc_outb(ahc
, SCBPTR
, i
);
5829 scbid
= ahc_inb(ahc
, SCB_TAG
);
5830 scbp
= ahc_lookup_scb(ahc
, scbid
);
5831 if ((scbp
== NULL
&& scbid
!= SCB_LIST_NULL
)
5833 && ahc_match_scb(ahc
, scbp
, target
, channel
, lun
, tag
, role
)))
5834 ahc_add_curscb_to_free_list(ahc
);
5838 * Go through the pending CCB list and look for
5839 * commands for this target that are still active.
5840 * These are other tagged commands that were
5841 * disconnected when the reset occurred.
5843 scbp_next
= LIST_FIRST(&ahc
->pending_scbs
);
5844 while (scbp_next
!= NULL
) {
5846 scbp_next
= LIST_NEXT(scbp
, pending_links
);
5847 if (ahc_match_scb(ahc
, scbp
, target
, channel
, lun
, tag
, role
)) {
5850 ostat
= ahc_get_transaction_status(scbp
);
5851 if (ostat
== CAM_REQ_INPROG
)
5852 ahc_set_transaction_status(scbp
, status
);
5853 if (ahc_get_transaction_status(scbp
) != CAM_REQ_CMP
)
5854 ahc_freeze_scb(scbp
);
5855 if ((scbp
->flags
& SCB_ACTIVE
) == 0)
5856 printf("Inactive SCB on pending list\n");
5857 ahc_done(ahc
, scbp
);
5861 ahc_outb(ahc
, SCBPTR
, active_scb
);
5862 ahc_platform_abort_scbs(ahc
, target
, channel
, lun
, tag
, role
, status
);
5863 ahc_release_untagged_queues(ahc
);
5868 ahc_reset_current_bus(struct ahc_softc
*ahc
)
5872 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENSCSIRST
);
5873 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
5874 ahc_outb(ahc
, SCSISEQ
, scsiseq
| SCSIRSTO
);
5875 ahc_flush_device_writes(ahc
);
5876 ahc_delay(AHC_BUSRESET_DELAY
);
5877 /* Turn off the bus reset */
5878 ahc_outb(ahc
, SCSISEQ
, scsiseq
& ~SCSIRSTO
);
5880 ahc_clear_intstat(ahc
);
5882 /* Re-enable reset interrupts */
5883 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) | ENSCSIRST
);
5887 ahc_reset_channel(struct ahc_softc
*ahc
, char channel
, int initiate_reset
)
5889 struct ahc_devinfo devinfo
;
5890 u_int initiator
, target
, max_scsiid
;
5898 ahc
->pending_device
= NULL
;
5900 ahc_compile_devinfo(&devinfo
,
5901 CAM_TARGET_WILDCARD
,
5902 CAM_TARGET_WILDCARD
,
5904 channel
, ROLE_UNKNOWN
);
5907 /* Make sure the sequencer is in a safe location. */
5908 ahc_clear_critical_section(ahc
);
5911 * Run our command complete fifos to ensure that we perform
5912 * completion processing on any commands that 'completed'
5913 * before the reset occurred.
5915 ahc_run_qoutfifo(ahc
);
5916 #ifdef AHC_TARGET_MODE
5918 * XXX - In Twin mode, the tqinfifo may have commands
5919 * for an unaffected channel in it. However, if
5920 * we have run out of ATIO resources to drain that
5921 * queue, we may not get them all out here. Further,
5922 * the blocked transactions for the reset channel
5923 * should just be killed off, irrespecitve of whether
5924 * we are blocked on ATIO resources. Write a routine
5925 * to compact the tqinfifo appropriately.
5927 if ((ahc
->flags
& AHC_TARGETROLE
) != 0) {
5928 ahc_run_tqinfifo(ahc
, /*paused*/TRUE
);
5933 * Reset the bus if we are initiating this reset
5935 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
5937 if ((ahc
->features
& AHC_TWIN
) != 0
5938 && ((sblkctl
& SELBUSB
) != 0))
5940 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
5941 if (cur_channel
!= channel
) {
5942 /* Case 1: Command for another bus is active
5943 * Stealthily reset the other bus without
5944 * upsetting the current bus.
5946 ahc_outb(ahc
, SBLKCTL
, sblkctl
^ SELBUSB
);
5947 simode1
= ahc_inb(ahc
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
);
5948 #ifdef AHC_TARGET_MODE
5950 * Bus resets clear ENSELI, so we cannot
5951 * defer re-enabling bus reset interrupts
5952 * if we are in target mode.
5954 if ((ahc
->flags
& AHC_TARGETROLE
) != 0)
5955 simode1
|= ENSCSIRST
;
5957 ahc_outb(ahc
, SIMODE1
, simode1
);
5959 ahc_reset_current_bus(ahc
);
5960 ahc_clear_intstat(ahc
);
5961 ahc_outb(ahc
, SCSISEQ
, scsiseq
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
5962 ahc_outb(ahc
, SBLKCTL
, sblkctl
);
5963 restart_needed
= FALSE
;
5965 /* Case 2: A command from this bus is active or we're idle */
5966 simode1
= ahc_inb(ahc
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
);
5967 #ifdef AHC_TARGET_MODE
5969 * Bus resets clear ENSELI, so we cannot
5970 * defer re-enabling bus reset interrupts
5971 * if we are in target mode.
5973 if ((ahc
->flags
& AHC_TARGETROLE
) != 0)
5974 simode1
|= ENSCSIRST
;
5976 ahc_outb(ahc
, SIMODE1
, simode1
);
5978 ahc_reset_current_bus(ahc
);
5979 ahc_clear_intstat(ahc
);
5980 ahc_outb(ahc
, SCSISEQ
, scsiseq
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
5981 restart_needed
= TRUE
;
5985 * Clean up all the state information for the
5986 * pending transactions on this bus.
5988 found
= ahc_abort_scbs(ahc
, CAM_TARGET_WILDCARD
, channel
,
5989 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
5990 ROLE_UNKNOWN
, CAM_SCSI_BUS_RESET
);
5992 max_scsiid
= (ahc
->features
& AHC_WIDE
) ? 15 : 7;
5994 #ifdef AHC_TARGET_MODE
5996 * Send an immediate notify ccb to all target more peripheral
5997 * drivers affected by this action.
5999 for (target
= 0; target
<= max_scsiid
; target
++) {
6000 struct ahc_tmode_tstate
* tstate
;
6003 tstate
= ahc
->enabled_targets
[target
];
6006 for (lun
= 0; lun
< AHC_NUM_LUNS
; lun
++) {
6007 struct ahc_tmode_lstate
* lstate
;
6009 lstate
= tstate
->enabled_luns
[lun
];
6013 ahc_queue_lstate_event(ahc
, lstate
, CAM_TARGET_WILDCARD
,
6014 EVENT_TYPE_BUS_RESET
, /*arg*/0);
6015 ahc_send_lstate_events(ahc
, lstate
);
6019 /* Notify the XPT that a bus reset occurred */
6020 ahc_send_async(ahc
, devinfo
.channel
, CAM_TARGET_WILDCARD
,
6021 CAM_LUN_WILDCARD
, AC_BUS_RESET
, NULL
);
6024 * Revert to async/narrow transfers until we renegotiate.
6026 for (target
= 0; target
<= max_scsiid
; target
++) {
6028 if (ahc
->enabled_targets
[target
] == NULL
)
6030 for (initiator
= 0; initiator
<= max_scsiid
; initiator
++) {
6031 struct ahc_devinfo devinfo
;
6033 ahc_compile_devinfo(&devinfo
, target
, initiator
,
6035 channel
, ROLE_UNKNOWN
);
6036 ahc_set_width(ahc
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6037 AHC_TRANS_CUR
, /*paused*/TRUE
);
6038 ahc_set_syncrate(ahc
, &devinfo
, /*syncrate*/NULL
,
6039 /*period*/0, /*offset*/0,
6040 /*ppr_options*/0, AHC_TRANS_CUR
,
6053 /***************************** Residual Processing ****************************/
6055 * Calculate the residual for a just completed SCB.
6058 ahc_calc_residual(struct ahc_softc
*ahc
, struct scb
*scb
)
6060 struct hardware_scb
*hscb
;
6061 struct status_pkt
*spkt
;
6063 uint32_t resid_sgptr
;
6069 * SG_RESID_VALID clear in sgptr.
6070 * 2) Transferless command
6071 * 3) Never performed any transfers.
6072 * sgptr has SG_FULL_RESID set.
6073 * 4) No residual but target did not
6074 * save data pointers after the
6075 * last transfer, so sgptr was
6077 * 5) We have a partial residual.
6078 * Use residual_sgptr to determine
6083 sgptr
= ahc_le32toh(hscb
->sgptr
);
6084 if ((sgptr
& SG_RESID_VALID
) == 0)
6087 sgptr
&= ~SG_RESID_VALID
;
6089 if ((sgptr
& SG_LIST_NULL
) != 0)
6093 spkt
= &hscb
->shared_data
.status
;
6094 resid_sgptr
= ahc_le32toh(spkt
->residual_sg_ptr
);
6095 if ((sgptr
& SG_FULL_RESID
) != 0) {
6097 resid
= ahc_get_transfer_length(scb
);
6098 } else if ((resid_sgptr
& SG_LIST_NULL
) != 0) {
6101 } else if ((resid_sgptr
& ~SG_PTR_MASK
) != 0) {
6102 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr
);
6104 struct ahc_dma_seg
*sg
;
6107 * Remainder of the SG where the transfer
6110 resid
= ahc_le32toh(spkt
->residual_datacnt
) & AHC_SG_LEN_MASK
;
6111 sg
= ahc_sg_bus_to_virt(scb
, resid_sgptr
& SG_PTR_MASK
);
6113 /* The residual sg_ptr always points to the next sg */
6117 * Add up the contents of all residual
6118 * SG segments that are after the SG where
6119 * the transfer stopped.
6121 while ((ahc_le32toh(sg
->len
) & AHC_DMA_LAST_SEG
) == 0) {
6123 resid
+= ahc_le32toh(sg
->len
) & AHC_SG_LEN_MASK
;
6126 if ((scb
->flags
& SCB_SENSE
) == 0)
6127 ahc_set_residual(scb
, resid
);
6129 ahc_set_sense_residual(scb
, resid
);
6132 if ((ahc_debug
& AHC_SHOW_MISC
) != 0) {
6133 ahc_print_path(ahc
, scb
);
6134 printf("Handled %sResidual of %d bytes\n",
6135 (scb
->flags
& SCB_SENSE
) ? "Sense " : "", resid
);
6140 /******************************* Target Mode **********************************/
6141 #ifdef AHC_TARGET_MODE
6143 * Add a target mode event to this lun's queue
6146 ahc_queue_lstate_event(struct ahc_softc
*ahc
, struct ahc_tmode_lstate
*lstate
,
6147 u_int initiator_id
, u_int event_type
, u_int event_arg
)
6149 struct ahc_tmode_event
*event
;
6152 xpt_freeze_devq(lstate
->path
, /*count*/1);
6153 if (lstate
->event_w_idx
>= lstate
->event_r_idx
)
6154 pending
= lstate
->event_w_idx
- lstate
->event_r_idx
;
6156 pending
= AHC_TMODE_EVENT_BUFFER_SIZE
+ 1
6157 - (lstate
->event_r_idx
- lstate
->event_w_idx
);
6159 if (event_type
== EVENT_TYPE_BUS_RESET
6160 || event_type
== MSG_BUS_DEV_RESET
) {
6162 * Any earlier events are irrelevant, so reset our buffer.
6163 * This has the effect of allowing us to deal with reset
6164 * floods (an external device holding down the reset line)
6165 * without losing the event that is really interesting.
6167 lstate
->event_r_idx
= 0;
6168 lstate
->event_w_idx
= 0;
6169 xpt_release_devq(lstate
->path
, pending
, /*runqueue*/FALSE
);
6172 if (pending
== AHC_TMODE_EVENT_BUFFER_SIZE
) {
6173 xpt_print_path(lstate
->path
);
6174 printf("immediate event %x:%x lost\n",
6175 lstate
->event_buffer
[lstate
->event_r_idx
].event_type
,
6176 lstate
->event_buffer
[lstate
->event_r_idx
].event_arg
);
6177 lstate
->event_r_idx
++;
6178 if (lstate
->event_r_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6179 lstate
->event_r_idx
= 0;
6180 xpt_release_devq(lstate
->path
, /*count*/1, /*runqueue*/FALSE
);
6183 event
= &lstate
->event_buffer
[lstate
->event_w_idx
];
6184 event
->initiator_id
= initiator_id
;
6185 event
->event_type
= event_type
;
6186 event
->event_arg
= event_arg
;
6187 lstate
->event_w_idx
++;
6188 if (lstate
->event_w_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6189 lstate
->event_w_idx
= 0;
6193 * Send any target mode events queued up waiting
6194 * for immediate notify resources.
6197 ahc_send_lstate_events(struct ahc_softc
*ahc
, struct ahc_tmode_lstate
*lstate
)
6199 struct ccb_hdr
*ccbh
;
6200 struct ccb_immed_notify
*inot
;
6202 while (lstate
->event_r_idx
!= lstate
->event_w_idx
6203 && (ccbh
= SLIST_FIRST(&lstate
->immed_notifies
)) != NULL
) {
6204 struct ahc_tmode_event
*event
;
6206 event
= &lstate
->event_buffer
[lstate
->event_r_idx
];
6207 SLIST_REMOVE_HEAD(&lstate
->immed_notifies
, sim_links
.sle
);
6208 inot
= (struct ccb_immed_notify
*)ccbh
;
6209 switch (event
->event_type
) {
6210 case EVENT_TYPE_BUS_RESET
:
6211 ccbh
->status
= CAM_SCSI_BUS_RESET
|CAM_DEV_QFRZN
;
6214 ccbh
->status
= CAM_MESSAGE_RECV
|CAM_DEV_QFRZN
;
6215 inot
->message_args
[0] = event
->event_type
;
6216 inot
->message_args
[1] = event
->event_arg
;
6219 inot
->initiator_id
= event
->initiator_id
;
6220 inot
->sense_len
= 0;
6221 xpt_done((union ccb
*)inot
);
6222 lstate
->event_r_idx
++;
6223 if (lstate
->event_r_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6224 lstate
->event_r_idx
= 0;
6229 /******************** Sequencer Program Patching/Download *********************/
6233 ahc_dumpseq(struct ahc_softc
* ahc
)
6237 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
6238 ahc_outb(ahc
, SEQADDR0
, 0);
6239 ahc_outb(ahc
, SEQADDR1
, 0);
6240 for (i
= 0; i
< ahc
->instruction_ram_size
; i
++) {
6241 uint8_t ins_bytes
[4];
6243 ahc_insb(ahc
, SEQRAM
, ins_bytes
, 4);
6244 printf("0x%08x\n", ins_bytes
[0] << 24
6245 | ins_bytes
[1] << 16
6253 ahc_loadseq(struct ahc_softc
*ahc
)
6255 struct cs cs_table
[num_critical_sections
];
6256 u_int begin_set
[num_critical_sections
];
6257 u_int end_set
[num_critical_sections
];
6258 struct patch
*cur_patch
;
6263 u_int sg_prefetch_cnt
;
6265 uint8_t download_consts
[7];
6268 * Start out with 0 critical sections
6269 * that apply to this firmware load.
6273 memset(begin_set
, 0, sizeof(begin_set
));
6274 memset(end_set
, 0, sizeof(end_set
));
6276 /* Setup downloadable constant table */
6277 download_consts
[QOUTFIFO_OFFSET
] = 0;
6278 if (ahc
->targetcmds
!= NULL
)
6279 download_consts
[QOUTFIFO_OFFSET
] += 32;
6280 download_consts
[QINFIFO_OFFSET
] = download_consts
[QOUTFIFO_OFFSET
] + 1;
6281 download_consts
[CACHESIZE_MASK
] = ahc
->pci_cachesize
- 1;
6282 download_consts
[INVERTED_CACHESIZE_MASK
] = ~(ahc
->pci_cachesize
- 1);
6283 sg_prefetch_cnt
= ahc
->pci_cachesize
;
6284 if (sg_prefetch_cnt
< (2 * sizeof(struct ahc_dma_seg
)))
6285 sg_prefetch_cnt
= 2 * sizeof(struct ahc_dma_seg
);
6286 download_consts
[SG_PREFETCH_CNT
] = sg_prefetch_cnt
;
6287 download_consts
[SG_PREFETCH_ALIGN_MASK
] = ~(sg_prefetch_cnt
- 1);
6288 download_consts
[SG_PREFETCH_ADDR_MASK
] = (sg_prefetch_cnt
- 1);
6290 cur_patch
= patches
;
6293 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
6294 ahc_outb(ahc
, SEQADDR0
, 0);
6295 ahc_outb(ahc
, SEQADDR1
, 0);
6297 for (i
= 0; i
< sizeof(seqprog
)/4; i
++) {
6298 if (ahc_check_patch(ahc
, &cur_patch
, i
, &skip_addr
) == 0) {
6300 * Don't download this instruction as it
6301 * is in a patch that was removed.
6306 if (downloaded
== ahc
->instruction_ram_size
) {
6308 * We're about to exceed the instruction
6309 * storage capacity for this chip. Fail
6312 printf("\n%s: Program too large for instruction memory "
6313 "size of %d!\n", ahc_name(ahc
),
6314 ahc
->instruction_ram_size
);
6319 * Move through the CS table until we find a CS
6320 * that might apply to this instruction.
6322 for (; cur_cs
< num_critical_sections
; cur_cs
++) {
6323 if (critical_sections
[cur_cs
].end
<= i
) {
6324 if (begin_set
[cs_count
] == TRUE
6325 && end_set
[cs_count
] == FALSE
) {
6326 cs_table
[cs_count
].end
= downloaded
;
6327 end_set
[cs_count
] = TRUE
;
6332 if (critical_sections
[cur_cs
].begin
<= i
6333 && begin_set
[cs_count
] == FALSE
) {
6334 cs_table
[cs_count
].begin
= downloaded
;
6335 begin_set
[cs_count
] = TRUE
;
6339 ahc_download_instr(ahc
, i
, download_consts
);
6343 ahc
->num_critical_sections
= cs_count
;
6344 if (cs_count
!= 0) {
6346 cs_count
*= sizeof(struct cs
);
6347 ahc
->critical_sections
= malloc(cs_count
, M_DEVBUF
, M_NOWAIT
);
6348 if (ahc
->critical_sections
== NULL
)
6349 panic("ahc_loadseq: Could not malloc");
6350 memcpy(ahc
->critical_sections
, cs_table
, cs_count
);
6352 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
);
6355 printf(" %d instructions downloaded\n", downloaded
);
6356 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6357 ahc_name(ahc
), ahc
->features
, ahc
->bugs
, ahc
->flags
);
6363 ahc_check_patch(struct ahc_softc
*ahc
, struct patch
**start_patch
,
6364 u_int start_instr
, u_int
*skip_addr
)
6366 struct patch
*cur_patch
;
6367 struct patch
*last_patch
;
6370 num_patches
= sizeof(patches
)/sizeof(struct patch
);
6371 last_patch
= &patches
[num_patches
];
6372 cur_patch
= *start_patch
;
6374 while (cur_patch
< last_patch
&& start_instr
== cur_patch
->begin
) {
6376 if (cur_patch
->patch_func(ahc
) == 0) {
6378 /* Start rejecting code */
6379 *skip_addr
= start_instr
+ cur_patch
->skip_instr
;
6380 cur_patch
+= cur_patch
->skip_patch
;
6382 /* Accepted this patch. Advance to the next
6383 * one and wait for our intruction pointer to
6390 *start_patch
= cur_patch
;
6391 if (start_instr
< *skip_addr
)
6392 /* Still skipping */
6399 ahc_download_instr(struct ahc_softc
*ahc
, u_int instrptr
, uint8_t *dconsts
)
6401 union ins_formats instr
;
6402 struct ins_format1
*fmt1_ins
;
6403 struct ins_format3
*fmt3_ins
;
6407 * The firmware is always compiled into a little endian format.
6409 instr
.integer
= ahc_le32toh(*(uint32_t*)&seqprog
[instrptr
* 4]);
6411 fmt1_ins
= &instr
.format1
;
6414 /* Pull the opcode */
6415 opcode
= instr
.format1
.opcode
;
6426 struct patch
*cur_patch
;
6432 fmt3_ins
= &instr
.format3
;
6434 address
= fmt3_ins
->address
;
6435 cur_patch
= patches
;
6438 for (i
= 0; i
< address
;) {
6440 ahc_check_patch(ahc
, &cur_patch
, i
, &skip_addr
);
6442 if (skip_addr
> i
) {
6445 end_addr
= MIN(address
, skip_addr
);
6446 address_offset
+= end_addr
- i
;
6452 address
-= address_offset
;
6453 fmt3_ins
->address
= address
;
6462 if (fmt1_ins
->parity
!= 0) {
6463 fmt1_ins
->immediate
= dconsts
[fmt1_ins
->immediate
];
6465 fmt1_ins
->parity
= 0;
6466 if ((ahc
->features
& AHC_CMD_CHAN
) == 0
6467 && opcode
== AIC_OP_BMOV
) {
6469 * Block move was added at the same time
6470 * as the command channel. Verify that
6471 * this is only a move of a single element
6472 * and convert the BMOV to a MOV
6473 * (AND with an immediate of FF).
6475 if (fmt1_ins
->immediate
!= 1)
6476 panic("%s: BMOV not supported\n",
6478 fmt1_ins
->opcode
= AIC_OP_AND
;
6479 fmt1_ins
->immediate
= 0xff;
6483 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
6486 /* Calculate odd parity for the instruction */
6487 for (i
= 0, count
= 0; i
< 31; i
++) {
6491 if ((instr
.integer
& mask
) != 0)
6494 if ((count
& 0x01) == 0)
6495 instr
.format1
.parity
= 1;
6497 /* Compress the instruction for older sequencers */
6498 if (fmt3_ins
!= NULL
) {
6501 | (fmt3_ins
->source
<< 8)
6502 | (fmt3_ins
->address
<< 16)
6503 | (fmt3_ins
->opcode
<< 25);
6507 | (fmt1_ins
->source
<< 8)
6508 | (fmt1_ins
->destination
<< 16)
6509 | (fmt1_ins
->ret
<< 24)
6510 | (fmt1_ins
->opcode
<< 25);
6513 /* The sequencer is a little endian cpu */
6514 instr
.integer
= ahc_htole32(instr
.integer
);
6515 ahc_outsb(ahc
, SEQRAM
, instr
.bytes
, 4);
6518 panic("Unknown opcode encountered in seq program");
6524 ahc_print_register(ahc_reg_parse_entry_t
*table
, u_int num_entries
,
6525 const char *name
, u_int address
, u_int value
,
6526 u_int
*cur_column
, u_int wrap_point
)
6531 if (cur_column
!= NULL
&& *cur_column
>= wrap_point
) {
6535 printed
= printf("%s[0x%x]", name
, value
);
6536 if (table
== NULL
) {
6537 printed
+= printf(" ");
6538 *cur_column
+= printed
;
6542 while (printed_mask
!= 0xFF) {
6545 for (entry
= 0; entry
< num_entries
; entry
++) {
6546 if (((value
& table
[entry
].mask
)
6547 != table
[entry
].value
)
6548 || ((printed_mask
& table
[entry
].mask
)
6549 == table
[entry
].mask
))
6552 printed
+= printf("%s%s",
6553 printed_mask
== 0 ? ":(" : "|",
6555 printed_mask
|= table
[entry
].mask
;
6559 if (entry
>= num_entries
)
6562 if (printed_mask
!= 0)
6563 printed
+= printf(") ");
6565 printed
+= printf(" ");
6566 if (cur_column
!= NULL
)
6567 *cur_column
+= printed
;
6572 ahc_dump_card_state(struct ahc_softc
*ahc
)
6575 struct scb_tailq
*untagged_q
;
6586 uint8_t saved_scbptr
;
6588 if (ahc_is_paused(ahc
)) {
6595 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
6596 last_phase
= ahc_inb(ahc
, LASTPHASE
);
6597 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6598 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6599 ahc_name(ahc
), ahc_lookup_phase_entry(last_phase
)->phasemsg
,
6600 ahc_inb(ahc
, SEQADDR0
) | (ahc_inb(ahc
, SEQADDR1
) << 8));
6602 printf("Card was paused\n");
6603 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6604 ahc_inb(ahc
, ACCUM
), ahc_inb(ahc
, SINDEX
), ahc_inb(ahc
, DINDEX
),
6605 ahc_inb(ahc
, ARG_2
));
6606 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc
, HCNT
),
6607 ahc_inb(ahc
, SCBPTR
));
6609 if ((ahc
->features
& AHC_DT
) != 0)
6610 ahc_scsiphase_print(ahc_inb(ahc
, SCSIPHASE
), &cur_col
, 50);
6611 ahc_scsisigi_print(ahc_inb(ahc
, SCSISIGI
), &cur_col
, 50);
6612 ahc_error_print(ahc_inb(ahc
, ERROR
), &cur_col
, 50);
6613 ahc_scsibusl_print(ahc_inb(ahc
, SCSIBUSL
), &cur_col
, 50);
6614 ahc_lastphase_print(ahc_inb(ahc
, LASTPHASE
), &cur_col
, 50);
6615 ahc_scsiseq_print(ahc_inb(ahc
, SCSISEQ
), &cur_col
, 50);
6616 ahc_sblkctl_print(ahc_inb(ahc
, SBLKCTL
), &cur_col
, 50);
6617 ahc_scsirate_print(ahc_inb(ahc
, SCSIRATE
), &cur_col
, 50);
6618 ahc_seqctl_print(ahc_inb(ahc
, SEQCTL
), &cur_col
, 50);
6619 ahc_seq_flags_print(ahc_inb(ahc
, SEQ_FLAGS
), &cur_col
, 50);
6620 ahc_sstat0_print(ahc_inb(ahc
, SSTAT0
), &cur_col
, 50);
6621 ahc_sstat1_print(ahc_inb(ahc
, SSTAT1
), &cur_col
, 50);
6622 ahc_sstat2_print(ahc_inb(ahc
, SSTAT2
), &cur_col
, 50);
6623 ahc_sstat3_print(ahc_inb(ahc
, SSTAT3
), &cur_col
, 50);
6624 ahc_simode0_print(ahc_inb(ahc
, SIMODE0
), &cur_col
, 50);
6625 ahc_simode1_print(ahc_inb(ahc
, SIMODE1
), &cur_col
, 50);
6626 ahc_sxfrctl0_print(ahc_inb(ahc
, SXFRCTL0
), &cur_col
, 50);
6627 ahc_dfcntrl_print(ahc_inb(ahc
, DFCNTRL
), &cur_col
, 50);
6628 ahc_dfstatus_print(ahc_inb(ahc
, DFSTATUS
), &cur_col
, 50);
6632 for (i
= 0; i
< STACK_SIZE
; i
++)
6633 printf(" 0x%x", ahc_inb(ahc
, STACK
)|(ahc_inb(ahc
, STACK
) << 8));
6634 printf("\nSCB count = %d\n", ahc
->scb_data
->numscbs
);
6635 printf("Kernel NEXTQSCB = %d\n", ahc
->next_queued_scb
->hscb
->tag
);
6636 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc
, NEXT_QUEUED_SCB
));
6638 printf("QINFIFO entries: ");
6639 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
6640 qinpos
= ahc_inb(ahc
, SNSCB_QOFF
);
6641 ahc_outb(ahc
, SNSCB_QOFF
, qinpos
);
6643 qinpos
= ahc_inb(ahc
, QINPOS
);
6644 qintail
= ahc
->qinfifonext
;
6645 while (qinpos
!= qintail
) {
6646 printf("%d ", ahc
->qinfifo
[qinpos
]);
6651 printf("Waiting Queue entries: ");
6652 scb_index
= ahc_inb(ahc
, WAITING_SCBH
);
6654 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6655 ahc_outb(ahc
, SCBPTR
, scb_index
);
6656 printf("%d:%d ", scb_index
, ahc_inb(ahc
, SCB_TAG
));
6657 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6661 printf("Disconnected Queue entries: ");
6662 scb_index
= ahc_inb(ahc
, DISCONNECTED_SCBH
);
6664 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6665 ahc_outb(ahc
, SCBPTR
, scb_index
);
6666 printf("%d:%d ", scb_index
, ahc_inb(ahc
, SCB_TAG
));
6667 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6671 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_POSTREAD
);
6672 printf("QOUTFIFO entries: ");
6673 qoutpos
= ahc
->qoutfifonext
;
6675 while (ahc
->qoutfifo
[qoutpos
] != SCB_LIST_NULL
&& i
++ < 256) {
6676 printf("%d ", ahc
->qoutfifo
[qoutpos
]);
6681 printf("Sequencer Free SCB List: ");
6682 scb_index
= ahc_inb(ahc
, FREE_SCBH
);
6684 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6685 ahc_outb(ahc
, SCBPTR
, scb_index
);
6686 printf("%d ", scb_index
);
6687 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6691 printf("Sequencer SCB Info: ");
6692 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
6693 ahc_outb(ahc
, SCBPTR
, i
);
6694 cur_col
= printf("\n%3d ", i
);
6696 ahc_scb_control_print(ahc_inb(ahc
, SCB_CONTROL
), &cur_col
, 60);
6697 ahc_scb_scsiid_print(ahc_inb(ahc
, SCB_SCSIID
), &cur_col
, 60);
6698 ahc_scb_lun_print(ahc_inb(ahc
, SCB_LUN
), &cur_col
, 60);
6699 ahc_scb_tag_print(ahc_inb(ahc
, SCB_TAG
), &cur_col
, 60);
6703 printf("Pending list: ");
6705 LIST_FOREACH(scb
, &ahc
->pending_scbs
, pending_links
) {
6708 cur_col
= printf("\n%3d ", scb
->hscb
->tag
);
6709 ahc_scb_control_print(scb
->hscb
->control
, &cur_col
, 60);
6710 ahc_scb_scsiid_print(scb
->hscb
->scsiid
, &cur_col
, 60);
6711 ahc_scb_lun_print(scb
->hscb
->lun
, &cur_col
, 60);
6712 if ((ahc
->flags
& AHC_PAGESCBS
) == 0) {
6713 ahc_outb(ahc
, SCBPTR
, scb
->hscb
->tag
);
6715 ahc_scb_control_print(ahc_inb(ahc
, SCB_CONTROL
),
6717 ahc_scb_tag_print(ahc_inb(ahc
, SCB_TAG
), &cur_col
, 60);
6723 printf("Kernel Free SCB list: ");
6725 SLIST_FOREACH(scb
, &ahc
->scb_data
->free_scbs
, links
.sle
) {
6728 printf("%d ", scb
->hscb
->tag
);
6732 maxtarget
= (ahc
->features
& (AHC_WIDE
|AHC_TWIN
)) ? 15 : 7;
6733 for (target
= 0; target
<= maxtarget
; target
++) {
6734 untagged_q
= &ahc
->untagged_queues
[target
];
6735 if (TAILQ_FIRST(untagged_q
) == NULL
)
6737 printf("Untagged Q(%d): ", target
);
6739 TAILQ_FOREACH(scb
, untagged_q
, links
.tqe
) {
6742 printf("%d ", scb
->hscb
->tag
);
6747 ahc_platform_dump_card_state(ahc
);
6748 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6749 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
6754 /************************* Target Mode ****************************************/
6755 #ifdef AHC_TARGET_MODE
6757 ahc_find_tmode_devs(struct ahc_softc
*ahc
, struct cam_sim
*sim
, union ccb
*ccb
,
6758 struct ahc_tmode_tstate
**tstate
,
6759 struct ahc_tmode_lstate
**lstate
,
6760 int notfound_failure
)
6763 if ((ahc
->features
& AHC_TARGETMODE
) == 0)
6764 return (CAM_REQ_INVALID
);
6767 * Handle the 'black hole' device that sucks up
6768 * requests to unattached luns on enabled targets.
6770 if (ccb
->ccb_h
.target_id
== CAM_TARGET_WILDCARD
6771 && ccb
->ccb_h
.target_lun
== CAM_LUN_WILDCARD
) {
6773 *lstate
= ahc
->black_hole
;
6777 max_id
= (ahc
->features
& AHC_WIDE
) ? 15 : 7;
6778 if (ccb
->ccb_h
.target_id
> max_id
)
6779 return (CAM_TID_INVALID
);
6781 if (ccb
->ccb_h
.target_lun
>= AHC_NUM_LUNS
)
6782 return (CAM_LUN_INVALID
);
6784 *tstate
= ahc
->enabled_targets
[ccb
->ccb_h
.target_id
];
6786 if (*tstate
!= NULL
)
6788 (*tstate
)->enabled_luns
[ccb
->ccb_h
.target_lun
];
6791 if (notfound_failure
!= 0 && *lstate
== NULL
)
6792 return (CAM_PATH_INVALID
);
6794 return (CAM_REQ_CMP
);
6798 ahc_handle_en_lun(struct ahc_softc
*ahc
, struct cam_sim
*sim
, union ccb
*ccb
)
6800 struct ahc_tmode_tstate
*tstate
;
6801 struct ahc_tmode_lstate
*lstate
;
6802 struct ccb_en_lun
*cel
;
6812 status
= ahc_find_tmode_devs(ahc
, sim
, ccb
, &tstate
, &lstate
,
6813 /*notfound_failure*/FALSE
);
6815 if (status
!= CAM_REQ_CMP
) {
6816 ccb
->ccb_h
.status
= status
;
6820 if (cam_sim_bus(sim
) == 0)
6821 our_id
= ahc
->our_id
;
6823 our_id
= ahc
->our_id_b
;
6825 if (ccb
->ccb_h
.target_id
!= our_id
) {
6827 * our_id represents our initiator ID, or
6828 * the ID of the first target to have an
6829 * enabled lun in target mode. There are
6830 * two cases that may preclude enabling a
6831 * target id other than our_id.
6833 * o our_id is for an active initiator role.
6834 * Since the hardware does not support
6835 * reselections to the initiator role at
6836 * anything other than our_id, and our_id
6837 * is used by the hardware to indicate the
6838 * ID to use for both select-out and
6839 * reselect-out operations, the only target
6840 * ID we can support in this mode is our_id.
6842 * o The MULTARGID feature is not available and
6843 * a previous target mode ID has been enabled.
6845 if ((ahc
->features
& AHC_MULTIROLE
) != 0) {
6847 if ((ahc
->features
& AHC_MULTI_TID
) != 0
6848 && (ahc
->flags
& AHC_INITIATORROLE
) != 0) {
6850 * Only allow additional targets if
6851 * the initiator role is disabled.
6852 * The hardware cannot handle a re-select-in
6853 * on the initiator id during a re-select-out
6854 * on a different target id.
6856 status
= CAM_TID_INVALID
;
6857 } else if ((ahc
->flags
& AHC_INITIATORROLE
) != 0
6858 || ahc
->enabled_luns
> 0) {
6860 * Only allow our target id to change
6861 * if the initiator role is not configured
6862 * and there are no enabled luns which
6863 * are attached to the currently registered
6866 status
= CAM_TID_INVALID
;
6868 } else if ((ahc
->features
& AHC_MULTI_TID
) == 0
6869 && ahc
->enabled_luns
> 0) {
6871 status
= CAM_TID_INVALID
;
6875 if (status
!= CAM_REQ_CMP
) {
6876 ccb
->ccb_h
.status
= status
;
6881 * We now have an id that is valid.
6882 * If we aren't in target mode, switch modes.
6884 if ((ahc
->flags
& AHC_TARGETROLE
) == 0
6885 && ccb
->ccb_h
.target_id
!= CAM_TARGET_WILDCARD
) {
6887 ahc_flag saved_flags
;
6889 printf("Configuring Target Mode\n");
6891 if (LIST_FIRST(&ahc
->pending_scbs
) != NULL
) {
6892 ccb
->ccb_h
.status
= CAM_BUSY
;
6893 ahc_unlock(ahc
, &s
);
6896 saved_flags
= ahc
->flags
;
6897 ahc
->flags
|= AHC_TARGETROLE
;
6898 if ((ahc
->features
& AHC_MULTIROLE
) == 0)
6899 ahc
->flags
&= ~AHC_INITIATORROLE
;
6901 error
= ahc_loadseq(ahc
);
6904 * Restore original configuration and notify
6905 * the caller that we cannot support target mode.
6906 * Since the adapter started out in this
6907 * configuration, the firmware load will succeed,
6908 * so there is no point in checking ahc_loadseq's
6911 ahc
->flags
= saved_flags
;
6912 (void)ahc_loadseq(ahc
);
6914 ahc_unlock(ahc
, &s
);
6915 ccb
->ccb_h
.status
= CAM_FUNC_NOTAVAIL
;
6919 ahc_unlock(ahc
, &s
);
6922 target
= ccb
->ccb_h
.target_id
;
6923 lun
= ccb
->ccb_h
.target_lun
;
6924 channel
= SIM_CHANNEL(ahc
, sim
);
6925 target_mask
= 0x01 << target
;
6929 if (cel
->enable
!= 0) {
6932 /* Are we already enabled?? */
6933 if (lstate
!= NULL
) {
6934 xpt_print_path(ccb
->ccb_h
.path
);
6935 printf("Lun already enabled\n");
6936 ccb
->ccb_h
.status
= CAM_LUN_ALRDY_ENA
;
6940 if (cel
->grp6_len
!= 0
6941 || cel
->grp7_len
!= 0) {
6943 * Don't (yet?) support vendor
6944 * specific commands.
6946 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
6947 printf("Non-zero Group Codes\n");
6953 * Setup our data structures.
6955 if (target
!= CAM_TARGET_WILDCARD
&& tstate
== NULL
) {
6956 tstate
= ahc_alloc_tstate(ahc
, target
, channel
);
6957 if (tstate
== NULL
) {
6958 xpt_print_path(ccb
->ccb_h
.path
);
6959 printf("Couldn't allocate tstate\n");
6960 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
6964 lstate
= malloc(sizeof(*lstate
), M_DEVBUF
, M_NOWAIT
);
6965 if (lstate
== NULL
) {
6966 xpt_print_path(ccb
->ccb_h
.path
);
6967 printf("Couldn't allocate lstate\n");
6968 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
6971 memset(lstate
, 0, sizeof(*lstate
));
6972 status
= xpt_create_path(&lstate
->path
, /*periph*/NULL
,
6973 xpt_path_path_id(ccb
->ccb_h
.path
),
6974 xpt_path_target_id(ccb
->ccb_h
.path
),
6975 xpt_path_lun_id(ccb
->ccb_h
.path
));
6976 if (status
!= CAM_REQ_CMP
) {
6977 free(lstate
, M_DEVBUF
);
6978 xpt_print_path(ccb
->ccb_h
.path
);
6979 printf("Couldn't allocate path\n");
6980 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
6983 SLIST_INIT(&lstate
->accept_tios
);
6984 SLIST_INIT(&lstate
->immed_notifies
);
6987 if (target
!= CAM_TARGET_WILDCARD
) {
6988 tstate
->enabled_luns
[lun
] = lstate
;
6989 ahc
->enabled_luns
++;
6991 if ((ahc
->features
& AHC_MULTI_TID
) != 0) {
6994 targid_mask
= ahc_inb(ahc
, TARGID
)
6995 | (ahc_inb(ahc
, TARGID
+ 1) << 8);
6997 targid_mask
|= target_mask
;
6998 ahc_outb(ahc
, TARGID
, targid_mask
);
6999 ahc_outb(ahc
, TARGID
+1, (targid_mask
>> 8));
7001 ahc_update_scsiid(ahc
, targid_mask
);
7006 channel
= SIM_CHANNEL(ahc
, sim
);
7007 our_id
= SIM_SCSI_ID(ahc
, sim
);
7010 * This can only happen if selections
7013 if (target
!= our_id
) {
7018 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
7019 cur_channel
= (sblkctl
& SELBUSB
)
7021 if ((ahc
->features
& AHC_TWIN
) == 0)
7023 swap
= cur_channel
!= channel
;
7025 ahc
->our_id
= target
;
7027 ahc
->our_id_b
= target
;
7030 ahc_outb(ahc
, SBLKCTL
,
7033 ahc_outb(ahc
, SCSIID
, target
);
7036 ahc_outb(ahc
, SBLKCTL
, sblkctl
);
7040 ahc
->black_hole
= lstate
;
7041 /* Allow select-in operations */
7042 if (ahc
->black_hole
!= NULL
&& ahc
->enabled_luns
> 0) {
7043 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
7045 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq
);
7046 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
7048 ahc_outb(ahc
, SCSISEQ
, scsiseq
);
7051 ahc_unlock(ahc
, &s
);
7052 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
7053 xpt_print_path(ccb
->ccb_h
.path
);
7054 printf("Lun now enabled for target mode\n");
7059 if (lstate
== NULL
) {
7060 ccb
->ccb_h
.status
= CAM_LUN_INVALID
;
7066 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
7067 LIST_FOREACH(scb
, &ahc
->pending_scbs
, pending_links
) {
7068 struct ccb_hdr
*ccbh
;
7070 ccbh
= &scb
->io_ctx
->ccb_h
;
7071 if (ccbh
->func_code
== XPT_CONT_TARGET_IO
7072 && !xpt_path_comp(ccbh
->path
, ccb
->ccb_h
.path
)){
7073 printf("CTIO pending\n");
7074 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7075 ahc_unlock(ahc
, &s
);
7080 if (SLIST_FIRST(&lstate
->accept_tios
) != NULL
) {
7081 printf("ATIOs pending\n");
7082 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7085 if (SLIST_FIRST(&lstate
->immed_notifies
) != NULL
) {
7086 printf("INOTs pending\n");
7087 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7090 if (ccb
->ccb_h
.status
!= CAM_REQ_CMP
) {
7091 ahc_unlock(ahc
, &s
);
7095 xpt_print_path(ccb
->ccb_h
.path
);
7096 printf("Target mode disabled\n");
7097 xpt_free_path(lstate
->path
);
7098 free(lstate
, M_DEVBUF
);
7101 /* Can we clean up the target too? */
7102 if (target
!= CAM_TARGET_WILDCARD
) {
7103 tstate
->enabled_luns
[lun
] = NULL
;
7104 ahc
->enabled_luns
--;
7105 for (empty
= 1, i
= 0; i
< 8; i
++)
7106 if (tstate
->enabled_luns
[i
] != NULL
) {
7112 ahc_free_tstate(ahc
, target
, channel
,
7114 if (ahc
->features
& AHC_MULTI_TID
) {
7117 targid_mask
= ahc_inb(ahc
, TARGID
)
7118 | (ahc_inb(ahc
, TARGID
+ 1)
7121 targid_mask
&= ~target_mask
;
7122 ahc_outb(ahc
, TARGID
, targid_mask
);
7123 ahc_outb(ahc
, TARGID
+1,
7124 (targid_mask
>> 8));
7125 ahc_update_scsiid(ahc
, targid_mask
);
7130 ahc
->black_hole
= NULL
;
7133 * We can't allow selections without
7134 * our black hole device.
7138 if (ahc
->enabled_luns
== 0) {
7139 /* Disallow select-in */
7142 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
7144 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq
);
7145 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
7147 ahc_outb(ahc
, SCSISEQ
, scsiseq
);
7149 if ((ahc
->features
& AHC_MULTIROLE
) == 0) {
7150 printf("Configuring Initiator Mode\n");
7151 ahc
->flags
&= ~AHC_TARGETROLE
;
7152 ahc
->flags
|= AHC_INITIATORROLE
;
7154 * Returning to a configuration that
7155 * fit previously will always succeed.
7157 (void)ahc_loadseq(ahc
);
7160 * Unpaused. The extra unpause
7161 * that follows is harmless.
7166 ahc_unlock(ahc
, &s
);
7171 ahc_update_scsiid(struct ahc_softc
*ahc
, u_int targid_mask
)
7176 if ((ahc
->features
& AHC_MULTI_TID
) == 0)
7177 panic("ahc_update_scsiid called on non-multitid unit\n");
7180 * Since we will rely on the TARGID mask
7181 * for selection enables, ensure that OID
7182 * in SCSIID is not set to some other ID
7183 * that we don't want to allow selections on.
7185 if ((ahc
->features
& AHC_ULTRA2
) != 0)
7186 scsiid
= ahc_inb(ahc
, SCSIID_ULTRA2
);
7188 scsiid
= ahc_inb(ahc
, SCSIID
);
7189 scsiid_mask
= 0x1 << (scsiid
& OID
);
7190 if ((targid_mask
& scsiid_mask
) == 0) {
7193 /* ffs counts from 1 */
7194 our_id
= ffs(targid_mask
);
7196 our_id
= ahc
->our_id
;
7202 if ((ahc
->features
& AHC_ULTRA2
) != 0)
7203 ahc_outb(ahc
, SCSIID_ULTRA2
, scsiid
);
7205 ahc_outb(ahc
, SCSIID
, scsiid
);
7209 ahc_run_tqinfifo(struct ahc_softc
*ahc
, int paused
)
7211 struct target_cmd
*cmd
;
7214 * If the card supports auto-access pause,
7215 * we can access the card directly regardless
7216 * of whether it is paused or not.
7218 if ((ahc
->features
& AHC_AUTOPAUSE
) != 0)
7221 ahc_sync_tqinfifo(ahc
, BUS_DMASYNC_POSTREAD
);
7222 while ((cmd
= &ahc
->targetcmds
[ahc
->tqinfifonext
])->cmd_valid
!= 0) {
7225 * Only advance through the queue if we
7226 * have the resources to process the command.
7228 if (ahc_handle_target_cmd(ahc
, cmd
) != 0)
7232 ahc_dmamap_sync(ahc
, ahc
->shared_data_dmat
,
7233 ahc
->shared_data_dmamap
,
7234 ahc_targetcmd_offset(ahc
, ahc
->tqinfifonext
),
7235 sizeof(struct target_cmd
),
7236 BUS_DMASYNC_PREREAD
);
7237 ahc
->tqinfifonext
++;
7240 * Lazily update our position in the target mode incoming
7241 * command queue as seen by the sequencer.
7243 if ((ahc
->tqinfifonext
& (HOST_TQINPOS
- 1)) == 1) {
7244 if ((ahc
->features
& AHC_HS_MAILBOX
) != 0) {
7247 hs_mailbox
= ahc_inb(ahc
, HS_MAILBOX
);
7248 hs_mailbox
&= ~HOST_TQINPOS
;
7249 hs_mailbox
|= ahc
->tqinfifonext
& HOST_TQINPOS
;
7250 ahc_outb(ahc
, HS_MAILBOX
, hs_mailbox
);
7254 ahc_outb(ahc
, KERNEL_TQINPOS
,
7255 ahc
->tqinfifonext
& HOST_TQINPOS
);
7264 ahc_handle_target_cmd(struct ahc_softc
*ahc
, struct target_cmd
*cmd
)
7266 struct ahc_tmode_tstate
*tstate
;
7267 struct ahc_tmode_lstate
*lstate
;
7268 struct ccb_accept_tio
*atio
;
7274 initiator
= SCSIID_TARGET(ahc
, cmd
->scsiid
);
7275 target
= SCSIID_OUR_ID(cmd
->scsiid
);
7276 lun
= (cmd
->identify
& MSG_IDENTIFY_LUNMASK
);
7279 tstate
= ahc
->enabled_targets
[target
];
7282 lstate
= tstate
->enabled_luns
[lun
];
7285 * Commands for disabled luns go to the black hole driver.
7288 lstate
= ahc
->black_hole
;
7290 atio
= (struct ccb_accept_tio
*)SLIST_FIRST(&lstate
->accept_tios
);
7292 ahc
->flags
|= AHC_TQINFIFO_BLOCKED
;
7294 * Wait for more ATIOs from the peripheral driver for this lun.
7297 printf("%s: ATIOs exhausted\n", ahc_name(ahc
));
7300 ahc
->flags
&= ~AHC_TQINFIFO_BLOCKED
;
7302 printf("Incoming command from %d for %d:%d%s\n",
7303 initiator
, target
, lun
,
7304 lstate
== ahc
->black_hole
? "(Black Holed)" : "");
7306 SLIST_REMOVE_HEAD(&lstate
->accept_tios
, sim_links
.sle
);
7308 if (lstate
== ahc
->black_hole
) {
7309 /* Fill in the wildcards */
7310 atio
->ccb_h
.target_id
= target
;
7311 atio
->ccb_h
.target_lun
= lun
;
7315 * Package it up and send it off to
7316 * whomever has this lun enabled.
7318 atio
->sense_len
= 0;
7319 atio
->init_id
= initiator
;
7320 if (byte
[0] != 0xFF) {
7321 /* Tag was included */
7322 atio
->tag_action
= *byte
++;
7323 atio
->tag_id
= *byte
++;
7324 atio
->ccb_h
.flags
= CAM_TAG_ACTION_VALID
;
7326 atio
->ccb_h
.flags
= 0;
7330 /* Okay. Now determine the cdb size based on the command code */
7331 switch (*byte
>> CMD_GROUP_CODE_SHIFT
) {
7347 /* Only copy the opcode. */
7349 printf("Reserved or VU command code type encountered\n");
7353 memcpy(atio
->cdb_io
.cdb_bytes
, byte
, atio
->cdb_len
);
7355 atio
->ccb_h
.status
|= CAM_CDB_RECVD
;
7357 if ((cmd
->identify
& MSG_IDENTIFY_DISCFLAG
) == 0) {
7359 * We weren't allowed to disconnect.
7360 * We're hanging on the bus until a
7361 * continue target I/O comes in response
7362 * to this accept tio.
7365 printf("Received Immediate Command %d:%d:%d - %p\n",
7366 initiator
, target
, lun
, ahc
->pending_device
);
7368 ahc
->pending_device
= lstate
;
7369 ahc_freeze_ccb((union ccb
*)atio
);
7370 atio
->ccb_h
.flags
|= CAM_DIS_DISCONNECT
;
7372 xpt_done((union ccb
*)atio
);