include/asm-mips/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #include <linux/config.h>
  16 #include <linux/compiler.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/byteorder.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/page.h>
  25 #include <asm/pgtable-bits.h>
  26 #include <asm/processor.h>
  27 #include <asm/string.h>
  28
  29 #include <ioremap.h>
  30 #include <mangle-port.h>
  31
  32 /*
  33  * Slowdown I/O port space accesses for antique hardware.
  34  */
  35 #undef CONF_SLOWDOWN_IO
  36
  37 /*
  38  * Raw operations are never swapped in software.  OTOH values that raw
  39  * operations are working on may or may not have been swapped by the bus
  40  * hardware.  An example use would be for flash memory that's used for
  41  * execute in place.
  42  */
  43 # define __raw_ioswabb(x)       (x)
  44 # define __raw_ioswabw(x)       (x)
  45 # define __raw_ioswabl(x)       (x)
  46 # define __raw_ioswabq(x)       (x)
  47 # define ____raw_ioswabq(x)     (x)
  48
  49 /*
  50  * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
  51  * less sane hardware forces software to fiddle with this...
  52  *
  53  * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
  54  * you can't have the numerical value of data and byte addresses within
  55  * multibyte quantities both preserved at the same time.  Hence two
  56  * variations of functions: non-prefixed ones that preserve the value
  57  * and prefixed ones that preserve byte addresses.  The latters are
  58  * typically used for moving raw data between a peripheral and memory (cf.
  59  * string I/O functions), hence the "__mem_" prefix.
  60  */
  61 #if defined(CONFIG_SWAP_IO_SPACE)
  62
  63 # define ioswabb(x)             (x)
  64 # define __mem_ioswabb(x)       (x)
  65 # ifdef CONFIG_SGI_IP22
  66 /*
  67  * IP22 seems braindead enough to swap 16bits values in hardware, but
  68  * not 32bits.  Go figure... Can't tell without documentation.
  69  */
  70 #  define ioswabw(x)            (x)
  71 #  define __mem_ioswabw(x)      le16_to_cpu(x)
  72 # else
  73 #  define ioswabw(x)            le16_to_cpu(x)
  74 #  define __mem_ioswabw(x)      (x)
  75 # endif
  76 # define ioswabl(x)             le32_to_cpu(x)
  77 # define __mem_ioswabl(x)       (x)
  78 # define ioswabq(x)             le64_to_cpu(x)
  79 # define __mem_ioswabq(x)       (x)
  80
  81 #else
  82
  83 # define ioswabb(x)             (x)
  84 # define __mem_ioswabb(x)       (x)
  85 # define ioswabw(x)             (x)
  86 # define __mem_ioswabw(x)       cpu_to_le16(x)
  87 # define ioswabl(x)             (x)
  88 # define __mem_ioswabl(x)       cpu_to_le32(x)
  89 # define ioswabq(x)             (x)
  90 # define __mem_ioswabq(x)       cpu_to_le32(x)
  91
  92 #endif
  93
  94 #define IO_SPACE_LIMIT 0xffff
  95
  96 /*
  97  * On MIPS I/O ports are memory mapped, so we access them using normal
  98  * load/store instructions. mips_io_port_base is the virtual address to
  99  * which all ports are being mapped.  For sake of efficiency some code
 100  * assumes that this is an address that can be loaded with a single lui
 101  * instruction, so the lower 16 bits must be zero.  Should be true on
 102  * on any sane architecture; generic code does not use this assumption.
 103  */
 104 extern const unsigned long mips_io_port_base;
 105
 106 /*
 107  * Gcc will generate code to load the value of mips_io_port_base after each
 108  * function call which may be fairly wasteful in some cases.  So we don't
 109  * play quite by the book.  We tell gcc mips_io_port_base is a long variable
 110  * which solves the code generation issue.  Now we need to violate the
 111  * aliasing rules a little to make initialization possible and finally we
 112  * will need the barrier() to fight side effects of the aliasing chat.
 113  * This trickery will eventually collapse under gcc's optimizer.  Oh well.
 114  */
 115 static inline void set_io_port_base(unsigned long base)
 116 {
 117         * (unsigned long *) &mips_io_port_base = base;
 118         barrier();
 119 }
 120
 121 /*
 122  * Thanks to James van Artsdalen for a better timing-fix than
 123  * the two short jumps: using outb's to a nonexistent port seems
 124  * to guarantee better timings even on fast machines.
 125  *
 126  * On the other hand, I'd like to be sure of a non-existent port:
 127  * I feel a bit unsafe about using 0x80 (should be safe, though)
 128  *
 129  *              Linus
 130  *
 131  */
 132
 133 #define __SLOW_DOWN_IO \
 134         __asm__ __volatile__( \
 135                 "sb\t$0,0x80(%0)" \
 136                 : : "r" (mips_io_port_base));
 137
 138 #ifdef CONF_SLOWDOWN_IO
 139 #ifdef REALLY_SLOW_IO
 140 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
 141 #else
 142 #define SLOW_DOWN_IO __SLOW_DOWN_IO
 143 #endif
 144 #else
 145 #define SLOW_DOWN_IO
 146 #endif
 147
 148 /*
 149  *     virt_to_phys    -       map virtual addresses to physical
 150  *     @address: address to remap
 151  *
 152  *     The returned physical address is the physical (CPU) mapping for
 153  *     the memory address given. It is only valid to use this function on
 154  *     addresses directly mapped or allocated via kmalloc.
 155  *
 156  *     This function does not give bus mappings for DMA transfers. In
 157  *     almost all conceivable cases a device driver should not be using
 158  *     this function
 159  */
 160 static inline unsigned long virt_to_phys(volatile void * address)
 161 {
 162         return (unsigned long)address - PAGE_OFFSET;
 163 }
 164
 165 /*
 166  *     phys_to_virt    -       map physical address to virtual
 167  *     @address: address to remap
 168  *
 169  *     The returned virtual address is a current CPU mapping for
 170  *     the memory address given. It is only valid to use this function on
 171  *     addresses that have a kernel mapping
 172  *
 173  *     This function does not handle bus mappings for DMA transfers. In
 174  *     almost all conceivable cases a device driver should not be using
 175  *     this function
 176  */
 177 static inline void * phys_to_virt(unsigned long address)
 178 {
 179         return (void *)(address + PAGE_OFFSET);
 180 }
 181
 182 /*
 183  * ISA I/O bus memory addresses are 1:1 with the physical address.
 184  */
 185 static inline unsigned long isa_virt_to_bus(volatile void * address)
 186 {
 187         return (unsigned long)address - PAGE_OFFSET;
 188 }
 189
 190 static inline void * isa_bus_to_virt(unsigned long address)
 191 {
 192         return (void *)(address + PAGE_OFFSET);
 193 }
 194
 195 #define isa_page_to_bus page_to_phys
 196
 197 /*
 198  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 199  * are forbidden in portable PCI drivers.
 200  *
 201  * Allow them for x86 for legacy drivers, though.
 202  */
 203 #define virt_to_bus virt_to_phys
 204 #define bus_to_virt phys_to_virt
 205
 206 /*
 207  * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
 208  * for the processor.  This implies the assumption that there is only
 209  * one of these busses.
 210  */
 211 extern unsigned long isa_slot_offset;
 212
 213 /*
 214  * Change "struct page" to physical address.
 215  */
 216 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 217
 218 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 219 extern void __iounmap(volatile void __iomem *addr);
 220
 221 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 222         unsigned long flags)
 223 {
 224 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
 225
 226         if (cpu_has_64bit_addresses) {
 227                 u64 base = UNCAC_BASE;
 228
 229                 /*
 230                  * R10000 supports a 2 bit uncached attribute therefore
 231                  * UNCAC_BASE may not equal IO_BASE.
 232                  */
 233                 if (flags == _CACHE_UNCACHED)
 234                         base = (u64) IO_BASE;
 235                 return (void __iomem *) (unsigned long) (base + offset);
 236         } else if (__builtin_constant_p(offset) &&
 237                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
 238                 phys_t phys_addr, last_addr;
 239
 240                 phys_addr = fixup_bigphys_addr(offset, size);
 241
 242                 /* Don't allow wraparound or zero size. */
 243                 last_addr = phys_addr + size - 1;
 244                 if (!size || last_addr < phys_addr)
 245                         return NULL;
 246
 247                 /*
 248                  * Map uncached objects in the low 512MB of address
 249                  * space using KSEG1.
 250                  */
 251                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
 252                     flags == _CACHE_UNCACHED)
 253                         return (void __iomem *)CKSEG1ADDR(phys_addr);
 254         }
 255
 256         return __ioremap(offset, size, flags);
 257
 258 #undef __IS_LOW512
 259 }
 260
 261 /*
 262  * ioremap     -   map bus memory into CPU space
 263  * @offset:    bus address of the memory
 264  * @size:      size of the resource to map
 265  *
 266  * ioremap performs a platform specific sequence of operations to
 267  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 268  * writew/writel functions and the other mmio helpers. The returned
 269  * address is not guaranteed to be usable directly as a virtual
 270  * address.
 271  */
 272 #define ioremap(offset, size)                                           \
 273         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 274
 275 /*
 276  * ioremap_nocache     -   map bus memory into CPU space
 277  * @offset:    bus address of the memory
 278  * @size:      size of the resource to map
 279  *
 280  * ioremap_nocache performs a platform specific sequence of operations to
 281  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 282  * writew/writel functions and the other mmio helpers. The returned
 283  * address is not guaranteed to be usable directly as a virtual
 284  * address.
 285  *
 286  * This version of ioremap ensures that the memory is marked uncachable
 287  * on the CPU as well as honouring existing caching rules from things like
 288  * the PCI bus. Note that there are other caches and buffers on many
 289  * busses. In paticular driver authors should read up on PCI writes
 290  *
 291  * It's useful if some control registers are in such an area and
 292  * write combining or read caching is not desirable:
 293  */
 294 #define ioremap_nocache(offset, size)                                   \
 295         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 296
 297 /*
 298  * ioremap_cachable -   map bus memory into CPU space
 299  * @offset:         bus address of the memory
 300  * @size:           size of the resource to map
 301  *
 302  * ioremap_nocache performs a platform specific sequence of operations to
 303  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 304  * writew/writel functions and the other mmio helpers. The returned
 305  * address is not guaranteed to be usable directly as a virtual
 306  * address.
 307  *
 308  * This version of ioremap ensures that the memory is marked cachable by
 309  * the CPU.  Also enables full write-combining.  Useful for some
 310  * memory-like regions on I/O busses.
 311  */
 312 #define ioremap_cachable(offset, size)                                  \
 313         __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
 314
 315 /*
 316  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
 317  * requests a cachable mapping, ioremap_uncached_accelerated requests a
 318  * mapping using the uncached accelerated mode which isn't supported on
 319  * all processors.
 320  */
 321 #define ioremap_cacheable_cow(offset, size)                             \
 322         __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
 323 #define ioremap_uncached_accelerated(offset, size)                      \
 324         __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
 325
 326 static inline void iounmap(volatile void __iomem *addr)
 327 {
 328 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
 329
 330         if (cpu_has_64bit_addresses ||
 331             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
 332                 return;
 333
 334         __iounmap(addr);
 335
 336 #undef __IS_KSEG1
 337 }
 338
 339 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
 340                                                                         \
 341 static inline void pfx##write##bwlq(type val,                           \
 342                                     volatile void __iomem *mem)         \
 343 {                                                                       \
 344         volatile type *__mem;                                           \
 345         type __val;                                                     \
 346                                                                         \
 347         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 348                                                                         \
 349         __val = pfx##ioswab##bwlq(val);                                 \
 350                                                                         \
 351         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 352                 *__mem = __val;                                         \
 353         else if (cpu_has_64bits) {                                      \
 354                 unsigned long __flags;                                  \
 355                 type __tmp;                                             \
 356                                                                         \
 357                 if (irq)                                                \
 358                         local_irq_save(__flags);                        \
 359                 __asm__ __volatile__(                                   \
 360                         ".set   mips3"          "\t\t# __writeq""\n\t"  \
 361                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 362                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 363                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 364                         "or     %L0, %L0, %M0"                  "\n\t"  \
 365                         "sd     %L0, %2"                        "\n\t"  \
 366                         ".set   mips0"                          "\n"    \
 367                         : "=r" (__tmp)                                  \
 368                         : "0" (__val), "m" (*__mem));                   \
 369                 if (irq)                                                \
 370                         local_irq_restore(__flags);                     \
 371         } else                                                          \
 372                 BUG();                                                  \
 373 }                                                                       \
 374                                                                         \
 375 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 376 {                                                                       \
 377         volatile type *__mem;                                           \
 378         type __val;                                                     \
 379                                                                         \
 380         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 381                                                                         \
 382         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 383                 __val = *__mem;                                         \
 384         else if (cpu_has_64bits) {                                      \
 385                 unsigned long __flags;                                  \
 386                                                                         \
 387                 if (irq)                                                \
 388                         local_irq_save(__flags);                        \
 389                 __asm__ __volatile__(                                   \
 390                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
 391                         "ld     %L0, %1"                        "\n\t"  \
 392                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 393                         "sll    %L0, %L0, 0"                    "\n\t"  \
 394                         ".set   mips0"                          "\n"    \
 395                         : "=r" (__val)                                  \
 396                         : "m" (*__mem));                                \
 397                 if (irq)                                                \
 398                         local_irq_restore(__flags);                     \
 399         } else {                                                        \
 400                 __val = 0;                                              \
 401                 BUG();                                                  \
 402         }                                                               \
 403                                                                         \
 404         return pfx##ioswab##bwlq(__val);                                \
 405 }
 406
 407 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 408                                                                         \
 409 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 410 {                                                                       \
 411         volatile type *__addr;                                          \
 412         type __val;                                                     \
 413                                                                         \
 414         port = __swizzle_addr_##bwlq(port);                             \
 415         __addr = (void *)(mips_io_port_base + port);                    \
 416                                                                         \
 417         __val = pfx##ioswab##bwlq(val);                                 \
 418                                                                         \
 419         /* Really, we want this to be atomic */                         \
 420         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 421                                                                         \
 422         *__addr = __val;                                                \
 423         slow;                                                           \
 424 }                                                                       \
 425                                                                         \
 426 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 427 {                                                                       \
 428         volatile type *__addr;                                          \
 429         type __val;                                                     \
 430                                                                         \
 431         port = __swizzle_addr_##bwlq(port);                             \
 432         __addr = (void *)(mips_io_port_base + port);                    \
 433                                                                         \
 434         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 435                                                                         \
 436         __val = *__addr;                                                \
 437         slow;                                                           \
 438                                                                         \
 439         return pfx##ioswab##bwlq(__val);                                \
 440 }
 441
 442 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
 443                                                                         \
 444 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 445
 446 #define BUILDIO_MEM(bwlq, type)                                         \
 447                                                                         \
 448 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
 449 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
 450 __BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
 451
 452 BUILDIO_MEM(b, u8)
 453 BUILDIO_MEM(w, u16)
 454 BUILDIO_MEM(l, u32)
 455 BUILDIO_MEM(q, u64)
 456
 457 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 458         __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
 459         __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 460
 461 #define BUILDIO_IOPORT(bwlq, type)                                      \
 462         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 463         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 464
 465 BUILDIO_IOPORT(b, u8)
 466 BUILDIO_IOPORT(w, u16)
 467 BUILDIO_IOPORT(l, u32)
 468 #ifdef CONFIG_64BIT
 469 BUILDIO_IOPORT(q, u64)
 470 #endif
 471
 472 #define __BUILDIO(bwlq, type)                                           \
 473                                                                         \
 474 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 475
 476 __BUILDIO(q, u64)
 477
 478 #define readb_relaxed                   readb
 479 #define readw_relaxed                   readw
 480 #define readl_relaxed                   readl
 481 #define readq_relaxed                   readq
 482
 483 /*
 484  * Some code tests for these symbols
 485  */
 486 #define readq                           readq
 487 #define writeq                          writeq
 488
 489 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 490                                                                         \
 491 static inline void writes##bwlq(volatile void __iomem *mem,             \
 492                                 const void *addr, unsigned int count)   \
 493 {                                                                       \
 494         const volatile type *__addr = addr;                             \
 495                                                                         \
 496         while (count--) {                                               \
 497                 __mem_write##bwlq(*__addr, mem);                        \
 498                 __addr++;                                               \
 499         }                                                               \
 500 }                                                                       \
 501                                                                         \
 502 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 503                                unsigned int count)                      \
 504 {                                                                       \
 505         volatile type *__addr = addr;                                   \
 506                                                                         \
 507         while (count--) {                                               \
 508                 *__addr = __mem_read##bwlq(mem);                        \
 509                 __addr++;                                               \
 510         }                                                               \
 511 }
 512
 513 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 514                                                                         \
 515 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 516                               unsigned int count)                       \
 517 {                                                                       \
 518         const volatile type *__addr = addr;                             \
 519                                                                         \
 520         while (count--) {                                               \
 521                 __mem_out##bwlq(*__addr, port);                         \
 522                 __addr++;                                               \
 523         }                                                               \
 524 }                                                                       \
 525                                                                         \
 526 static inline void ins##bwlq(unsigned long port, void *addr,            \
 527                              unsigned int count)                        \
 528 {                                                                       \
 529         volatile type *__addr = addr;                                   \
 530                                                                         \
 531         while (count--) {                                               \
 532                 *__addr = __mem_in##bwlq(port);                         \
 533                 __addr++;                                               \
 534         }                                                               \
 535 }
 536
 537 #define BUILDSTRING(bwlq, type)                                         \
 538                                                                         \
 539 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 540 __BUILD_IOPORT_STRING(bwlq, type)
 541
 542 BUILDSTRING(b, u8)
 543 BUILDSTRING(w, u16)
 544 BUILDSTRING(l, u32)
 545 #ifdef CONFIG_64BIT
 546 BUILDSTRING(q, u64)
 547 #endif
 548
 549
 550 /* Depends on MIPS II instruction set */
 551 #define mmiowb() asm volatile ("sync" ::: "memory")
 552
 553 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 554 {
 555         memset((void __force *) addr, val, count);
 556 }
 557 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 558 {
 559         memcpy(dst, (void __force *) src, count);
 560 }
 561 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 562 {
 563         memcpy((void __force *) dst, src, count);
 564 }
 565
 566 /*
 567  * Memory Mapped I/O
 568  */
 569 #define ioread8(addr)           readb(addr)
 570 #define ioread16(addr)          readw(addr)
 571 #define ioread32(addr)          readl(addr)
 572
 573 #define iowrite8(b,addr)        writeb(b,addr)
 574 #define iowrite16(w,addr)       writew(w,addr)
 575 #define iowrite32(l,addr)       writel(l,addr)
 576
 577 #define ioread8_rep(a,b,c)      readsb(a,b,c)
 578 #define ioread16_rep(a,b,c)     readsw(a,b,c)
 579 #define ioread32_rep(a,b,c)     readsl(a,b,c)
 580
 581 #define iowrite8_rep(a,b,c)     writesb(a,b,c)
 582 #define iowrite16_rep(a,b,c)    writesw(a,b,c)
 583 #define iowrite32_rep(a,b,c)    writesl(a,b,c)
 584
 585 /* Create a virtual mapping cookie for an IO port range */
 586 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 587 extern void ioport_unmap(void __iomem *);
 588
 589 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 590 struct pci_dev;
 591 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 592 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 593
 594 /*
 595  * ISA space is 'always mapped' on currently supported MIPS systems, no need
 596  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
 597  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 598  * are physical addresses. The following constant pointer can be
 599  * used as the IO-area pointer (it can be iounmapped as well, so the
 600  * analogy with PCI is quite large):
 601  */
 602 #define __ISA_IO_base ((char *)(isa_slot_offset))
 603
 604 #define isa_readb(a)            readb(__ISA_IO_base + (a))
 605 #define isa_readw(a)            readw(__ISA_IO_base + (a))
 606 #define isa_readl(a)            readl(__ISA_IO_base + (a))
 607 #define isa_readq(a)            readq(__ISA_IO_base + (a))
 608 #define isa_writeb(b,a)         writeb(b,__ISA_IO_base + (a))
 609 #define isa_writew(w,a)         writew(w,__ISA_IO_base + (a))
 610 #define isa_writel(l,a)         writel(l,__ISA_IO_base + (a))
 611 #define isa_writeq(q,a)         writeq(q,__ISA_IO_base + (a))
 612 #define isa_memset_io(a,b,c)    memset_io(__ISA_IO_base + (a),(b),(c))
 613 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
 614 #define isa_memcpy_toio(a,b,c)  memcpy_toio(__ISA_IO_base + (a),(b),(c))
 615
 616 /*
 617  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
 618  * just copy it. The net code will then do the checksum later.
 619  */
 620 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
 621 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
 622
 623 /*
 624  *     check_signature         -       find BIOS signatures
 625  *     @io_addr: mmio address to check
 626  *     @signature:  signature block
 627  *     @length: length of signature
 628  *
 629  *     Perform a signature comparison with the mmio address io_addr. This
 630  *     address should have been obtained by ioremap.
 631  *     Returns 1 on a match.
 632  */
 633 static inline int check_signature(char __iomem *io_addr,
 634         const unsigned char *signature, int length)
 635 {
 636         int retval = 0;
 637         do {
 638                 if (readb(io_addr) != *signature)
 639                         goto out;
 640                 io_addr++;
 641                 signature++;
 642                 length--;
 643         } while (length);
 644         retval = 1;
 645 out:
 646         return retval;
 647 }
 648
 649 /*
 650  * The caches on some architectures aren't dma-coherent and have need to
 651  * handle this in software.  There are three types of operations that
 652  * can be applied to dma buffers.
 653  *
 654  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 655  *    writing the content of the caches back to memory, if necessary.
 656  *    The function also invalidates the affected part of the caches as
 657  *    necessary before DMA transfers from outside to memory.
 658  *  - dma_cache_wback(start, size) makes caches and coherent by
 659  *    writing the content of the caches back to memory, if necessary.
 660  *    The function also invalidates the affected part of the caches as
 661  *    necessary before DMA transfers from outside to memory.
 662  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 663  *    caches.  Dirty lines of the caches may be written back or simply
 664  *    be discarded.  This operation is necessary before dma operations
 665  *    to the memory.
 666  */
 667 #ifdef CONFIG_DMA_NONCOHERENT
 668
 669 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 670 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 671 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 672
 673 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start,size)
 674 #define dma_cache_wback(start, size)            _dma_cache_wback(start,size)
 675 #define dma_cache_inv(start, size)              _dma_cache_inv(start,size)
 676
 677 #else /* Sane hardware */
 678
 679 #define dma_cache_wback_inv(start,size) \
 680         do { (void) (start); (void) (size); } while (0)
 681 #define dma_cache_wback(start,size)     \
 682         do { (void) (start); (void) (size); } while (0)
 683 #define dma_cache_inv(start,size)       \
 684         do { (void) (start); (void) (size); } while (0)
 685
 686 #endif /* CONFIG_DMA_NONCOHERENT */
 687
 688 /*
 689  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 690  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 691  * Assume the addresses are 8-byte aligned.
 692  */
 693 #ifdef __MIPSEB__
 694 #define __CSR_32_ADJUST 4
 695 #else
 696 #define __CSR_32_ADJUST 0
 697 #endif
 698
 699 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 700 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 701
 702 /*
 703  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 704  * access
 705  */
 706 #define xlate_dev_mem_ptr(p)    __va(p)
 707
 708 /*
 709  * Convert a virtual cached pointer to an uncached pointer
 710  */
 711 #define xlate_dev_kmem_ptr(p)   p
 712
 713 #endif /* _ASM_IO_H */