arch/arm/mach-at91rm9200/gpio.c

   1 /*
   2  * linux/arch/arm/mach-at91rm9200/gpio.c
   3  *
   4  * Copyright (C) 2005 HP Labs
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/mach/irq.h>
  19 #include <asm/arch/hardware.h>
  20 #include <asm/arch/gpio.h>
  21
  22 static const u32 pio_controller_offset[4] = {
  23         AT91_PIOA,
  24         AT91_PIOB,
  25         AT91_PIOC,
  26         AT91_PIOD,
  27 };
  28
  29 static inline void __iomem *pin_to_controller(unsigned pin)
  30 {
  31         void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
  32
  33         pin -= PIN_BASE;
  34         pin /= 32;
  35         if (likely(pin < BGA_GPIO_BANKS))
  36                 return sys_base + pio_controller_offset[pin];
  37
  38         return NULL;
  39 }
  40
  41 static inline unsigned pin_to_mask(unsigned pin)
  42 {
  43         pin -= PIN_BASE;
  44         return 1 << (pin % 32);
  45 }
  46
  47
  48 /*--------------------------------------------------------------------------*/
  49
  50 /* Not all hardware capabilities are exposed through these calls; they
  51  * only encapsulate the most common features and modes.  (So if you
  52  * want to change signals in groups, do it directly.)
  53  *
  54  * Bootloaders will usually handle some of the pin multiplexing setup.
  55  * The intent is certainly that by the time Linux is fully booted, all
  56  * pins should have been fully initialized.  These setup calls should
  57  * only be used by board setup routines, or possibly in driver probe().
  58  *
  59  * For bootloaders doing all that setup, these calls could be inlined
  60  * as NOPs so Linux won't duplicate any setup code
  61  */
  62
  63
  64 /*
  65  * mux the pin to the "A" internal peripheral role.
  66  */
  67 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
  68 {
  69         void __iomem    *pio = pin_to_controller(pin);
  70         unsigned        mask = pin_to_mask(pin);
  71
  72         if (!pio)
  73                 return -EINVAL;
  74
  75         __raw_writel(mask, pio + PIO_IDR);
  76         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
  77         __raw_writel(mask, pio + PIO_ASR);
  78         __raw_writel(mask, pio + PIO_PDR);
  79         return 0;
  80 }
  81 EXPORT_SYMBOL(at91_set_A_periph);
  82
  83
  84 /*
  85  * mux the pin to the "B" internal peripheral role.
  86  */
  87 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
  88 {
  89         void __iomem    *pio = pin_to_controller(pin);
  90         unsigned        mask = pin_to_mask(pin);
  91
  92         if (!pio)
  93                 return -EINVAL;
  94
  95         __raw_writel(mask, pio + PIO_IDR);
  96         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
  97         __raw_writel(mask, pio + PIO_BSR);
  98         __raw_writel(mask, pio + PIO_PDR);
  99         return 0;
 100 }
 101 EXPORT_SYMBOL(at91_set_B_periph);
 102
 103
 104 /*
 105  * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 106  * configure it for an input.
 107  */
 108 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 109 {
 110         void __iomem    *pio = pin_to_controller(pin);
 111         unsigned        mask = pin_to_mask(pin);
 112
 113         if (!pio)
 114                 return -EINVAL;
 115
 116         __raw_writel(mask, pio + PIO_IDR);
 117         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 118         __raw_writel(mask, pio + PIO_ODR);
 119         __raw_writel(mask, pio + PIO_PER);
 120         return 0;
 121 }
 122 EXPORT_SYMBOL(at91_set_gpio_input);
 123
 124
 125 /*
 126  * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 127  * and configure it for an output.
 128  */
 129 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 130 {
 131         void __iomem    *pio = pin_to_controller(pin);
 132         unsigned        mask = pin_to_mask(pin);
 133
 134         if (!pio)
 135                 return -EINVAL;
 136
 137         __raw_writel(mask, pio + PIO_IDR);
 138         __raw_writel(mask, pio + PIO_PUDR);
 139         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 140         __raw_writel(mask, pio + PIO_OER);
 141         __raw_writel(mask, pio + PIO_PER);
 142         return 0;
 143 }
 144 EXPORT_SYMBOL(at91_set_gpio_output);
 145
 146
 147 /*
 148  * enable/disable the glitch filter; mostly used with IRQ handling.
 149  */
 150 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 151 {
 152         void __iomem    *pio = pin_to_controller(pin);
 153         unsigned        mask = pin_to_mask(pin);
 154
 155         if (!pio)
 156                 return -EINVAL;
 157         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 158         return 0;
 159 }
 160 EXPORT_SYMBOL(at91_set_deglitch);
 161
 162 /*
 163  * enable/disable the multi-driver; This is only valid for output and
 164  * allows the output pin to run as an open collector output.
 165  */
 166 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 167 {
 168         void __iomem    *pio = pin_to_controller(pin);
 169         unsigned        mask = pin_to_mask(pin);
 170
 171         if (!pio)
 172                 return -EINVAL;
 173
 174         __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
 175         return 0;
 176 }
 177 EXPORT_SYMBOL(at91_set_multi_drive);
 178
 179 /*--------------------------------------------------------------------------*/
 180
 181
 182 /*
 183  * assuming the pin is muxed as a gpio output, set its value.
 184  */
 185 int at91_set_gpio_value(unsigned pin, int value)
 186 {
 187         void __iomem    *pio = pin_to_controller(pin);
 188         unsigned        mask = pin_to_mask(pin);
 189
 190         if (!pio)
 191                 return -EINVAL;
 192         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 193         return 0;
 194 }
 195 EXPORT_SYMBOL(at91_set_gpio_value);
 196
 197
 198 /*
 199  * read the pin's value (works even if it's not muxed as a gpio).
 200  */
 201 int at91_get_gpio_value(unsigned pin)
 202 {
 203         void __iomem    *pio = pin_to_controller(pin);
 204         unsigned        mask = pin_to_mask(pin);
 205         u32             pdsr;
 206
 207         if (!pio)
 208                 return -EINVAL;
 209         pdsr = __raw_readl(pio + PIO_PDSR);
 210         return (pdsr & mask) != 0;
 211 }
 212 EXPORT_SYMBOL(at91_get_gpio_value);
 213
 214 /*--------------------------------------------------------------------------*/
 215
 216
 217 /* Several AIC controller irqs are dispatched through this GPIO handler.
 218  * To use any AT91_PIN_* as an externally triggered IRQ, first call
 219  * at91_set_gpio_input() then maybe enable its glitch filter.
 220  * Then just request_irq() with the pin ID; it works like any ARM IRQ
 221  * handler, though it always triggers on rising and falling edges.
 222  *
 223  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 224  * configuring them with at91_set_a_periph() or at91_set_b_periph().
 225  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 226  */
 227
 228 static void gpio_irq_mask(unsigned pin)
 229 {
 230         void __iomem    *pio = pin_to_controller(pin);
 231         unsigned        mask = pin_to_mask(pin);
 232
 233         if (pio)
 234                 __raw_writel(mask, pio + PIO_IDR);
 235 }
 236
 237 static void gpio_irq_unmask(unsigned pin)
 238 {
 239         void __iomem    *pio = pin_to_controller(pin);
 240         unsigned        mask = pin_to_mask(pin);
 241
 242         if (pio)
 243                 __raw_writel(mask, pio + PIO_IER);
 244 }
 245
 246 static int gpio_irq_type(unsigned pin, unsigned type)
 247 {
 248         return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
 249 }
 250
 251 static struct irqchip gpio_irqchip = {
 252         .mask           = gpio_irq_mask,
 253         .unmask         = gpio_irq_unmask,
 254         .set_type       = gpio_irq_type,
 255 };
 256
 257 static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
 258 {
 259         unsigned        pin;
 260         struct irqdesc  *gpio;
 261         void __iomem    *pio;
 262         u32             isr;
 263
 264         pio = desc->base;
 265
 266         /* temporarily mask (level sensitive) parent IRQ */
 267         desc->chip->ack(irq);
 268         for (;;) {
 269                 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
 270                 if (!isr)
 271                         break;
 272
 273                 pin = (unsigned) desc->data;
 274                 gpio = &irq_desc[pin];
 275
 276                 while (isr) {
 277                         if (isr & 1) {
 278                                 if (unlikely(gpio->disable_depth)) {
 279                                         /*
 280                                          * The core ARM interrupt handler lazily disables IRQs so
 281                                          * another IRQ must be generated before it actually gets
 282                                          * here to be disabled on the GPIO controller.
 283                                          */
 284                                         gpio_irq_mask(pin);
 285                                 }
 286                                 else
 287                                         gpio->handle(pin, gpio, regs);
 288                         }
 289                         pin++;
 290                         gpio++;
 291                         isr >>= 1;
 292                 }
 293         }
 294         desc->chip->unmask(irq);
 295         /* now it may re-trigger */
 296 }
 297
 298 /* call this from board-specific init_irq */
 299 void __init at91_gpio_irq_setup(unsigned banks)
 300 {
 301         unsigned        pioc, pin, id;
 302
 303         if (banks > 4)
 304                 banks = 4;
 305         for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
 306                         pioc < banks;
 307                         pioc++, id++) {
 308                 void __iomem    *controller;
 309                 unsigned        i;
 310
 311                 controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
 312                 __raw_writel(~0, controller + PIO_IDR);
 313
 314                 set_irq_data(id, (void *) pin);
 315                 set_irq_chipdata(id, controller);
 316
 317                 for (i = 0; i < 32; i++, pin++) {
 318                         set_irq_chip(pin, &gpio_irqchip);
 319                         set_irq_handler(pin, do_simple_IRQ);
 320                         set_irq_flags(pin, IRQF_VALID);
 321                 }
 322
 323                 set_irq_chained_handler(id, gpio_irq_handler);
 324
 325                 /* enable the PIO peripheral clock */
 326                 at91_sys_write(AT91_PMC_PCER, 1 << id);
 327         }
 328         pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
 329 }