arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/hardware.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/leds.h>
  35 #include <asm/hardware/arm_timer.h>
  36 #include <asm/hardware/icst307.h>
  37
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/flash.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/time.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/mmc.h>
  44
  45 #include <asm/hardware/gic.h>
  46
  47 #include "core.h"
  48 #include "clock.h"
  49
  50 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  51
  52 /*
  53  * This is the RealView sched_clock implementation.  This has
  54  * a resolution of 41.7ns, and a maximum value of about 179s.
  55  */
  56 unsigned long long sched_clock(void)
  57 {
  58         unsigned long long v;
  59
  60         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  61         do_div(v, 3);
  62
  63         return v;
  64 }
  65
  66
  67 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  68
  69 static int realview_flash_init(void)
  70 {
  71         u32 val;
  72
  73         val = __raw_readl(REALVIEW_FLASHCTRL);
  74         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  75         __raw_writel(val, REALVIEW_FLASHCTRL);
  76
  77         return 0;
  78 }
  79
  80 static void realview_flash_exit(void)
  81 {
  82         u32 val;
  83
  84         val = __raw_readl(REALVIEW_FLASHCTRL);
  85         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  86         __raw_writel(val, REALVIEW_FLASHCTRL);
  87 }
  88
  89 static void realview_flash_set_vpp(int on)
  90 {
  91         u32 val;
  92
  93         val = __raw_readl(REALVIEW_FLASHCTRL);
  94         if (on)
  95                 val |= REALVIEW_FLASHPROG_FLVPPEN;
  96         else
  97                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  98         __raw_writel(val, REALVIEW_FLASHCTRL);
  99 }
 100
 101 static struct flash_platform_data realview_flash_data = {
 102         .map_name               = "cfi_probe",
 103         .width                  = 4,
 104         .init                   = realview_flash_init,
 105         .exit                   = realview_flash_exit,
 106         .set_vpp                = realview_flash_set_vpp,
 107 };
 108
 109 static struct resource realview_flash_resource = {
 110         .start                  = REALVIEW_FLASH_BASE,
 111         .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
 112         .flags                  = IORESOURCE_MEM,
 113 };
 114
 115 struct platform_device realview_flash_device = {
 116         .name                   = "armflash",
 117         .id                     = 0,
 118         .dev                    = {
 119                 .platform_data  = &realview_flash_data,
 120         },
 121         .num_resources          = 1,
 122         .resource               = &realview_flash_resource,
 123 };
 124
 125 static struct resource realview_smc91x_resources[] = {
 126         [0] = {
 127                 .start          = REALVIEW_ETH_BASE,
 128                 .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
 129                 .flags          = IORESOURCE_MEM,
 130         },
 131         [1] = {
 132                 .start          = IRQ_ETH,
 133                 .end            = IRQ_ETH,
 134                 .flags          = IORESOURCE_IRQ,
 135         },
 136 };
 137
 138 struct platform_device realview_smc91x_device = {
 139         .name           = "smc91x",
 140         .id             = 0,
 141         .num_resources  = ARRAY_SIZE(realview_smc91x_resources),
 142         .resource       = realview_smc91x_resources,
 143 };
 144
 145 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 146
 147 static unsigned int realview_mmc_status(struct device *dev)
 148 {
 149         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 150         u32 mask;
 151
 152         if (adev->res.start == REALVIEW_MMCI0_BASE)
 153                 mask = 1;
 154         else
 155                 mask = 2;
 156
 157         return readl(REALVIEW_SYSMCI) & mask;
 158 }
 159
 160 struct mmc_platform_data realview_mmc0_plat_data = {
 161         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 162         .status         = realview_mmc_status,
 163 };
 164
 165 struct mmc_platform_data realview_mmc1_plat_data = {
 166         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 167         .status         = realview_mmc_status,
 168 };
 169
 170 /*
 171  * Clock handling
 172  */
 173 static const struct icst307_params realview_oscvco_params = {
 174         .ref            = 24000,
 175         .vco_max        = 200000,
 176         .vd_min         = 4 + 8,
 177         .vd_max         = 511 + 8,
 178         .rd_min         = 1 + 2,
 179         .rd_max         = 127 + 2,
 180 };
 181
 182 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 183 {
 184         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 185         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 186         u32 val;
 187
 188         val = readl(sys_osc) & ~0x7ffff;
 189         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 190
 191         writel(0xa05f, sys_lock);
 192         writel(val, sys_osc);
 193         writel(0, sys_lock);
 194 }
 195
 196 struct clk realview_clcd_clk = {
 197         .name   = "CLCDCLK",
 198         .params = &realview_oscvco_params,
 199         .setvco = realview_oscvco_set,
 200 };
 201
 202 /*
 203  * CLCD support.
 204  */
 205 #define SYS_CLCD_NLCDIOON       (1 << 2)
 206 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 207 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 208 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 209 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 210 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 211 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 212 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 213 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 214
 215 static struct clcd_panel vga = {
 216         .mode           = {
 217                 .name           = "VGA",
 218                 .refresh        = 60,
 219                 .xres           = 640,
 220                 .yres           = 480,
 221                 .pixclock       = 39721,
 222                 .left_margin    = 40,
 223                 .right_margin   = 24,
 224                 .upper_margin   = 32,
 225                 .lower_margin   = 11,
 226                 .hsync_len      = 96,
 227                 .vsync_len      = 2,
 228                 .sync           = 0,
 229                 .vmode          = FB_VMODE_NONINTERLACED,
 230         },
 231         .width          = -1,
 232         .height         = -1,
 233         .tim2           = TIM2_BCD | TIM2_IPC,
 234         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 235         .bpp            = 16,
 236 };
 237
 238 static struct clcd_panel sanyo_3_8_in = {
 239         .mode           = {
 240                 .name           = "Sanyo QVGA",
 241                 .refresh        = 116,
 242                 .xres           = 320,
 243                 .yres           = 240,
 244                 .pixclock       = 100000,
 245                 .left_margin    = 6,
 246                 .right_margin   = 6,
 247                 .upper_margin   = 5,
 248                 .lower_margin   = 5,
 249                 .hsync_len      = 6,
 250                 .vsync_len      = 6,
 251                 .sync           = 0,
 252                 .vmode          = FB_VMODE_NONINTERLACED,
 253         },
 254         .width          = -1,
 255         .height         = -1,
 256         .tim2           = TIM2_BCD,
 257         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 258         .bpp            = 16,
 259 };
 260
 261 static struct clcd_panel sanyo_2_5_in = {
 262         .mode           = {
 263                 .name           = "Sanyo QVGA Portrait",
 264                 .refresh        = 116,
 265                 .xres           = 240,
 266                 .yres           = 320,
 267                 .pixclock       = 100000,
 268                 .left_margin    = 20,
 269                 .right_margin   = 10,
 270                 .upper_margin   = 2,
 271                 .lower_margin   = 2,
 272                 .hsync_len      = 10,
 273                 .vsync_len      = 2,
 274                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 275                 .vmode          = FB_VMODE_NONINTERLACED,
 276         },
 277         .width          = -1,
 278         .height         = -1,
 279         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 280         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 281         .bpp            = 16,
 282 };
 283
 284 static struct clcd_panel epson_2_2_in = {
 285         .mode           = {
 286                 .name           = "Epson QCIF",
 287                 .refresh        = 390,
 288                 .xres           = 176,
 289                 .yres           = 220,
 290                 .pixclock       = 62500,
 291                 .left_margin    = 3,
 292                 .right_margin   = 2,
 293                 .upper_margin   = 1,
 294                 .lower_margin   = 0,
 295                 .hsync_len      = 3,
 296                 .vsync_len      = 2,
 297                 .sync           = 0,
 298                 .vmode          = FB_VMODE_NONINTERLACED,
 299         },
 300         .width          = -1,
 301         .height         = -1,
 302         .tim2           = TIM2_BCD | TIM2_IPC,
 303         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 304         .bpp            = 16,
 305 };
 306
 307 /*
 308  * Detect which LCD panel is connected, and return the appropriate
 309  * clcd_panel structure.  Note: we do not have any information on
 310  * the required timings for the 8.4in panel, so we presently assume
 311  * VGA timings.
 312  */
 313 static struct clcd_panel *realview_clcd_panel(void)
 314 {
 315         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 316         struct clcd_panel *panel = &vga;
 317         u32 val;
 318
 319         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 320         if (val == SYS_CLCD_ID_SANYO_3_8)
 321                 panel = &sanyo_3_8_in;
 322         else if (val == SYS_CLCD_ID_SANYO_2_5)
 323                 panel = &sanyo_2_5_in;
 324         else if (val == SYS_CLCD_ID_EPSON_2_2)
 325                 panel = &epson_2_2_in;
 326         else if (val == SYS_CLCD_ID_VGA)
 327                 panel = &vga;
 328         else {
 329                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 330                         val);
 331                 panel = &vga;
 332         }
 333
 334         return panel;
 335 }
 336
 337 /*
 338  * Disable all display connectors on the interface module.
 339  */
 340 static void realview_clcd_disable(struct clcd_fb *fb)
 341 {
 342         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 343         u32 val;
 344
 345         val = readl(sys_clcd);
 346         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 347         writel(val, sys_clcd);
 348 }
 349
 350 /*
 351  * Enable the relevant connector on the interface module.
 352  */
 353 static void realview_clcd_enable(struct clcd_fb *fb)
 354 {
 355         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 356         u32 val;
 357
 358         /*
 359          * Enable the PSUs
 360          */
 361         val = readl(sys_clcd);
 362         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 363         writel(val, sys_clcd);
 364 }
 365
 366 static unsigned long framesize = SZ_1M;
 367
 368 static int realview_clcd_setup(struct clcd_fb *fb)
 369 {
 370         dma_addr_t dma;
 371
 372         fb->panel               = realview_clcd_panel();
 373
 374         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 375                                                     &dma, GFP_KERNEL);
 376         if (!fb->fb.screen_base) {
 377                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 378                 return -ENOMEM;
 379         }
 380
 381         fb->fb.fix.smem_start   = dma;
 382         fb->fb.fix.smem_len     = framesize;
 383
 384         return 0;
 385 }
 386
 387 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 388 {
 389         return dma_mmap_writecombine(&fb->dev->dev, vma,
 390                                      fb->fb.screen_base,
 391                                      fb->fb.fix.smem_start,
 392                                      fb->fb.fix.smem_len);
 393 }
 394
 395 static void realview_clcd_remove(struct clcd_fb *fb)
 396 {
 397         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 398                               fb->fb.screen_base, fb->fb.fix.smem_start);
 399 }
 400
 401 struct clcd_board clcd_plat_data = {
 402         .name           = "RealView",
 403         .check          = clcdfb_check,
 404         .decode         = clcdfb_decode,
 405         .disable        = realview_clcd_disable,
 406         .enable         = realview_clcd_enable,
 407         .setup          = realview_clcd_setup,
 408         .mmap           = realview_clcd_mmap,
 409         .remove         = realview_clcd_remove,
 410 };
 411
 412 #ifdef CONFIG_LEDS
 413 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 414
 415 void realview_leds_event(led_event_t ledevt)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         local_irq_save(flags);
 421         val = readl(VA_LEDS_BASE);
 422
 423         switch (ledevt) {
 424         case led_idle_start:
 425                 val = val & ~REALVIEW_SYS_LED0;
 426                 break;
 427
 428         case led_idle_end:
 429                 val = val | REALVIEW_SYS_LED0;
 430                 break;
 431
 432         case led_timer:
 433                 val = val ^ REALVIEW_SYS_LED1;
 434                 break;
 435
 436         case led_halted:
 437                 val = 0;
 438                 break;
 439
 440         default:
 441                 break;
 442         }
 443
 444         writel(val, VA_LEDS_BASE);
 445         local_irq_restore(flags);
 446 }
 447 #endif  /* CONFIG_LEDS */
 448
 449 /*
 450  * Where is the timer (VA)?
 451  */
 452 #define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
 453 #define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
 454 #define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
 455 #define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
 456
 457 /*
 458  * How long is the timer interval?
 459  */
 460 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 461 #if TIMER_INTERVAL >= 0x100000
 462 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 463 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 464 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 465 #elif TIMER_INTERVAL >= 0x10000
 466 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 467 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 468 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 469 #else
 470 #define TIMER_RELOAD    (TIMER_INTERVAL)
 471 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 472 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 473 #endif
 474
 475 /*
 476  * Returns number of ms since last clock interrupt.  Note that interrupts
 477  * will have been disabled by do_gettimeoffset()
 478  */
 479 static unsigned long realview_gettimeoffset(void)
 480 {
 481         unsigned long ticks1, ticks2, status;
 482
 483         /*
 484          * Get the current number of ticks.  Note that there is a race
 485          * condition between us reading the timer and checking for
 486          * an interrupt.  We get around this by ensuring that the
 487          * counter has not reloaded between our two reads.
 488          */
 489         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 490         do {
 491                 ticks1 = ticks2;
 492                 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
 493                                      + ((IRQ_TIMERINT0_1 >> 5) << 2));
 494                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 495         } while (ticks2 > ticks1);
 496
 497         /*
 498          * Number of ticks since last interrupt.
 499          */
 500         ticks1 = TIMER_RELOAD - ticks2;
 501
 502         /*
 503          * Interrupt pending?  If so, we've reloaded once already.
 504          *
 505          * FIXME: Need to check this is effectively timer 0 that expires
 506          */
 507         if (status & IRQMASK_TIMERINT0_1)
 508                 ticks1 += TIMER_RELOAD;
 509
 510         /*
 511          * Convert the ticks to usecs
 512          */
 513         return TICKS2USECS(ticks1);
 514 }
 515
 516 /*
 517  * IRQ handler for the timer
 518  */
 519 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 520 {
 521         write_seqlock(&xtime_lock);
 522
 523         // ...clear the interrupt
 524         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 525
 526         timer_tick(regs);
 527
 528 #if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
 529         smp_send_timer();
 530         update_process_times(user_mode(regs));
 531 #endif
 532
 533         write_sequnlock(&xtime_lock);
 534
 535         return IRQ_HANDLED;
 536 }
 537
 538 static struct irqaction realview_timer_irq = {
 539         .name           = "RealView Timer Tick",
 540         .flags          = SA_INTERRUPT | SA_TIMER,
 541         .handler        = realview_timer_interrupt,
 542 };
 543
 544 /*
 545  * Set up timer interrupt, and return the current time in seconds.
 546  */
 547 static void __init realview_timer_init(void)
 548 {
 549         u32 val;
 550
 551         /*
 552          * set clock frequency:
 553          *      REALVIEW_REFCLK is 32KHz
 554          *      REALVIEW_TIMCLK is 1MHz
 555          */
 556         val = readl(__io_address(REALVIEW_SCTL_BASE));
 557         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 558                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 559                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 560                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 561                __io_address(REALVIEW_SCTL_BASE));
 562
 563         /*
 564          * Initialise to a known state (all timers off)
 565          */
 566         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 567         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 568         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 569         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 570
 571         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 572         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
 573         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
 574                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
 575
 576         /*
 577          * Make irqs happen for the system timer
 578          */
 579         setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
 580 }
 581
 582 struct sys_timer realview_timer = {
 583         .init           = realview_timer_init,
 584         .offset         = realview_gettimeoffset,
 585 };