2 * ALSA modem driver for Intel ICH (i8x0) chipsets
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
6 * This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
7 * of ALSA ICH sound driver intel8x0.c .
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <sound/driver.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/slab.h>
33 #include <linux/moduleparam.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/ac97_codec.h>
37 #include <sound/info.h>
38 #include <sound/initval.h>
40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
42 MODULE_LICENSE("GPL");
43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
44 "{Intel,82901AB-ICH0},"
45 "{Intel,82801BA-ICH2},"
46 "{Intel,82801CA-ICH3},"
47 "{Intel,82801DB-ICH4},"
53 "{NVidia,NForce Modem},"
54 "{NVidia,NForce2 Modem},"
55 "{NVidia,NForce2s Modem},"
56 "{NVidia,NForce3 Modem},"
59 static int index
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
- 1)] = -2}; /* Exclude the first card */
60 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
61 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
62 static int ac97_clock
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
- 1)] = 0};
64 module_param_array(index
, int, NULL
, 0444);
65 MODULE_PARM_DESC(index
, "Index value for Intel i8x0 modemcard.");
66 module_param_array(id
, charp
, NULL
, 0444);
67 MODULE_PARM_DESC(id
, "ID string for Intel i8x0 modemcard.");
68 module_param_array(enable
, bool, NULL
, 0444);
69 MODULE_PARM_DESC(enable
, "Enable Intel i8x0 modemcard.");
70 module_param_array(ac97_clock
, int, NULL
, 0444);
71 MODULE_PARM_DESC(ac97_clock
, "AC'97 codec clock (0 = auto-detect).");
76 enum { DEVICE_INTEL
, DEVICE_SIS
, DEVICE_ALI
, DEVICE_NFORCE
};
78 #define ICHREG(x) ICH_REG_##x
80 #define DEFINE_REGSET(name,base) \
82 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
83 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
84 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
85 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
86 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
87 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
88 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
91 /* busmaster blocks */
92 DEFINE_REGSET(OFF
, 0); /* offset */
94 /* values for each busmaster block */
97 #define ICH_REG_LVI_MASK 0x1f
100 #define ICH_FIFOE 0x10 /* FIFO error */
101 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
102 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
103 #define ICH_CELV 0x02 /* current equals last valid */
104 #define ICH_DCH 0x01 /* DMA controller halted */
107 #define ICH_REG_PIV_MASK 0x1f /* mask */
110 #define ICH_IOCE 0x10 /* interrupt on completion enable */
111 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
112 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
113 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
114 #define ICH_STARTBM 0x01 /* start busmaster operation */
118 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
119 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
120 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
121 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
122 #define ICH_ACLINK 0x00000008 /* AClink shut off */
123 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
124 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
125 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
126 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */
127 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
128 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
129 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
130 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
131 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
132 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
133 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
134 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
135 #define ICH_MD3 0x00020000 /* modem power down semaphore */
136 #define ICH_AD3 0x00010000 /* audio power down semaphore */
137 #define ICH_RCS 0x00008000 /* read completion status */
138 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
139 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
140 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
141 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
142 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
143 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
144 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
145 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
146 #define ICH_POINT 0x00000040 /* playback interrupt */
147 #define ICH_PIINT 0x00000020 /* capture interrupt */
148 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
149 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
150 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
151 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
152 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
153 #define ICH_CAS 0x01 /* codec access semaphore */
155 #define ICH_MAX_FRAGS 32 /* max hw frags */
162 enum { ICHD_MDMIN
, ICHD_MDMOUT
, ICHD_MDMLAST
= ICHD_MDMOUT
};
163 enum { ALID_MDMIN
, ALID_MDMOUT
, ALID_MDMLAST
= ALID_MDMOUT
};
165 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
168 unsigned int ichd
; /* ich device number */
169 unsigned long reg_offset
; /* offset to bmaddr */
170 u32
*bdbar
; /* CPU address (32bit) */
171 unsigned int bdbar_addr
; /* PCI bus address (32bit) */
172 snd_pcm_substream_t
*substream
;
173 unsigned int physbuf
; /* physical address (32bit) */
175 unsigned int fragsize
;
176 unsigned int fragsize1
;
177 unsigned int position
;
184 unsigned int ack_bit
;
185 unsigned int roff_sr
;
186 unsigned int roff_picb
;
187 unsigned int int_sta_mask
; /* interrupt status mask */
188 unsigned int ali_slot
; /* ALI DMA slot */
192 typedef struct _snd_intel8x0m intel8x0_t
;
194 struct _snd_intel8x0m
{
195 unsigned int device_type
;
201 void __iomem
*remap_addr
;
202 unsigned int bm_mmio
;
203 unsigned long bmaddr
;
204 void __iomem
*remap_bmaddr
;
213 unsigned int in_ac97_init
: 1;
215 ac97_bus_t
*ac97_bus
;
220 struct snd_dma_buffer bdbars
;
222 u32 int_sta_reg
; /* interrupt status register */
223 u32 int_sta_mask
; /* interrupt status mask */
224 unsigned int pcm_pos_shift
;
227 static struct pci_device_id snd_intel8x0m_ids
[] = {
228 { 0x8086, 0x2416, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* 82801AA */
229 { 0x8086, 0x2426, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* 82901AB */
230 { 0x8086, 0x2446, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* 82801BA */
231 { 0x8086, 0x2486, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* ICH3 */
232 { 0x8086, 0x24c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* ICH4 */
233 { 0x8086, 0x24d6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* ICH5 */
234 { 0x8086, 0x266d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* ICH6 */
235 { 0x8086, 0x27dd, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* ICH7 */
236 { 0x8086, 0x7196, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* 440MX */
237 { 0x1022, 0x7446, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* AMD768 */
238 { 0x1039, 0x7013, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_SIS
}, /* SI7013 */
239 { 0x10de, 0x01c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_NFORCE
}, /* NFORCE */
240 { 0x10de, 0x0069, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_NFORCE
}, /* NFORCE2 */
241 { 0x10de, 0x0089, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_NFORCE
}, /* NFORCE2s */
242 { 0x10de, 0x00d9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_NFORCE
}, /* NFORCE3 */
244 { 0x1022, 0x746d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_INTEL
}, /* AMD8111 */
245 { 0x10b9, 0x5455, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, DEVICE_ALI
}, /* Ali5455 */
250 MODULE_DEVICE_TABLE(pci
, snd_intel8x0m_ids
);
253 * Lowlevel I/O - busmaster
256 static u8
igetbyte(intel8x0_t
*chip
, u32 offset
)
259 return readb(chip
->remap_bmaddr
+ offset
);
261 return inb(chip
->bmaddr
+ offset
);
264 static u16
igetword(intel8x0_t
*chip
, u32 offset
)
267 return readw(chip
->remap_bmaddr
+ offset
);
269 return inw(chip
->bmaddr
+ offset
);
272 static u32
igetdword(intel8x0_t
*chip
, u32 offset
)
275 return readl(chip
->remap_bmaddr
+ offset
);
277 return inl(chip
->bmaddr
+ offset
);
280 static void iputbyte(intel8x0_t
*chip
, u32 offset
, u8 val
)
283 writeb(val
, chip
->remap_bmaddr
+ offset
);
285 outb(val
, chip
->bmaddr
+ offset
);
288 static void iputword(intel8x0_t
*chip
, u32 offset
, u16 val
)
291 writew(val
, chip
->remap_bmaddr
+ offset
);
293 outw(val
, chip
->bmaddr
+ offset
);
296 static void iputdword(intel8x0_t
*chip
, u32 offset
, u32 val
)
299 writel(val
, chip
->remap_bmaddr
+ offset
);
301 outl(val
, chip
->bmaddr
+ offset
);
305 * Lowlevel I/O - AC'97 registers
308 static u16
iagetword(intel8x0_t
*chip
, u32 offset
)
311 return readw(chip
->remap_addr
+ offset
);
313 return inw(chip
->addr
+ offset
);
316 static void iaputword(intel8x0_t
*chip
, u32 offset
, u16 val
)
319 writew(val
, chip
->remap_addr
+ offset
);
321 outw(val
, chip
->addr
+ offset
);
329 * access to AC97 codec via normal i/o (for ICH and SIS7013)
332 /* return the GLOB_STA bit for the corresponding codec */
333 static unsigned int get_ich_codec_bit(intel8x0_t
*chip
, unsigned int codec
)
335 static unsigned int codec_bit
[3] = {
336 ICH_PCR
, ICH_SCR
, ICH_TCR
338 snd_assert(codec
< 3, return ICH_PCR
);
339 return codec_bit
[codec
];
342 static int snd_intel8x0m_codec_semaphore(intel8x0_t
*chip
, unsigned int codec
)
348 codec
= get_ich_codec_bit(chip
, codec
);
351 if ((igetdword(chip
, ICHREG(GLOB_STA
)) & codec
) == 0)
354 /* Anyone holding a semaphore for 1 msec should be shot... */
357 if (!(igetbyte(chip
, ICHREG(ACC_SEMA
)) & ICH_CAS
))
362 /* access to some forbidden (non existant) ac97 registers will not
363 * reset the semaphore. So even if you don't get the semaphore, still
364 * continue the access. We don't need the semaphore anyway. */
365 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
366 igetbyte(chip
, ICHREG(ACC_SEMA
)), igetdword(chip
, ICHREG(GLOB_STA
)));
367 iagetword(chip
, 0); /* clear semaphore flag */
368 /* I don't care about the semaphore */
372 static void snd_intel8x0_codec_write(ac97_t
*ac97
,
376 intel8x0_t
*chip
= ac97
->private_data
;
378 if (snd_intel8x0m_codec_semaphore(chip
, ac97
->num
) < 0) {
379 if (! chip
->in_ac97_init
)
380 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97
->num
, reg
);
382 iaputword(chip
, reg
+ ac97
->num
* 0x80, val
);
385 static unsigned short snd_intel8x0_codec_read(ac97_t
*ac97
,
388 intel8x0_t
*chip
= ac97
->private_data
;
392 if (snd_intel8x0m_codec_semaphore(chip
, ac97
->num
) < 0) {
393 if (! chip
->in_ac97_init
)
394 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97
->num
, reg
);
397 res
= iagetword(chip
, reg
+ ac97
->num
* 0x80);
398 if ((tmp
= igetdword(chip
, ICHREG(GLOB_STA
))) & ICH_RCS
) {
399 /* reset RCS and preserve other R/WC bits */
400 iputdword(chip
, ICHREG(GLOB_STA
), tmp
& ~(ICH_SRI
|ICH_PRI
|ICH_TRI
|ICH_GSCI
));
401 if (! chip
->in_ac97_init
)
402 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97
->num
, reg
);
406 if (reg
== AC97_GPIO_STATUS
)
407 iagetword(chip
, 0); /* clear semaphore */
415 static void snd_intel8x0_setup_periods(intel8x0_t
*chip
, ichdev_t
*ichdev
)
418 u32
*bdbar
= ichdev
->bdbar
;
419 unsigned long port
= ichdev
->reg_offset
;
421 iputdword(chip
, port
+ ICH_REG_OFF_BDBAR
, ichdev
->bdbar_addr
);
422 if (ichdev
->size
== ichdev
->fragsize
) {
423 ichdev
->ack_reload
= ichdev
->ack
= 2;
424 ichdev
->fragsize1
= ichdev
->fragsize
>> 1;
425 for (idx
= 0; idx
< (ICH_REG_LVI_MASK
+ 1) * 2; idx
+= 4) {
426 bdbar
[idx
+ 0] = cpu_to_le32(ichdev
->physbuf
);
427 bdbar
[idx
+ 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
428 ichdev
->fragsize1
>> chip
->pcm_pos_shift
);
429 bdbar
[idx
+ 2] = cpu_to_le32(ichdev
->physbuf
+ (ichdev
->size
>> 1));
430 bdbar
[idx
+ 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
431 ichdev
->fragsize1
>> chip
->pcm_pos_shift
);
435 ichdev
->ack_reload
= ichdev
->ack
= 1;
436 ichdev
->fragsize1
= ichdev
->fragsize
;
437 for (idx
= 0; idx
< (ICH_REG_LVI_MASK
+ 1) * 2; idx
+= 2) {
438 bdbar
[idx
+ 0] = cpu_to_le32(ichdev
->physbuf
+ (((idx
>> 1) * ichdev
->fragsize
) % ichdev
->size
));
439 bdbar
[idx
+ 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
440 ichdev
->fragsize
>> chip
->pcm_pos_shift
);
441 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
443 ichdev
->frags
= ichdev
->size
/ ichdev
->fragsize
;
445 iputbyte(chip
, port
+ ICH_REG_OFF_LVI
, ichdev
->lvi
= ICH_REG_LVI_MASK
);
447 iputbyte(chip
, port
+ ICH_REG_OFF_CIV
, 0);
448 ichdev
->lvi_frag
= ICH_REG_LVI_MASK
% ichdev
->frags
;
449 ichdev
->position
= 0;
451 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
452 ichdev
->lvi_frag
, ichdev
->frags
, ichdev
->fragsize
, ichdev
->fragsize1
);
454 /* clear interrupts */
455 iputbyte(chip
, port
+ ichdev
->roff_sr
, ICH_FIFOE
| ICH_BCIS
| ICH_LVBCI
);
462 static inline void snd_intel8x0_update(intel8x0_t
*chip
, ichdev_t
*ichdev
)
464 unsigned long port
= ichdev
->reg_offset
;
468 civ
= igetbyte(chip
, port
+ ICH_REG_OFF_CIV
);
469 if (civ
== ichdev
->civ
) {
470 // snd_printd("civ same %d\n", civ);
473 ichdev
->civ
&= ICH_REG_LVI_MASK
;
475 step
= civ
- ichdev
->civ
;
477 step
+= ICH_REG_LVI_MASK
+ 1;
479 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
483 ichdev
->position
+= step
* ichdev
->fragsize1
;
484 ichdev
->position
%= ichdev
->size
;
486 ichdev
->lvi
&= ICH_REG_LVI_MASK
;
487 iputbyte(chip
, port
+ ICH_REG_OFF_LVI
, ichdev
->lvi
);
488 for (i
= 0; i
< step
; i
++) {
490 ichdev
->lvi_frag
%= ichdev
->frags
;
491 ichdev
->bdbar
[ichdev
->lvi
* 2] = cpu_to_le32(ichdev
->physbuf
+ ichdev
->lvi_frag
* ichdev
->fragsize1
);
492 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
493 if (--ichdev
->ack
== 0) {
494 ichdev
->ack
= ichdev
->ack_reload
;
498 if (ack
&& ichdev
->substream
) {
499 spin_unlock(&chip
->reg_lock
);
500 snd_pcm_period_elapsed(ichdev
->substream
);
501 spin_lock(&chip
->reg_lock
);
503 iputbyte(chip
, port
+ ichdev
->roff_sr
, ICH_FIFOE
| ICH_BCIS
| ICH_LVBCI
);
506 static irqreturn_t
snd_intel8x0_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
508 intel8x0_t
*chip
= dev_id
;
513 spin_lock(&chip
->reg_lock
);
514 status
= igetdword(chip
, chip
->int_sta_reg
);
515 if (status
== 0xffffffff) { /* we are not yet resumed */
516 spin_unlock(&chip
->reg_lock
);
519 if ((status
& chip
->int_sta_mask
) == 0) {
521 iputdword(chip
, chip
->int_sta_reg
, status
);
522 spin_unlock(&chip
->reg_lock
);
526 for (i
= 0; i
< chip
->bdbars_count
; i
++) {
527 ichdev
= &chip
->ichd
[i
];
528 if (status
& ichdev
->int_sta_mask
)
529 snd_intel8x0_update(chip
, ichdev
);
533 iputdword(chip
, chip
->int_sta_reg
, status
& chip
->int_sta_mask
);
534 spin_unlock(&chip
->reg_lock
);
543 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t
*substream
, int cmd
)
545 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
546 ichdev_t
*ichdev
= get_ichdev(substream
);
547 unsigned char val
= 0;
548 unsigned long port
= ichdev
->reg_offset
;
551 case SNDRV_PCM_TRIGGER_START
:
552 case SNDRV_PCM_TRIGGER_RESUME
:
553 val
= ICH_IOCE
| ICH_STARTBM
;
555 case SNDRV_PCM_TRIGGER_STOP
:
556 case SNDRV_PCM_TRIGGER_SUSPEND
:
559 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
562 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
563 val
= ICH_IOCE
| ICH_STARTBM
;
568 iputbyte(chip
, port
+ ICH_REG_OFF_CR
, val
);
569 if (cmd
== SNDRV_PCM_TRIGGER_STOP
) {
570 /* wait until DMA stopped */
571 while (!(igetbyte(chip
, port
+ ichdev
->roff_sr
) & ICH_DCH
)) ;
572 /* reset whole DMA things */
573 iputbyte(chip
, port
+ ICH_REG_OFF_CR
, ICH_RESETREGS
);
578 static int snd_intel8x0_hw_params(snd_pcm_substream_t
* substream
,
579 snd_pcm_hw_params_t
* hw_params
)
581 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
584 static int snd_intel8x0_hw_free(snd_pcm_substream_t
* substream
)
586 return snd_pcm_lib_free_pages(substream
);
589 static snd_pcm_uframes_t
snd_intel8x0_pcm_pointer(snd_pcm_substream_t
* substream
)
591 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
592 ichdev_t
*ichdev
= get_ichdev(substream
);
595 ptr1
= igetword(chip
, ichdev
->reg_offset
+ ichdev
->roff_picb
) << chip
->pcm_pos_shift
;
597 ptr
= ichdev
->fragsize1
- ptr1
;
600 ptr
+= ichdev
->position
;
601 if (ptr
>= ichdev
->size
)
603 return bytes_to_frames(substream
->runtime
, ptr
);
606 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t
* substream
)
608 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
609 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
610 ichdev_t
*ichdev
= get_ichdev(substream
);
612 ichdev
->physbuf
= runtime
->dma_addr
;
613 ichdev
->size
= snd_pcm_lib_buffer_bytes(substream
);
614 ichdev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
615 snd_ac97_write(ichdev
->ac97
, AC97_LINE1_RATE
, runtime
->rate
);
616 snd_ac97_write(ichdev
->ac97
, AC97_LINE1_LEVEL
, 0);
617 snd_intel8x0_setup_periods(chip
, ichdev
);
621 static snd_pcm_hardware_t snd_intel8x0m_stream
=
623 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
624 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
625 SNDRV_PCM_INFO_MMAP_VALID
|
626 SNDRV_PCM_INFO_PAUSE
|
627 SNDRV_PCM_INFO_RESUME
),
628 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
629 .rates
= SNDRV_PCM_RATE_8000
| SNDRV_PCM_RATE_16000
| SNDRV_PCM_RATE_KNOT
,
634 .buffer_bytes_max
= 64 * 1024,
635 .period_bytes_min
= 32,
636 .period_bytes_max
= 64 * 1024,
643 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t
* substream
, ichdev_t
*ichdev
)
645 static unsigned int rates
[] = { 8000, 9600, 12000, 16000 };
646 static snd_pcm_hw_constraint_list_t hw_constraints_rates
= {
647 .count
= ARRAY_SIZE(rates
),
651 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
654 ichdev
->substream
= substream
;
655 runtime
->hw
= snd_intel8x0m_stream
;
656 err
= snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
, &hw_constraints_rates
);
659 runtime
->private_data
= ichdev
;
663 static int snd_intel8x0m_playback_open(snd_pcm_substream_t
* substream
)
665 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
667 return snd_intel8x0m_pcm_open(substream
, &chip
->ichd
[ICHD_MDMOUT
]);
670 static int snd_intel8x0m_playback_close(snd_pcm_substream_t
* substream
)
672 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
674 chip
->ichd
[ICHD_MDMOUT
].substream
= NULL
;
678 static int snd_intel8x0m_capture_open(snd_pcm_substream_t
* substream
)
680 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
682 return snd_intel8x0m_pcm_open(substream
, &chip
->ichd
[ICHD_MDMIN
]);
685 static int snd_intel8x0m_capture_close(snd_pcm_substream_t
* substream
)
687 intel8x0_t
*chip
= snd_pcm_substream_chip(substream
);
689 chip
->ichd
[ICHD_MDMIN
].substream
= NULL
;
694 static snd_pcm_ops_t snd_intel8x0m_playback_ops
= {
695 .open
= snd_intel8x0m_playback_open
,
696 .close
= snd_intel8x0m_playback_close
,
697 .ioctl
= snd_pcm_lib_ioctl
,
698 .hw_params
= snd_intel8x0_hw_params
,
699 .hw_free
= snd_intel8x0_hw_free
,
700 .prepare
= snd_intel8x0m_pcm_prepare
,
701 .trigger
= snd_intel8x0_pcm_trigger
,
702 .pointer
= snd_intel8x0_pcm_pointer
,
705 static snd_pcm_ops_t snd_intel8x0m_capture_ops
= {
706 .open
= snd_intel8x0m_capture_open
,
707 .close
= snd_intel8x0m_capture_close
,
708 .ioctl
= snd_pcm_lib_ioctl
,
709 .hw_params
= snd_intel8x0_hw_params
,
710 .hw_free
= snd_intel8x0_hw_free
,
711 .prepare
= snd_intel8x0m_pcm_prepare
,
712 .trigger
= snd_intel8x0_pcm_trigger
,
713 .pointer
= snd_intel8x0_pcm_pointer
,
717 struct ich_pcm_table
{
719 snd_pcm_ops_t
*playback_ops
;
720 snd_pcm_ops_t
*capture_ops
;
721 size_t prealloc_size
;
722 size_t prealloc_max_size
;
726 static int __devinit
snd_intel8x0_pcm1(intel8x0_t
*chip
, int device
, struct ich_pcm_table
*rec
)
733 sprintf(name
, "Intel ICH - %s", rec
->suffix
);
735 strcpy(name
, "Intel ICH");
736 err
= snd_pcm_new(chip
->card
, name
, device
,
737 rec
->playback_ops
? 1 : 0,
738 rec
->capture_ops
? 1 : 0, &pcm
);
742 if (rec
->playback_ops
)
743 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, rec
->playback_ops
);
744 if (rec
->capture_ops
)
745 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, rec
->capture_ops
);
747 pcm
->private_data
= chip
;
750 sprintf(pcm
->name
, "%s - %s", chip
->card
->shortname
, rec
->suffix
);
752 strcpy(pcm
->name
, chip
->card
->shortname
);
753 chip
->pcm
[device
] = pcm
;
755 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
756 snd_dma_pci_data(chip
->pci
),
758 rec
->prealloc_max_size
);
763 static struct ich_pcm_table intel_pcms
[] __devinitdata
= {
766 .playback_ops
= &snd_intel8x0m_playback_ops
,
767 .capture_ops
= &snd_intel8x0m_capture_ops
,
768 .prealloc_size
= 32 * 1024,
769 .prealloc_max_size
= 64 * 1024,
773 static int __devinit
snd_intel8x0_pcm(intel8x0_t
*chip
)
775 int i
, tblsize
, device
, err
;
776 struct ich_pcm_table
*tbl
, *rec
;
782 switch (chip
->device_type
) {
785 tblsize
= ARRAY_SIZE(nforce_pcms
);
789 tblsize
= ARRAY_SIZE(ali_pcms
);
798 for (i
= 0; i
< tblsize
; i
++) {
800 if (i
> 0 && rec
->ac97_idx
) {
801 /* activate PCM only when associated AC'97 codec */
802 if (! chip
->ichd
[rec
->ac97_idx
].ac97
)
805 err
= snd_intel8x0_pcm1(chip
, device
, rec
);
811 chip
->pcm_devs
= device
;
820 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t
*bus
)
822 intel8x0_t
*chip
= bus
->private_data
;
823 chip
->ac97_bus
= NULL
;
826 static void snd_intel8x0_mixer_free_ac97(ac97_t
*ac97
)
828 intel8x0_t
*chip
= ac97
->private_data
;
833 static int __devinit
snd_intel8x0_mixer(intel8x0_t
*chip
, int ac97_clock
)
836 ac97_template_t ac97
;
839 unsigned int glob_sta
= 0;
840 static ac97_bus_ops_t ops
= {
841 .write
= snd_intel8x0_codec_write
,
842 .read
= snd_intel8x0_codec_read
,
845 chip
->in_ac97_init
= 1;
847 memset(&ac97
, 0, sizeof(ac97
));
848 ac97
.private_data
= chip
;
849 ac97
.private_free
= snd_intel8x0_mixer_free_ac97
;
850 ac97
.scaps
= AC97_SCAP_SKIP_AUDIO
;
852 glob_sta
= igetdword(chip
, ICHREG(GLOB_STA
));
854 if ((err
= snd_ac97_bus(chip
->card
, 0, &ops
, chip
, &pbus
)) < 0)
856 pbus
->private_free
= snd_intel8x0_mixer_free_ac97_bus
;
857 pbus
->shared_type
= AC97_SHARED_TYPE_ICH
; /* shared with audio driver */
858 if (ac97_clock
>= 8000 && ac97_clock
<= 48000)
859 pbus
->clock
= ac97_clock
;
860 chip
->ac97_bus
= pbus
;
862 ac97
.pci
= chip
->pci
;
863 ac97
.num
= glob_sta
& ICH_SCR
? 1 : 0;
864 if ((err
= snd_ac97_mixer(pbus
, &ac97
, &x97
)) < 0) {
865 snd_printk(KERN_ERR
"Unable to initialize codec #%d\n", ac97
.num
);
871 if(ac97_is_modem(x97
) && !chip
->ichd
[ICHD_MDMIN
].ac97
) {
872 chip
->ichd
[ICHD_MDMIN
].ac97
= x97
;
873 chip
->ichd
[ICHD_MDMOUT
].ac97
= x97
;
876 chip
->in_ac97_init
= 0;
880 /* clear the cold-reset bit for the next chance */
881 if (chip
->device_type
!= DEVICE_ALI
)
882 iputdword(chip
, ICHREG(GLOB_CNT
), igetdword(chip
, ICHREG(GLOB_CNT
)) & ~ICH_AC97COLD
);
891 #define do_delay(chip) do {\
892 set_current_state(TASK_UNINTERRUPTIBLE);\
893 schedule_timeout(1);\
896 static int snd_intel8x0m_ich_chip_init(intel8x0_t
*chip
, int probing
)
898 unsigned long end_time
;
899 unsigned int cnt
, status
, nstatus
;
901 /* put logic to right state */
902 /* first clear status bits */
903 status
= ICH_RCS
| ICH_MIINT
| ICH_MOINT
;
904 cnt
= igetdword(chip
, ICHREG(GLOB_STA
));
905 iputdword(chip
, ICHREG(GLOB_STA
), cnt
& status
);
907 /* ACLink on, 2 channels */
908 cnt
= igetdword(chip
, ICHREG(GLOB_CNT
));
909 cnt
&= ~(ICH_ACLINK
);
910 /* finish cold or do warm reset */
911 cnt
|= (cnt
& ICH_AC97COLD
) == 0 ? ICH_AC97COLD
: ICH_AC97WARM
;
912 iputdword(chip
, ICHREG(GLOB_CNT
), cnt
);
913 end_time
= (jiffies
+ (HZ
/ 4)) + 1;
915 if ((igetdword(chip
, ICHREG(GLOB_CNT
)) & ICH_AC97WARM
) == 0)
918 } while (time_after_eq(end_time
, jiffies
));
919 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip
, ICHREG(GLOB_CNT
)));
924 /* wait for any codec ready status.
925 * Once it becomes ready it should remain ready
926 * as long as we do not disable the ac97 link.
928 end_time
= jiffies
+ HZ
;
930 status
= igetdword(chip
, ICHREG(GLOB_STA
)) & (ICH_PCR
| ICH_SCR
| ICH_TCR
);
934 } while (time_after_eq(end_time
, jiffies
));
936 /* no codec is found */
937 snd_printk(KERN_ERR
"codec_ready: codec is not ready [0x%x]\n", igetdword(chip
, ICHREG(GLOB_STA
)));
941 /* up to two codecs (modem cannot be tertiary with ICH4) */
942 nstatus
= ICH_PCR
| ICH_SCR
;
944 /* wait for other codecs ready status. */
945 end_time
= jiffies
+ HZ
/ 4;
946 while (status
!= nstatus
&& time_after_eq(end_time
, jiffies
)) {
948 status
|= igetdword(chip
, ICHREG(GLOB_STA
)) & nstatus
;
955 status
|= get_ich_codec_bit(chip
, chip
->ac97
->num
);
956 /* wait until all the probed codecs are ready */
957 end_time
= jiffies
+ HZ
;
959 nstatus
= igetdword(chip
, ICHREG(GLOB_STA
)) & (ICH_PCR
| ICH_SCR
| ICH_TCR
);
960 if (status
== nstatus
)
963 } while (time_after_eq(end_time
, jiffies
));
966 if (chip
->device_type
== DEVICE_SIS
) {
967 /* unmute the output on SIS7012 */
968 iputword(chip
, 0x4c, igetword(chip
, 0x4c) | 1);
974 static int snd_intel8x0_chip_init(intel8x0_t
*chip
, int probing
)
979 if ((err
= snd_intel8x0m_ich_chip_init(chip
, probing
)) < 0)
981 iagetword(chip
, 0); /* clear semaphore flag */
983 /* disable interrupts */
984 for (i
= 0; i
< chip
->bdbars_count
; i
++)
985 iputbyte(chip
, ICH_REG_OFF_CR
+ chip
->ichd
[i
].reg_offset
, 0x00);
987 for (i
= 0; i
< chip
->bdbars_count
; i
++)
988 iputbyte(chip
, ICH_REG_OFF_CR
+ chip
->ichd
[i
].reg_offset
, ICH_RESETREGS
);
989 /* initialize Buffer Descriptor Lists */
990 for (i
= 0; i
< chip
->bdbars_count
; i
++)
991 iputdword(chip
, ICH_REG_OFF_BDBAR
+ chip
->ichd
[i
].reg_offset
, chip
->ichd
[i
].bdbar_addr
);
995 static int snd_intel8x0_free(intel8x0_t
*chip
)
1001 /* disable interrupts */
1002 for (i
= 0; i
< chip
->bdbars_count
; i
++)
1003 iputbyte(chip
, ICH_REG_OFF_CR
+ chip
->ichd
[i
].reg_offset
, 0x00);
1004 /* reset channels */
1005 for (i
= 0; i
< chip
->bdbars_count
; i
++)
1006 iputbyte(chip
, ICH_REG_OFF_CR
+ chip
->ichd
[i
].reg_offset
, ICH_RESETREGS
);
1008 synchronize_irq(chip
->irq
);
1010 if (chip
->bdbars
.area
)
1011 snd_dma_free_pages(&chip
->bdbars
);
1012 if (chip
->remap_addr
)
1013 iounmap(chip
->remap_addr
);
1014 if (chip
->remap_bmaddr
)
1015 iounmap(chip
->remap_bmaddr
);
1017 free_irq(chip
->irq
, (void *)chip
);
1018 pci_release_regions(chip
->pci
);
1019 pci_disable_device(chip
->pci
);
1028 static int intel8x0m_suspend(snd_card_t
*card
, pm_message_t state
)
1030 intel8x0_t
*chip
= card
->pm_private_data
;
1033 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1034 snd_pcm_suspend_all(chip
->pcm
[i
]);
1036 snd_ac97_suspend(chip
->ac97
);
1037 pci_disable_device(chip
->pci
);
1041 static int intel8x0m_resume(snd_card_t
*card
)
1043 intel8x0_t
*chip
= card
->pm_private_data
;
1044 pci_enable_device(chip
->pci
);
1045 pci_set_master(chip
->pci
);
1046 snd_intel8x0_chip_init(chip
, 0);
1048 snd_ac97_resume(chip
->ac97
);
1052 #endif /* CONFIG_PM */
1054 static void snd_intel8x0m_proc_read(snd_info_entry_t
* entry
,
1055 snd_info_buffer_t
* buffer
)
1057 intel8x0_t
*chip
= entry
->private_data
;
1060 snd_iprintf(buffer
, "Intel8x0m\n\n");
1061 if (chip
->device_type
== DEVICE_ALI
)
1063 tmp
= igetdword(chip
, ICHREG(GLOB_STA
));
1064 snd_iprintf(buffer
, "Global control : 0x%08x\n", igetdword(chip
, ICHREG(GLOB_CNT
)));
1065 snd_iprintf(buffer
, "Global status : 0x%08x\n", tmp
);
1066 snd_iprintf(buffer
, "AC'97 codecs ready :%s%s%s%s\n",
1067 tmp
& ICH_PCR
? " primary" : "",
1068 tmp
& ICH_SCR
? " secondary" : "",
1069 tmp
& ICH_TCR
? " tertiary" : "",
1070 (tmp
& (ICH_PCR
| ICH_SCR
| ICH_TCR
)) == 0 ? " none" : "");
1073 static void __devinit
snd_intel8x0m_proc_init(intel8x0_t
* chip
)
1075 snd_info_entry_t
*entry
;
1077 if (! snd_card_proc_new(chip
->card
, "intel8x0m", &entry
))
1078 snd_info_set_text_ops(entry
, chip
, 1024, snd_intel8x0m_proc_read
);
1081 static int snd_intel8x0_dev_free(snd_device_t
*device
)
1083 intel8x0_t
*chip
= device
->device_data
;
1084 return snd_intel8x0_free(chip
);
1087 struct ich_reg_info
{
1088 unsigned int int_sta_mask
;
1089 unsigned int offset
;
1092 static int __devinit
snd_intel8x0m_create(snd_card_t
* card
,
1093 struct pci_dev
*pci
,
1094 unsigned long device_type
,
1095 intel8x0_t
** r_intel8x0
)
1100 unsigned int int_sta_masks
;
1102 static snd_device_ops_t ops
= {
1103 .dev_free
= snd_intel8x0_dev_free
,
1105 static struct ich_reg_info intel_regs
[2] = {
1107 { ICH_MOINT
, 0x10 },
1109 struct ich_reg_info
*tbl
;
1113 if ((err
= pci_enable_device(pci
)) < 0)
1116 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1118 pci_disable_device(pci
);
1121 spin_lock_init(&chip
->reg_lock
);
1122 chip
->device_type
= device_type
;
1127 if ((err
= pci_request_regions(pci
, card
->shortname
)) < 0) {
1129 pci_disable_device(pci
);
1133 if (device_type
== DEVICE_ALI
) {
1134 /* ALI5455 has no ac97 region */
1135 chip
->bmaddr
= pci_resource_start(pci
, 0);
1139 if (pci_resource_flags(pci
, 2) & IORESOURCE_MEM
) { /* ICH4 and Nforce */
1141 chip
->addr
= pci_resource_start(pci
, 2);
1142 chip
->remap_addr
= ioremap_nocache(chip
->addr
,
1143 pci_resource_len(pci
, 2));
1144 if (chip
->remap_addr
== NULL
) {
1145 snd_printk("AC'97 space ioremap problem\n");
1146 snd_intel8x0_free(chip
);
1150 chip
->addr
= pci_resource_start(pci
, 0);
1152 if (pci_resource_flags(pci
, 3) & IORESOURCE_MEM
) { /* ICH4 */
1154 chip
->bmaddr
= pci_resource_start(pci
, 3);
1155 chip
->remap_bmaddr
= ioremap_nocache(chip
->bmaddr
,
1156 pci_resource_len(pci
, 3));
1157 if (chip
->remap_bmaddr
== NULL
) {
1158 snd_printk("Controller space ioremap problem\n");
1159 snd_intel8x0_free(chip
);
1163 chip
->bmaddr
= pci_resource_start(pci
, 1);
1167 if (request_irq(pci
->irq
, snd_intel8x0_interrupt
, SA_INTERRUPT
|SA_SHIRQ
, card
->shortname
, (void *)chip
)) {
1168 snd_printk("unable to grab IRQ %d\n", pci
->irq
);
1169 snd_intel8x0_free(chip
);
1172 chip
->irq
= pci
->irq
;
1173 pci_set_master(pci
);
1174 synchronize_irq(chip
->irq
);
1176 /* initialize offsets */
1177 chip
->bdbars_count
= 2;
1180 for (i
= 0; i
< chip
->bdbars_count
; i
++) {
1181 ichdev
= &chip
->ichd
[i
];
1183 ichdev
->reg_offset
= tbl
[i
].offset
;
1184 ichdev
->int_sta_mask
= tbl
[i
].int_sta_mask
;
1185 if (device_type
== DEVICE_SIS
) {
1186 /* SiS 7013 swaps the registers */
1187 ichdev
->roff_sr
= ICH_REG_OFF_PICB
;
1188 ichdev
->roff_picb
= ICH_REG_OFF_SR
;
1190 ichdev
->roff_sr
= ICH_REG_OFF_SR
;
1191 ichdev
->roff_picb
= ICH_REG_OFF_PICB
;
1193 if (device_type
== DEVICE_ALI
)
1194 ichdev
->ali_slot
= (ichdev
->reg_offset
- 0x40) / 0x10;
1196 /* SIS7013 handles the pcm data in bytes, others are in words */
1197 chip
->pcm_pos_shift
= (device_type
== DEVICE_SIS
) ? 0 : 1;
1199 /* allocate buffer descriptor lists */
1200 /* the start of each lists must be aligned to 8 bytes */
1201 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(pci
),
1202 chip
->bdbars_count
* sizeof(u32
) * ICH_MAX_FRAGS
* 2,
1203 &chip
->bdbars
) < 0) {
1204 snd_intel8x0_free(chip
);
1207 /* tables must be aligned to 8 bytes here, but the kernel pages
1208 are much bigger, so we don't care (on i386) */
1210 for (i
= 0; i
< chip
->bdbars_count
; i
++) {
1211 ichdev
= &chip
->ichd
[i
];
1212 ichdev
->bdbar
= ((u32
*)chip
->bdbars
.area
) + (i
* ICH_MAX_FRAGS
* 2);
1213 ichdev
->bdbar_addr
= chip
->bdbars
.addr
+ (i
* sizeof(u32
) * ICH_MAX_FRAGS
* 2);
1214 int_sta_masks
|= ichdev
->int_sta_mask
;
1216 chip
->int_sta_reg
= ICH_REG_GLOB_STA
;
1217 chip
->int_sta_mask
= int_sta_masks
;
1219 if ((err
= snd_intel8x0_chip_init(chip
, 1)) < 0) {
1220 snd_intel8x0_free(chip
);
1224 snd_card_set_pm_callback(card
, intel8x0m_suspend
, intel8x0m_resume
, chip
);
1226 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) < 0) {
1227 snd_intel8x0_free(chip
);
1231 snd_card_set_dev(card
, &pci
->dev
);
1237 static struct shortname_table
{
1240 } shortnames
[] __devinitdata
= {
1241 { PCI_DEVICE_ID_INTEL_82801AA_6
, "Intel 82801AA-ICH" },
1242 { PCI_DEVICE_ID_INTEL_82801AB_6
, "Intel 82901AB-ICH0" },
1243 { PCI_DEVICE_ID_INTEL_82801BA_6
, "Intel 82801BA-ICH2" },
1244 { PCI_DEVICE_ID_INTEL_440MX_6
, "Intel 440MX" },
1245 { PCI_DEVICE_ID_INTEL_82801CA_6
, "Intel 82801CA-ICH3" },
1246 { PCI_DEVICE_ID_INTEL_82801DB_6
, "Intel 82801DB-ICH4" },
1247 { PCI_DEVICE_ID_INTEL_82801EB_6
, "Intel ICH5" },
1248 { PCI_DEVICE_ID_INTEL_ICH6_17
, "Intel ICH6" },
1249 { PCI_DEVICE_ID_INTEL_ICH7_19
, "Intel ICH7" },
1250 { 0x7446, "AMD AMD768" },
1251 { PCI_DEVICE_ID_SI_7013
, "SiS SI7013" },
1252 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM
, "NVidia nForce" },
1253 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
, "NVidia nForce2" },
1254 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
, "NVidia nForce2s" },
1255 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
, "NVidia nForce3" },
1257 { 0x5455, "ALi M5455" },
1258 { 0x746d, "AMD AMD8111" },
1263 static int __devinit
snd_intel8x0m_probe(struct pci_dev
*pci
,
1264 const struct pci_device_id
*pci_id
)
1270 struct shortname_table
*name
;
1272 if (dev
>= SNDRV_CARDS
)
1279 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
1283 strcpy(card
->driver
, "ICH-MODEM");
1284 strcpy(card
->shortname
, "Intel ICH");
1285 for (name
= shortnames
; name
->id
; name
++) {
1286 if (pci
->device
== name
->id
) {
1287 strcpy(card
->shortname
, name
->s
);
1291 strcat(card
->shortname
," Modem");
1293 if ((err
= snd_intel8x0m_create(card
, pci
, pci_id
->driver_data
, &chip
)) < 0) {
1294 snd_card_free(card
);
1298 if ((err
= snd_intel8x0_mixer(chip
, ac97_clock
[dev
])) < 0) {
1299 snd_card_free(card
);
1302 if ((err
= snd_intel8x0_pcm(chip
)) < 0) {
1303 snd_card_free(card
);
1307 snd_intel8x0m_proc_init(chip
);
1309 sprintf(card
->longname
, "%s at 0x%lx, irq %i",
1310 card
->shortname
, chip
->addr
, chip
->irq
);
1312 if ((err
= snd_card_register(card
)) < 0) {
1313 snd_card_free(card
);
1316 pci_set_drvdata(pci
, card
);
1321 static void __devexit
snd_intel8x0m_remove(struct pci_dev
*pci
)
1323 snd_card_free(pci_get_drvdata(pci
));
1324 pci_set_drvdata(pci
, NULL
);
1327 static struct pci_driver driver
= {
1328 .name
= "Intel ICH Modem",
1329 .owner
= THIS_MODULE
,
1330 .id_table
= snd_intel8x0m_ids
,
1331 .probe
= snd_intel8x0m_probe
,
1332 .remove
= __devexit_p(snd_intel8x0m_remove
),
1333 SND_PCI_PM_CALLBACKS
1337 static int __init
alsa_card_intel8x0m_init(void)
1339 return pci_register_driver(&driver
);
1342 static void __exit
alsa_card_intel8x0m_exit(void)
1344 pci_unregister_driver(&driver
);
1347 module_init(alsa_card_intel8x0m_init
)
1348 module_exit(alsa_card_intel8x0m_exit
)