2 * Driver for CS4231 sound chips found on Sparcs.
3 * Copyright (C) 2002 David S. Miller <davem@redhat.com>
5 * Based entirely upon drivers/sbus/audio/cs4231.c which is:
6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
7 * and also sound/isa/cs423x/cs4231_lib.c which is:
8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/moduleparam.h>
20 #include <sound/driver.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/info.h>
24 #include <sound/control.h>
25 #include <sound/timer.h>
26 #include <sound/initval.h>
27 #include <sound/pcm_params.h>
40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
45 #include <linux/pci.h>
49 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
50 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
51 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
53 module_param_array(index
, int, NULL
, 0444);
54 MODULE_PARM_DESC(index
, "Index value for Sun CS4231 soundcard.");
55 module_param_array(id
, charp
, NULL
, 0444);
56 MODULE_PARM_DESC(id
, "ID string for Sun CS4231 soundcard.");
57 module_param_array(enable
, bool, NULL
, 0444);
58 MODULE_PARM_DESC(enable
, "Enable Sun CS4231 soundcard.");
59 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
60 MODULE_DESCRIPTION("Sun CS4231");
61 MODULE_LICENSE("GPL");
62 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
64 typedef struct snd_cs4231
{
68 struct ebus_dma_info eb2c
;
69 struct ebus_dma_info eb2p
;
73 #define CS4231_FLAG_EBUS 0x00000001
74 #define CS4231_FLAG_PLAYBACK 0x00000002
75 #define CS4231_FLAG_CAPTURE 0x00000004
79 snd_pcm_substream_t
*playback_substream
;
80 unsigned int p_periods_sent
;
81 snd_pcm_substream_t
*capture_substream
;
82 unsigned int c_periods_sent
;
86 #define CS4231_MODE_NONE 0x0000
87 #define CS4231_MODE_PLAY 0x0001
88 #define CS4231_MODE_RECORD 0x0002
89 #define CS4231_MODE_TIMER 0x0004
90 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
92 unsigned char image
[32]; /* registers image */
95 struct semaphore mce_mutex
;
96 struct semaphore open_mutex
;
100 struct sbus_dev
*sdev
;
103 struct pci_dev
*pdev
;
107 unsigned int regs_size
;
108 struct snd_cs4231
*next
;
111 static cs4231_t
*cs4231_list
;
113 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
119 #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
121 /* XXX offsets are different than PC ISA chips... */
122 #define c_d_c_CS4231REGSEL 0x0
123 #define c_d_c_CS4231REG 0x4
124 #define c_d_c_CS4231STATUS 0x8
125 #define c_d_c_CS4231PIO 0xc
127 /* codec registers */
129 #define CS4231_LEFT_INPUT 0x00 /* left input control */
130 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
131 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
132 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
133 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
134 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
135 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
136 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
137 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
138 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
139 #define CS4231_PIN_CTRL 0x0a /* pin control */
140 #define CS4231_TEST_INIT 0x0b /* test and initialization */
141 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
142 #define CS4231_LOOPBACK 0x0d /* loopback control */
143 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
144 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
145 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
146 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
147 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
148 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
149 #define CS4231_TIMER_LOW 0x14 /* timer low byte */
150 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
151 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
152 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
153 #define CS4236_EXT_REG 0x17 /* extended register access */
154 #define CS4231_IRQ_STATUS 0x18 /* irq status register */
155 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
156 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
157 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
158 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
159 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
160 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
161 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
162 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
163 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
164 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
166 /* definitions for codec register select port - CODECP( REGSEL ) */
168 #define CS4231_INIT 0x80 /* CODEC is initializing */
169 #define CS4231_MCE 0x40 /* mode change enable */
170 #define CS4231_TRD 0x20 /* transfer request disable */
172 /* definitions for codec status register - CODECP( STATUS ) */
174 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
176 /* definitions for codec irq status - CS4231_IRQ_STATUS */
178 #define CS4231_PLAYBACK_IRQ 0x10
179 #define CS4231_RECORD_IRQ 0x20
180 #define CS4231_TIMER_IRQ 0x40
181 #define CS4231_ALL_IRQS 0x70
182 #define CS4231_REC_UNDERRUN 0x08
183 #define CS4231_REC_OVERRUN 0x04
184 #define CS4231_PLY_OVERRUN 0x02
185 #define CS4231_PLY_UNDERRUN 0x01
187 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
189 #define CS4231_ENABLE_MIC_GAIN 0x20
191 #define CS4231_MIXS_LINE 0x00
192 #define CS4231_MIXS_AUX1 0x40
193 #define CS4231_MIXS_MIC 0x80
194 #define CS4231_MIXS_ALL 0xc0
196 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
198 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
199 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
200 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
201 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
202 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
203 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
204 #define CS4231_STEREO 0x10 /* stereo mode */
205 /* bits 3-1 define frequency divisor */
206 #define CS4231_XTAL1 0x00 /* 24.576 crystal */
207 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
209 /* definitions for interface control register - CS4231_IFACE_CTRL */
211 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
212 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
213 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
214 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
215 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
216 #define CS4231_RECORD_ENABLE 0x02 /* record enable */
217 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
219 /* definitions for pin control register - CS4231_PIN_CTRL */
221 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
222 #define CS4231_XCTL1 0x40 /* external control #1 */
223 #define CS4231_XCTL0 0x80 /* external control #0 */
225 /* definitions for test and init register - CS4231_TEST_INIT */
227 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
228 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
230 /* definitions for misc control register - CS4231_MISC_INFO */
232 #define CS4231_MODE2 0x40 /* MODE 2 */
233 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
234 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
236 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
238 #define CS4231_DACZ 0x01 /* zero DAC when underrun */
239 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
240 #define CS4231_OLB 0x80 /* output level bit */
242 /* SBUS DMA register defines. */
244 #define APCCSR 0x10UL /* APC DMA CSR */
245 #define APCCVA 0x20UL /* APC Capture DMA Address */
246 #define APCCC 0x24UL /* APC Capture Count */
247 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
248 #define APCCNC 0x2cUL /* APC Capture Next Count */
249 #define APCPVA 0x30UL /* APC Play DMA Address */
250 #define APCPC 0x34UL /* APC Play Count */
251 #define APCPNVA 0x38UL /* APC Play DMA Next Address */
252 #define APCPNC 0x3cUL /* APC Play Next Count */
256 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
257 #define APC_PLAY_INT 0x400000 /* Playback interrupt */
258 #define APC_CAPT_INT 0x200000 /* Capture interrupt */
259 #define APC_GENL_INT 0x100000 /* General interrupt */
260 #define APC_XINT_ENA 0x80000 /* General ext int. enable */
261 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
262 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
263 #define APC_XINT_GENL 0x10000 /* Error ext intr */
264 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
265 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
266 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
267 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
268 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
269 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
270 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
271 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
272 #define APC_PPAUSE 0x80 /* Pause the play DMA */
273 #define APC_CPAUSE 0x40 /* Pause the capture DMA */
274 #define APC_CDC_RESET 0x20 /* CODEC RESET */
275 #define APC_PDMA_READY 0x08 /* Play DMA Go */
276 #define APC_CDMA_READY 0x04 /* Capture DMA Go */
277 #define APC_CHIP_RESET 0x01 /* Reset the chip */
279 /* EBUS DMA register offsets */
281 #define EBDMA_CSR 0x00UL /* Control/Status */
282 #define EBDMA_ADDR 0x04UL /* DMA Address */
283 #define EBDMA_COUNT 0x08UL /* DMA Count */
289 static unsigned char freq_bits
[14] = {
290 /* 5510 */ 0x00 | CS4231_XTAL2
,
291 /* 6620 */ 0x0E | CS4231_XTAL2
,
292 /* 8000 */ 0x00 | CS4231_XTAL1
,
293 /* 9600 */ 0x0E | CS4231_XTAL1
,
294 /* 11025 */ 0x02 | CS4231_XTAL2
,
295 /* 16000 */ 0x02 | CS4231_XTAL1
,
296 /* 18900 */ 0x04 | CS4231_XTAL2
,
297 /* 22050 */ 0x06 | CS4231_XTAL2
,
298 /* 27042 */ 0x04 | CS4231_XTAL1
,
299 /* 32000 */ 0x06 | CS4231_XTAL1
,
300 /* 33075 */ 0x0C | CS4231_XTAL2
,
301 /* 37800 */ 0x08 | CS4231_XTAL2
,
302 /* 44100 */ 0x0A | CS4231_XTAL2
,
303 /* 48000 */ 0x0C | CS4231_XTAL1
306 static unsigned int rates
[14] = {
307 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
308 27042, 32000, 33075, 37800, 44100, 48000
311 static snd_pcm_hw_constraint_list_t hw_constraints_rates
= {
316 static int snd_cs4231_xrate(snd_pcm_runtime_t
*runtime
)
318 return snd_pcm_hw_constraint_list(runtime
, 0,
319 SNDRV_PCM_HW_PARAM_RATE
,
320 &hw_constraints_rates
);
323 static unsigned char snd_cs4231_original_image
[32] =
325 0x00, /* 00/00 - lic */
326 0x00, /* 01/01 - ric */
327 0x9f, /* 02/02 - la1ic */
328 0x9f, /* 03/03 - ra1ic */
329 0x9f, /* 04/04 - la2ic */
330 0x9f, /* 05/05 - ra2ic */
331 0xbf, /* 06/06 - loc */
332 0xbf, /* 07/07 - roc */
333 0x20, /* 08/08 - pdfr */
334 CS4231_AUTOCALIB
, /* 09/09 - ic */
335 0x00, /* 0a/10 - pc */
336 0x00, /* 0b/11 - ti */
337 CS4231_MODE2
, /* 0c/12 - mi */
338 0x00, /* 0d/13 - lbc */
339 0x00, /* 0e/14 - pbru */
340 0x00, /* 0f/15 - pbrl */
341 0x80, /* 10/16 - afei */
342 0x01, /* 11/17 - afeii */
343 0x9f, /* 12/18 - llic */
344 0x9f, /* 13/19 - rlic */
345 0x00, /* 14/20 - tlb */
346 0x00, /* 15/21 - thb */
347 0x00, /* 16/22 - la3mic/reserved */
348 0x00, /* 17/23 - ra3mic/reserved */
349 0x00, /* 18/24 - afs */
350 0x00, /* 19/25 - lamoc/version */
351 0x00, /* 1a/26 - mioc */
352 0x00, /* 1b/27 - ramoc/reserved */
353 0x20, /* 1c/28 - cdfr */
354 0x00, /* 1d/29 - res4 */
355 0x00, /* 1e/30 - cbru */
356 0x00, /* 1f/31 - cbrl */
359 static u8
__cs4231_readb(cs4231_t
*cp
, void __iomem
*reg_addr
)
362 if (cp
->flags
& CS4231_FLAG_EBUS
) {
363 return readb(reg_addr
);
367 return sbus_readb(reg_addr
);
374 static void __cs4231_writeb(cs4231_t
*cp
, u8 val
, void __iomem
*reg_addr
)
377 if (cp
->flags
& CS4231_FLAG_EBUS
) {
378 return writeb(val
, reg_addr
);
382 return sbus_writeb(val
, reg_addr
);
390 * Basic I/O functions
393 static void snd_cs4231_outm(cs4231_t
*chip
, unsigned char reg
,
394 unsigned char mask
, unsigned char value
)
400 timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
);
403 #ifdef CONFIG_SND_DEBUG
404 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
405 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg
, value
);
407 if (chip
->calibrate_mute
) {
408 chip
->image
[reg
] &= mask
;
409 chip
->image
[reg
] |= value
;
411 __cs4231_writeb(chip
, chip
->mce_bit
| reg
, CS4231P(chip
, REGSEL
));
413 tmp
= (chip
->image
[reg
] & mask
) | value
;
414 __cs4231_writeb(chip
, tmp
, CS4231P(chip
, REG
));
415 chip
->image
[reg
] = tmp
;
420 static void snd_cs4231_dout(cs4231_t
*chip
, unsigned char reg
, unsigned char value
)
425 timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
);
428 #ifdef CONFIG_SND_DEBUG
429 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
430 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg
, value
);
432 __cs4231_writeb(chip
, chip
->mce_bit
| reg
, CS4231P(chip
, REGSEL
));
433 __cs4231_writeb(chip
, value
, CS4231P(chip
, REG
));
437 static void snd_cs4231_out(cs4231_t
*chip
, unsigned char reg
, unsigned char value
)
442 timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
);
445 #ifdef CONFIG_SND_DEBUG
446 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
447 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg
, value
);
449 __cs4231_writeb(chip
, chip
->mce_bit
| reg
, CS4231P(chip
, REGSEL
));
450 __cs4231_writeb(chip
, value
, CS4231P(chip
, REG
));
451 chip
->image
[reg
] = value
;
455 static unsigned char snd_cs4231_in(cs4231_t
*chip
, unsigned char reg
)
461 timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
);
464 #ifdef CONFIG_SND_DEBUG
465 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
466 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg
);
468 __cs4231_writeb(chip
, chip
->mce_bit
| reg
, CS4231P(chip
, REGSEL
));
470 ret
= __cs4231_readb(chip
, CS4231P(chip
, REG
));
475 * CS4231 detection / MCE routines
478 static void snd_cs4231_busy_wait(cs4231_t
*chip
)
482 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
483 for (timeout
= 5; timeout
> 0; timeout
--)
484 __cs4231_readb(chip
, CS4231P(chip
, REGSEL
));
486 /* end of cleanup sequence */
488 timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
);
493 static void snd_cs4231_mce_up(cs4231_t
*chip
)
498 spin_lock_irqsave(&chip
->lock
, flags
);
499 for (timeout
= 250; timeout
> 0 && (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
); timeout
--)
501 #ifdef CONFIG_SND_DEBUG
502 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
503 snd_printdd("mce_up - auto calibration time out (0)\n");
505 chip
->mce_bit
|= CS4231_MCE
;
506 timeout
= __cs4231_readb(chip
, CS4231P(chip
, REGSEL
));
508 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip
->port
);
509 if (!(timeout
& CS4231_MCE
))
510 __cs4231_writeb(chip
, chip
->mce_bit
| (timeout
& 0x1f), CS4231P(chip
, REGSEL
));
511 spin_unlock_irqrestore(&chip
->lock
, flags
);
514 static void snd_cs4231_mce_down(cs4231_t
*chip
)
519 spin_lock_irqsave(&chip
->lock
, flags
);
520 snd_cs4231_busy_wait(chip
);
521 #ifdef CONFIG_SND_DEBUG
522 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
523 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip
, REGSEL
));
525 chip
->mce_bit
&= ~CS4231_MCE
;
526 timeout
= __cs4231_readb(chip
, CS4231P(chip
, REGSEL
));
527 __cs4231_writeb(chip
, chip
->mce_bit
| (timeout
& 0x1f), CS4231P(chip
, REGSEL
));
529 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip
->port
);
530 if ((timeout
& CS4231_MCE
) == 0) {
531 spin_unlock_irqrestore(&chip
->lock
, flags
);
534 snd_cs4231_busy_wait(chip
);
536 /* calibration process */
538 for (timeout
= 500; timeout
> 0 && (snd_cs4231_in(chip
, CS4231_TEST_INIT
) & CS4231_CALIB_IN_PROGRESS
) == 0; timeout
--)
540 if ((snd_cs4231_in(chip
, CS4231_TEST_INIT
) & CS4231_CALIB_IN_PROGRESS
) == 0) {
541 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
542 spin_unlock_irqrestore(&chip
->lock
, flags
);
546 /* in 10ms increments, check condition, up to 250ms */
548 while (snd_cs4231_in(chip
, CS4231_TEST_INIT
) & CS4231_CALIB_IN_PROGRESS
) {
549 spin_unlock_irqrestore(&chip
->lock
, flags
);
551 snd_printk("mce_down - auto calibration time out (2)\n");
555 spin_lock_irqsave(&chip
->lock
, flags
);
558 /* in 10ms increments, check condition, up to 100ms */
560 while (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
) {
561 spin_unlock_irqrestore(&chip
->lock
, flags
);
563 snd_printk("mce_down - auto calibration time out (3)\n");
567 spin_lock_irqsave(&chip
->lock
, flags
);
569 spin_unlock_irqrestore(&chip
->lock
, flags
);
573 static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info
*p
, snd_pcm_substream_t
*substream
, unsigned int *periods_sent
)
575 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
578 unsigned int period_size
= snd_pcm_lib_period_bytes(substream
);
579 unsigned int offset
= period_size
* (*periods_sent
);
581 if (period_size
>= (1 << 24))
584 if (ebus_dma_request(p
, runtime
->dma_addr
+ offset
, period_size
))
586 (*periods_sent
) = ((*periods_sent
) + 1) % runtime
->periods
;
592 static void snd_cs4231_sbus_advance_dma(snd_pcm_substream_t
*substream
, unsigned int *periods_sent
)
594 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
595 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
597 unsigned int period_size
= snd_pcm_lib_period_bytes(substream
);
598 unsigned int offset
= period_size
* (*periods_sent
% runtime
->periods
);
600 if (runtime
->period_size
> 0xffff + 1)
603 switch (substream
->stream
) {
604 case SNDRV_PCM_STREAM_PLAYBACK
:
605 sbus_writel(runtime
->dma_addr
+ offset
, chip
->port
+ APCPNVA
);
606 sbus_writel(period_size
, chip
->port
+ APCPNC
);
608 case SNDRV_PCM_STREAM_CAPTURE
:
609 sbus_writel(runtime
->dma_addr
+ offset
, chip
->port
+ APCCNVA
);
610 sbus_writel(period_size
, chip
->port
+ APCCNC
);
614 (*periods_sent
) = (*periods_sent
+ 1) % runtime
->periods
;
618 static void cs4231_dma_trigger(snd_pcm_substream_t
*substream
, unsigned int what
, int on
)
620 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
623 if (chip
->flags
& CS4231_FLAG_EBUS
) {
624 if (what
& CS4231_PLAYBACK_ENABLE
) {
626 ebus_dma_prepare(&chip
->eb2p
, 0);
627 ebus_dma_enable(&chip
->eb2p
, 1);
628 snd_cs4231_ebus_advance_dma(&chip
->eb2p
,
629 chip
->playback_substream
,
630 &chip
->p_periods_sent
);
632 ebus_dma_enable(&chip
->eb2p
, 0);
635 if (what
& CS4231_RECORD_ENABLE
) {
637 ebus_dma_prepare(&chip
->eb2c
, 1);
638 ebus_dma_enable(&chip
->eb2c
, 1);
639 snd_cs4231_ebus_advance_dma(&chip
->eb2c
,
640 chip
->capture_substream
,
641 &chip
->c_periods_sent
);
643 ebus_dma_enable(&chip
->eb2c
, 0);
649 u32 csr
= sbus_readl(chip
->port
+ APCCSR
);
650 /* I don't know why, but on sbus the period counter must
651 * only start counting after the first period is sent.
652 * Therefore this dummy thing.
654 unsigned int dummy
= 0;
657 case CS4231_PLAYBACK_ENABLE
:
659 csr
&= ~APC_XINT_PLAY
;
660 sbus_writel(csr
, chip
->port
+ APCCSR
);
663 sbus_writel(csr
, chip
->port
+ APCCSR
);
665 snd_cs4231_sbus_advance_dma(substream
, &dummy
);
667 csr
|= APC_GENL_INT
| APC_PLAY_INT
| APC_XINT_ENA
|
668 APC_XINT_PLAY
| APC_XINT_EMPT
| APC_XINT_GENL
|
669 APC_XINT_PENA
| APC_PDMA_READY
;
670 sbus_writel(csr
, chip
->port
+ APCCSR
);
673 sbus_writel(csr
, chip
->port
+ APCCSR
);
675 csr
&= ~APC_PDMA_READY
;
676 sbus_writel(csr
, chip
->port
+ APCCSR
);
679 case CS4231_RECORD_ENABLE
:
681 csr
&= ~APC_XINT_CAPT
;
682 sbus_writel(csr
, chip
->port
+ APCCSR
);
685 sbus_writel(csr
, chip
->port
+ APCCSR
);
687 snd_cs4231_sbus_advance_dma(substream
, &dummy
);
689 csr
|= APC_GENL_INT
| APC_CAPT_INT
| APC_XINT_ENA
|
690 APC_XINT_CAPT
| APC_XINT_CEMP
| APC_XINT_GENL
|
693 sbus_writel(csr
, chip
->port
+ APCCSR
);
696 sbus_writel(csr
, chip
->port
+ APCCSR
);
698 csr
&= ~APC_CDMA_READY
;
699 sbus_writel(csr
, chip
->port
+ APCCSR
);
709 static int snd_cs4231_trigger(snd_pcm_substream_t
*substream
, int cmd
)
711 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
715 case SNDRV_PCM_TRIGGER_START
:
716 case SNDRV_PCM_TRIGGER_STOP
:
718 unsigned int what
= 0;
719 snd_pcm_substream_t
*s
;
720 struct list_head
*pos
;
723 snd_pcm_group_for_each(pos
, substream
) {
724 s
= snd_pcm_group_substream_entry(pos
);
725 if (s
== chip
->playback_substream
) {
726 what
|= CS4231_PLAYBACK_ENABLE
;
727 snd_pcm_trigger_done(s
, substream
);
728 } else if (s
== chip
->capture_substream
) {
729 what
|= CS4231_RECORD_ENABLE
;
730 snd_pcm_trigger_done(s
, substream
);
734 spin_lock_irqsave(&chip
->lock
, flags
);
735 if (cmd
== SNDRV_PCM_TRIGGER_START
) {
736 cs4231_dma_trigger(substream
, what
, 1);
737 chip
->image
[CS4231_IFACE_CTRL
] |= what
;
739 cs4231_dma_trigger(substream
, what
, 0);
740 chip
->image
[CS4231_IFACE_CTRL
] &= ~what
;
742 snd_cs4231_out(chip
, CS4231_IFACE_CTRL
,
743 chip
->image
[CS4231_IFACE_CTRL
]);
744 spin_unlock_irqrestore(&chip
->lock
, flags
);
759 static unsigned char snd_cs4231_get_rate(unsigned int rate
)
763 for (i
= 0; i
< 14; i
++)
764 if (rate
== rates
[i
])
767 return freq_bits
[13];
770 static unsigned char snd_cs4231_get_format(cs4231_t
*chip
, int format
, int channels
)
772 unsigned char rformat
;
774 rformat
= CS4231_LINEAR_8
;
776 case SNDRV_PCM_FORMAT_MU_LAW
: rformat
= CS4231_ULAW_8
; break;
777 case SNDRV_PCM_FORMAT_A_LAW
: rformat
= CS4231_ALAW_8
; break;
778 case SNDRV_PCM_FORMAT_S16_LE
: rformat
= CS4231_LINEAR_16
; break;
779 case SNDRV_PCM_FORMAT_S16_BE
: rformat
= CS4231_LINEAR_16_BIG
; break;
780 case SNDRV_PCM_FORMAT_IMA_ADPCM
: rformat
= CS4231_ADPCM_16
; break;
783 rformat
|= CS4231_STEREO
;
787 static void snd_cs4231_calibrate_mute(cs4231_t
*chip
, int mute
)
792 spin_lock_irqsave(&chip
->lock
, flags
);
793 if (chip
->calibrate_mute
== mute
) {
794 spin_unlock_irqrestore(&chip
->lock
, flags
);
798 snd_cs4231_dout(chip
, CS4231_LEFT_INPUT
,
799 chip
->image
[CS4231_LEFT_INPUT
]);
800 snd_cs4231_dout(chip
, CS4231_RIGHT_INPUT
,
801 chip
->image
[CS4231_RIGHT_INPUT
]);
802 snd_cs4231_dout(chip
, CS4231_LOOPBACK
,
803 chip
->image
[CS4231_LOOPBACK
]);
805 snd_cs4231_dout(chip
, CS4231_AUX1_LEFT_INPUT
,
806 mute
? 0x80 : chip
->image
[CS4231_AUX1_LEFT_INPUT
]);
807 snd_cs4231_dout(chip
, CS4231_AUX1_RIGHT_INPUT
,
808 mute
? 0x80 : chip
->image
[CS4231_AUX1_RIGHT_INPUT
]);
809 snd_cs4231_dout(chip
, CS4231_AUX2_LEFT_INPUT
,
810 mute
? 0x80 : chip
->image
[CS4231_AUX2_LEFT_INPUT
]);
811 snd_cs4231_dout(chip
, CS4231_AUX2_RIGHT_INPUT
,
812 mute
? 0x80 : chip
->image
[CS4231_AUX2_RIGHT_INPUT
]);
813 snd_cs4231_dout(chip
, CS4231_LEFT_OUTPUT
,
814 mute
? 0x80 : chip
->image
[CS4231_LEFT_OUTPUT
]);
815 snd_cs4231_dout(chip
, CS4231_RIGHT_OUTPUT
,
816 mute
? 0x80 : chip
->image
[CS4231_RIGHT_OUTPUT
]);
817 snd_cs4231_dout(chip
, CS4231_LEFT_LINE_IN
,
818 mute
? 0x80 : chip
->image
[CS4231_LEFT_LINE_IN
]);
819 snd_cs4231_dout(chip
, CS4231_RIGHT_LINE_IN
,
820 mute
? 0x80 : chip
->image
[CS4231_RIGHT_LINE_IN
]);
821 snd_cs4231_dout(chip
, CS4231_MONO_CTRL
,
822 mute
? 0xc0 : chip
->image
[CS4231_MONO_CTRL
]);
823 chip
->calibrate_mute
= mute
;
824 spin_unlock_irqrestore(&chip
->lock
, flags
);
827 static void snd_cs4231_playback_format(cs4231_t
*chip
, snd_pcm_hw_params_t
*params
,
832 down(&chip
->mce_mutex
);
833 snd_cs4231_calibrate_mute(chip
, 1);
835 snd_cs4231_mce_up(chip
);
837 spin_lock_irqsave(&chip
->lock
, flags
);
838 snd_cs4231_out(chip
, CS4231_PLAYBK_FORMAT
,
839 (chip
->image
[CS4231_IFACE_CTRL
] & CS4231_RECORD_ENABLE
) ?
840 (pdfr
& 0xf0) | (chip
->image
[CS4231_REC_FORMAT
] & 0x0f) :
842 spin_unlock_irqrestore(&chip
->lock
, flags
);
844 snd_cs4231_mce_down(chip
);
846 snd_cs4231_calibrate_mute(chip
, 0);
847 up(&chip
->mce_mutex
);
850 static void snd_cs4231_capture_format(cs4231_t
*chip
, snd_pcm_hw_params_t
*params
,
855 down(&chip
->mce_mutex
);
856 snd_cs4231_calibrate_mute(chip
, 1);
858 snd_cs4231_mce_up(chip
);
860 spin_lock_irqsave(&chip
->lock
, flags
);
861 if (!(chip
->image
[CS4231_IFACE_CTRL
] & CS4231_PLAYBACK_ENABLE
)) {
862 snd_cs4231_out(chip
, CS4231_PLAYBK_FORMAT
,
863 ((chip
->image
[CS4231_PLAYBK_FORMAT
]) & 0xf0) |
865 spin_unlock_irqrestore(&chip
->lock
, flags
);
866 snd_cs4231_mce_down(chip
);
867 snd_cs4231_mce_up(chip
);
868 spin_lock_irqsave(&chip
->lock
, flags
);
870 snd_cs4231_out(chip
, CS4231_REC_FORMAT
, cdfr
);
871 spin_unlock_irqrestore(&chip
->lock
, flags
);
873 snd_cs4231_mce_down(chip
);
875 snd_cs4231_calibrate_mute(chip
, 0);
876 up(&chip
->mce_mutex
);
883 static unsigned long snd_cs4231_timer_resolution(snd_timer_t
*timer
)
885 cs4231_t
*chip
= snd_timer_chip(timer
);
887 return chip
->image
[CS4231_PLAYBK_FORMAT
] & 1 ? 9969 : 9920;
890 static int snd_cs4231_timer_start(snd_timer_t
*timer
)
894 cs4231_t
*chip
= snd_timer_chip(timer
);
896 spin_lock_irqsave(&chip
->lock
, flags
);
897 ticks
= timer
->sticks
;
898 if ((chip
->image
[CS4231_ALT_FEATURE_1
] & CS4231_TIMER_ENABLE
) == 0 ||
899 (unsigned char)(ticks
>> 8) != chip
->image
[CS4231_TIMER_HIGH
] ||
900 (unsigned char)ticks
!= chip
->image
[CS4231_TIMER_LOW
]) {
901 snd_cs4231_out(chip
, CS4231_TIMER_HIGH
,
902 chip
->image
[CS4231_TIMER_HIGH
] =
903 (unsigned char) (ticks
>> 8));
904 snd_cs4231_out(chip
, CS4231_TIMER_LOW
,
905 chip
->image
[CS4231_TIMER_LOW
] =
906 (unsigned char) ticks
);
907 snd_cs4231_out(chip
, CS4231_ALT_FEATURE_1
,
908 chip
->image
[CS4231_ALT_FEATURE_1
] | CS4231_TIMER_ENABLE
);
910 spin_unlock_irqrestore(&chip
->lock
, flags
);
915 static int snd_cs4231_timer_stop(snd_timer_t
*timer
)
918 cs4231_t
*chip
= snd_timer_chip(timer
);
920 spin_lock_irqsave(&chip
->lock
, flags
);
921 snd_cs4231_out(chip
, CS4231_ALT_FEATURE_1
,
922 chip
->image
[CS4231_ALT_FEATURE_1
] &= ~CS4231_TIMER_ENABLE
);
923 spin_unlock_irqrestore(&chip
->lock
, flags
);
928 static void snd_cs4231_init(cs4231_t
*chip
)
932 snd_cs4231_mce_down(chip
);
934 #ifdef SNDRV_DEBUG_MCE
935 snd_printdd("init: (1)\n");
937 snd_cs4231_mce_up(chip
);
938 spin_lock_irqsave(&chip
->lock
, flags
);
939 chip
->image
[CS4231_IFACE_CTRL
] &= ~(CS4231_PLAYBACK_ENABLE
| CS4231_PLAYBACK_PIO
|
940 CS4231_RECORD_ENABLE
| CS4231_RECORD_PIO
|
942 chip
->image
[CS4231_IFACE_CTRL
] |= CS4231_AUTOCALIB
;
943 snd_cs4231_out(chip
, CS4231_IFACE_CTRL
, chip
->image
[CS4231_IFACE_CTRL
]);
944 spin_unlock_irqrestore(&chip
->lock
, flags
);
945 snd_cs4231_mce_down(chip
);
947 #ifdef SNDRV_DEBUG_MCE
948 snd_printdd("init: (2)\n");
951 snd_cs4231_mce_up(chip
);
952 spin_lock_irqsave(&chip
->lock
, flags
);
953 snd_cs4231_out(chip
, CS4231_ALT_FEATURE_1
, chip
->image
[CS4231_ALT_FEATURE_1
]);
954 spin_unlock_irqrestore(&chip
->lock
, flags
);
955 snd_cs4231_mce_down(chip
);
957 #ifdef SNDRV_DEBUG_MCE
958 snd_printdd("init: (3) - afei = 0x%x\n", chip
->image
[CS4231_ALT_FEATURE_1
]);
961 spin_lock_irqsave(&chip
->lock
, flags
);
962 snd_cs4231_out(chip
, CS4231_ALT_FEATURE_2
, chip
->image
[CS4231_ALT_FEATURE_2
]);
963 spin_unlock_irqrestore(&chip
->lock
, flags
);
965 snd_cs4231_mce_up(chip
);
966 spin_lock_irqsave(&chip
->lock
, flags
);
967 snd_cs4231_out(chip
, CS4231_PLAYBK_FORMAT
, chip
->image
[CS4231_PLAYBK_FORMAT
]);
968 spin_unlock_irqrestore(&chip
->lock
, flags
);
969 snd_cs4231_mce_down(chip
);
971 #ifdef SNDRV_DEBUG_MCE
972 snd_printdd("init: (4)\n");
975 snd_cs4231_mce_up(chip
);
976 spin_lock_irqsave(&chip
->lock
, flags
);
977 snd_cs4231_out(chip
, CS4231_REC_FORMAT
, chip
->image
[CS4231_REC_FORMAT
]);
978 spin_unlock_irqrestore(&chip
->lock
, flags
);
979 snd_cs4231_mce_down(chip
);
981 #ifdef SNDRV_DEBUG_MCE
982 snd_printdd("init: (5)\n");
986 static int snd_cs4231_open(cs4231_t
*chip
, unsigned int mode
)
990 down(&chip
->open_mutex
);
991 if ((chip
->mode
& mode
)) {
992 up(&chip
->open_mutex
);
995 if (chip
->mode
& CS4231_MODE_OPEN
) {
997 up(&chip
->open_mutex
);
1000 /* ok. now enable and ack CODEC IRQ */
1001 spin_lock_irqsave(&chip
->lock
, flags
);
1002 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, CS4231_PLAYBACK_IRQ
|
1005 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, 0);
1006 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1007 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1009 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, CS4231_PLAYBACK_IRQ
|
1012 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, 0);
1014 spin_unlock_irqrestore(&chip
->lock
, flags
);
1017 up(&chip
->open_mutex
);
1021 static void snd_cs4231_close(cs4231_t
*chip
, unsigned int mode
)
1023 unsigned long flags
;
1025 down(&chip
->open_mutex
);
1026 chip
->mode
&= ~mode
;
1027 if (chip
->mode
& CS4231_MODE_OPEN
) {
1028 up(&chip
->open_mutex
);
1031 snd_cs4231_calibrate_mute(chip
, 1);
1034 spin_lock_irqsave(&chip
->lock
, flags
);
1035 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, 0);
1036 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1037 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1039 /* now disable record & playback */
1041 if (chip
->image
[CS4231_IFACE_CTRL
] &
1042 (CS4231_PLAYBACK_ENABLE
| CS4231_PLAYBACK_PIO
|
1043 CS4231_RECORD_ENABLE
| CS4231_RECORD_PIO
)) {
1044 spin_unlock_irqrestore(&chip
->lock
, flags
);
1045 snd_cs4231_mce_up(chip
);
1046 spin_lock_irqsave(&chip
->lock
, flags
);
1047 chip
->image
[CS4231_IFACE_CTRL
] &=
1048 ~(CS4231_PLAYBACK_ENABLE
| CS4231_PLAYBACK_PIO
|
1049 CS4231_RECORD_ENABLE
| CS4231_RECORD_PIO
);
1050 snd_cs4231_out(chip
, CS4231_IFACE_CTRL
, chip
->image
[CS4231_IFACE_CTRL
]);
1051 spin_unlock_irqrestore(&chip
->lock
, flags
);
1052 snd_cs4231_mce_down(chip
);
1053 spin_lock_irqsave(&chip
->lock
, flags
);
1056 /* clear IRQ again */
1057 snd_cs4231_out(chip
, CS4231_IRQ_STATUS
, 0);
1058 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1059 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
)); /* clear IRQ */
1060 spin_unlock_irqrestore(&chip
->lock
, flags
);
1062 snd_cs4231_calibrate_mute(chip
, 0);
1065 up(&chip
->open_mutex
);
1072 static int snd_cs4231_timer_open(snd_timer_t
*timer
)
1074 cs4231_t
*chip
= snd_timer_chip(timer
);
1075 snd_cs4231_open(chip
, CS4231_MODE_TIMER
);
1079 static int snd_cs4231_timer_close(snd_timer_t
* timer
)
1081 cs4231_t
*chip
= snd_timer_chip(timer
);
1082 snd_cs4231_close(chip
, CS4231_MODE_TIMER
);
1086 static struct _snd_timer_hardware snd_cs4231_timer_table
=
1088 .flags
= SNDRV_TIMER_HW_AUTO
,
1091 .open
= snd_cs4231_timer_open
,
1092 .close
= snd_cs4231_timer_close
,
1093 .c_resolution
= snd_cs4231_timer_resolution
,
1094 .start
= snd_cs4231_timer_start
,
1095 .stop
= snd_cs4231_timer_stop
,
1099 * ok.. exported functions..
1102 static int snd_cs4231_playback_hw_params(snd_pcm_substream_t
*substream
,
1103 snd_pcm_hw_params_t
*hw_params
)
1105 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1106 unsigned char new_pdfr
;
1109 if ((err
= snd_pcm_lib_malloc_pages(substream
,
1110 params_buffer_bytes(hw_params
))) < 0)
1112 new_pdfr
= snd_cs4231_get_format(chip
, params_format(hw_params
),
1113 params_channels(hw_params
)) |
1114 snd_cs4231_get_rate(params_rate(hw_params
));
1115 snd_cs4231_playback_format(chip
, hw_params
, new_pdfr
);
1120 static int snd_cs4231_playback_hw_free(snd_pcm_substream_t
*substream
)
1122 return snd_pcm_lib_free_pages(substream
);
1125 static int snd_cs4231_playback_prepare(snd_pcm_substream_t
*substream
)
1127 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1128 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1129 unsigned long flags
;
1131 spin_lock_irqsave(&chip
->lock
, flags
);
1133 chip
->image
[CS4231_IFACE_CTRL
] &= ~(CS4231_PLAYBACK_ENABLE
|
1134 CS4231_PLAYBACK_PIO
);
1136 if (runtime
->period_size
> 0xffff + 1)
1139 snd_cs4231_out(chip
, CS4231_PLY_LWR_CNT
, (runtime
->period_size
- 1) & 0x00ff);
1140 snd_cs4231_out(chip
, CS4231_PLY_UPR_CNT
, (runtime
->period_size
- 1) >> 8 & 0x00ff);
1141 chip
->p_periods_sent
= 0;
1143 spin_unlock_irqrestore(&chip
->lock
, flags
);
1148 static int snd_cs4231_capture_hw_params(snd_pcm_substream_t
*substream
,
1149 snd_pcm_hw_params_t
*hw_params
)
1151 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1152 unsigned char new_cdfr
;
1155 if ((err
= snd_pcm_lib_malloc_pages(substream
,
1156 params_buffer_bytes(hw_params
))) < 0)
1158 new_cdfr
= snd_cs4231_get_format(chip
, params_format(hw_params
),
1159 params_channels(hw_params
)) |
1160 snd_cs4231_get_rate(params_rate(hw_params
));
1161 snd_cs4231_capture_format(chip
, hw_params
, new_cdfr
);
1166 static int snd_cs4231_capture_hw_free(snd_pcm_substream_t
*substream
)
1168 return snd_pcm_lib_free_pages(substream
);
1171 static int snd_cs4231_capture_prepare(snd_pcm_substream_t
*substream
)
1173 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1174 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1175 unsigned long flags
;
1177 spin_lock_irqsave(&chip
->lock
, flags
);
1178 chip
->image
[CS4231_IFACE_CTRL
] &= ~(CS4231_RECORD_ENABLE
|
1181 snd_cs4231_out(chip
, CS4231_REC_LWR_CNT
, (runtime
->period_size
- 1) & 0x00ff);
1182 snd_cs4231_out(chip
, CS4231_REC_LWR_CNT
, (runtime
->period_size
- 1) >> 8 & 0x00ff);
1184 spin_unlock_irqrestore(&chip
->lock
, flags
);
1189 static void snd_cs4231_overrange(cs4231_t
*chip
)
1191 unsigned long flags
;
1194 spin_lock_irqsave(&chip
->lock
, flags
);
1195 res
= snd_cs4231_in(chip
, CS4231_TEST_INIT
);
1196 spin_unlock_irqrestore(&chip
->lock
, flags
);
1198 if (res
& (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1199 chip
->capture_substream
->runtime
->overrange
++;
1202 static irqreturn_t
snd_cs4231_generic_interrupt(cs4231_t
*chip
)
1204 unsigned long flags
;
1205 unsigned char status
;
1207 /*This is IRQ is not raised by the cs4231*/
1208 if (!(__cs4231_readb(chip
, CS4231P(chip
, STATUS
)) & CS4231_GLOBALIRQ
))
1211 status
= snd_cs4231_in(chip
, CS4231_IRQ_STATUS
);
1213 if (status
& CS4231_TIMER_IRQ
) {
1215 snd_timer_interrupt(chip
->timer
, chip
->timer
->sticks
);
1218 if (status
& CS4231_RECORD_IRQ
)
1219 snd_cs4231_overrange(chip
);
1221 /* ACK the CS4231 interrupt. */
1222 spin_lock_irqsave(&chip
->lock
, flags
);
1223 snd_cs4231_outm(chip
, CS4231_IRQ_STATUS
, ~CS4231_ALL_IRQS
| ~status
, 0);
1224 spin_unlock_irqrestore(&chip
->lock
, flags
);
1230 static irqreturn_t
snd_cs4231_sbus_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
1232 cs4231_t
*chip
= dev_id
;
1234 /* ACK the APC interrupt. */
1235 u32 csr
= sbus_readl(chip
->port
+ APCCSR
);
1237 sbus_writel(csr
, chip
->port
+ APCCSR
);
1239 if ((chip
->image
[CS4231_IFACE_CTRL
] & CS4231_PLAYBACK_ENABLE
) &&
1240 (csr
& APC_PLAY_INT
) &&
1241 (csr
& APC_XINT_PNVA
) &&
1242 !(csr
& APC_XINT_EMPT
)) {
1243 snd_cs4231_sbus_advance_dma(chip
->playback_substream
,
1244 &chip
->p_periods_sent
);
1245 snd_pcm_period_elapsed(chip
->playback_substream
);
1248 if ((chip
->image
[CS4231_IFACE_CTRL
] & CS4231_RECORD_ENABLE
) &&
1249 (csr
& APC_CAPT_INT
) &&
1250 (csr
& APC_XINT_CNVA
)) {
1251 snd_cs4231_sbus_advance_dma(chip
->capture_substream
,
1252 &chip
->c_periods_sent
);
1253 snd_pcm_period_elapsed(chip
->capture_substream
);
1256 return snd_cs4231_generic_interrupt(chip
);
1261 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info
*p
, int event
, void *cookie
)
1263 cs4231_t
*chip
= cookie
;
1265 if (chip
->image
[CS4231_IFACE_CTRL
] & CS4231_PLAYBACK_ENABLE
) {
1266 snd_pcm_period_elapsed(chip
->playback_substream
);
1267 snd_cs4231_ebus_advance_dma(p
, chip
->playback_substream
,
1268 &chip
->p_periods_sent
);
1272 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info
*p
, int event
, void *cookie
)
1274 cs4231_t
*chip
= cookie
;
1276 if (chip
->image
[CS4231_IFACE_CTRL
] & CS4231_RECORD_ENABLE
) {
1277 snd_pcm_period_elapsed(chip
->capture_substream
);
1278 snd_cs4231_ebus_advance_dma(p
, chip
->capture_substream
,
1279 &chip
->c_periods_sent
);
1284 static snd_pcm_uframes_t
snd_cs4231_playback_pointer(snd_pcm_substream_t
*substream
)
1286 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1287 size_t ptr
, residue
, period_bytes
;
1289 if (!(chip
->image
[CS4231_IFACE_CTRL
] & CS4231_PLAYBACK_ENABLE
))
1291 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1292 ptr
= period_bytes
* chip
->p_periods_sent
;
1294 if (chip
->flags
& CS4231_FLAG_EBUS
) {
1295 residue
= ebus_dma_residue(&chip
->eb2p
);
1299 residue
= sbus_readl(chip
->port
+ APCPC
);
1304 ptr
+= period_bytes
- residue
;
1306 return bytes_to_frames(substream
->runtime
, ptr
);
1309 static snd_pcm_uframes_t
snd_cs4231_capture_pointer(snd_pcm_substream_t
* substream
)
1311 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1312 size_t ptr
, residue
, period_bytes
;
1314 if (!(chip
->image
[CS4231_IFACE_CTRL
] & CS4231_RECORD_ENABLE
))
1316 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1317 ptr
= period_bytes
* chip
->c_periods_sent
;
1319 if (chip
->flags
& CS4231_FLAG_EBUS
) {
1320 residue
= ebus_dma_residue(&chip
->eb2c
);
1324 residue
= sbus_readl(chip
->port
+ APCCC
);
1329 ptr
+= period_bytes
- residue
;
1330 return bytes_to_frames(substream
->runtime
, ptr
);
1337 static int snd_cs4231_probe(cs4231_t
*chip
)
1339 unsigned long flags
;
1344 for (i
= 0; i
< 50; i
++) {
1346 if (__cs4231_readb(chip
, CS4231P(chip
, REGSEL
)) & CS4231_INIT
)
1349 spin_lock_irqsave(&chip
->lock
, flags
);
1350 snd_cs4231_out(chip
, CS4231_MISC_INFO
, CS4231_MODE2
);
1351 id
= snd_cs4231_in(chip
, CS4231_MISC_INFO
) & 0x0f;
1352 vers
= snd_cs4231_in(chip
, CS4231_VERSION
);
1353 spin_unlock_irqrestore(&chip
->lock
, flags
);
1355 break; /* this is valid value */
1358 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip
->port
, id
);
1360 return -ENODEV
; /* no valid device found */
1362 spin_lock_irqsave(&chip
->lock
, flags
);
1365 /* Reset DMA engine. */
1367 if (chip
->flags
& CS4231_FLAG_EBUS
) {
1368 /* Done by ebus_dma_register */
1372 sbus_writel(APC_CHIP_RESET
, chip
->port
+ APCCSR
);
1373 sbus_writel(0x00, chip
->port
+ APCCSR
);
1374 sbus_writel(sbus_readl(chip
->port
+ APCCSR
) | APC_CDC_RESET
,
1375 chip
->port
+ APCCSR
);
1379 sbus_writel(sbus_readl(chip
->port
+ APCCSR
) & ~APC_CDC_RESET
,
1380 chip
->port
+ APCCSR
);
1381 sbus_writel(sbus_readl(chip
->port
+ APCCSR
) | (APC_XINT_ENA
|
1384 chip
->port
+ APCCSR
);
1390 __cs4231_readb(chip
, CS4231P(chip
, STATUS
)); /* clear any pendings IRQ */
1391 __cs4231_writeb(chip
, 0, CS4231P(chip
, STATUS
));
1394 spin_unlock_irqrestore(&chip
->lock
, flags
);
1396 chip
->image
[CS4231_MISC_INFO
] = CS4231_MODE2
;
1397 chip
->image
[CS4231_IFACE_CTRL
] =
1398 chip
->image
[CS4231_IFACE_CTRL
] & ~CS4231_SINGLE_DMA
;
1399 chip
->image
[CS4231_ALT_FEATURE_1
] = 0x80;
1400 chip
->image
[CS4231_ALT_FEATURE_2
] = 0x01;
1402 chip
->image
[CS4231_ALT_FEATURE_2
] |= 0x02;
1404 ptr
= (unsigned char *) &chip
->image
;
1406 snd_cs4231_mce_down(chip
);
1408 spin_lock_irqsave(&chip
->lock
, flags
);
1410 for (i
= 0; i
< 32; i
++) /* ok.. fill all CS4231 registers */
1411 snd_cs4231_out(chip
, i
, *ptr
++);
1413 spin_unlock_irqrestore(&chip
->lock
, flags
);
1415 snd_cs4231_mce_up(chip
);
1417 snd_cs4231_mce_down(chip
);
1421 return 0; /* all things are ok.. */
1424 static snd_pcm_hardware_t snd_cs4231_playback
=
1426 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1427 SNDRV_PCM_INFO_MMAP_VALID
| SNDRV_PCM_INFO_SYNC_START
),
1428 .formats
= (SNDRV_PCM_FMTBIT_MU_LAW
| SNDRV_PCM_FMTBIT_A_LAW
|
1429 SNDRV_PCM_FMTBIT_IMA_ADPCM
|
1430 SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
|
1431 SNDRV_PCM_FMTBIT_S16_BE
),
1432 .rates
= SNDRV_PCM_RATE_KNOT
| SNDRV_PCM_RATE_8000_48000
,
1437 .buffer_bytes_max
= (32*1024),
1438 .period_bytes_min
= 4096,
1439 .period_bytes_max
= (32*1024),
1441 .periods_max
= 1024,
1444 static snd_pcm_hardware_t snd_cs4231_capture
=
1446 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1447 SNDRV_PCM_INFO_MMAP_VALID
| SNDRV_PCM_INFO_SYNC_START
),
1448 .formats
= (SNDRV_PCM_FMTBIT_MU_LAW
| SNDRV_PCM_FMTBIT_A_LAW
|
1449 SNDRV_PCM_FMTBIT_IMA_ADPCM
|
1450 SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
|
1451 SNDRV_PCM_FMTBIT_S16_BE
),
1452 .rates
= SNDRV_PCM_RATE_KNOT
| SNDRV_PCM_RATE_8000_48000
,
1457 .buffer_bytes_max
= (32*1024),
1458 .period_bytes_min
= 4096,
1459 .period_bytes_max
= (32*1024),
1461 .periods_max
= 1024,
1464 static int snd_cs4231_playback_open(snd_pcm_substream_t
*substream
)
1466 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1467 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1470 runtime
->hw
= snd_cs4231_playback
;
1472 if ((err
= snd_cs4231_open(chip
, CS4231_MODE_PLAY
)) < 0) {
1473 snd_free_pages(runtime
->dma_area
, runtime
->dma_bytes
);
1476 chip
->playback_substream
= substream
;
1477 chip
->p_periods_sent
= 0;
1478 snd_pcm_set_sync(substream
);
1479 snd_cs4231_xrate(runtime
);
1484 static int snd_cs4231_capture_open(snd_pcm_substream_t
*substream
)
1486 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1487 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1490 runtime
->hw
= snd_cs4231_capture
;
1492 if ((err
= snd_cs4231_open(chip
, CS4231_MODE_RECORD
)) < 0) {
1493 snd_free_pages(runtime
->dma_area
, runtime
->dma_bytes
);
1496 chip
->capture_substream
= substream
;
1497 chip
->c_periods_sent
= 0;
1498 snd_pcm_set_sync(substream
);
1499 snd_cs4231_xrate(runtime
);
1504 static int snd_cs4231_playback_close(snd_pcm_substream_t
*substream
)
1506 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1508 chip
->playback_substream
= NULL
;
1509 snd_cs4231_close(chip
, CS4231_MODE_PLAY
);
1514 static int snd_cs4231_capture_close(snd_pcm_substream_t
*substream
)
1516 cs4231_t
*chip
= snd_pcm_substream_chip(substream
);
1518 chip
->capture_substream
= NULL
;
1519 snd_cs4231_close(chip
, CS4231_MODE_RECORD
);
1524 /* XXX We can do some power-management, in particular on EBUS using
1525 * XXX the audio AUXIO register...
1528 static snd_pcm_ops_t snd_cs4231_playback_ops
= {
1529 .open
= snd_cs4231_playback_open
,
1530 .close
= snd_cs4231_playback_close
,
1531 .ioctl
= snd_pcm_lib_ioctl
,
1532 .hw_params
= snd_cs4231_playback_hw_params
,
1533 .hw_free
= snd_cs4231_playback_hw_free
,
1534 .prepare
= snd_cs4231_playback_prepare
,
1535 .trigger
= snd_cs4231_trigger
,
1536 .pointer
= snd_cs4231_playback_pointer
,
1539 static snd_pcm_ops_t snd_cs4231_capture_ops
= {
1540 .open
= snd_cs4231_capture_open
,
1541 .close
= snd_cs4231_capture_close
,
1542 .ioctl
= snd_pcm_lib_ioctl
,
1543 .hw_params
= snd_cs4231_capture_hw_params
,
1544 .hw_free
= snd_cs4231_capture_hw_free
,
1545 .prepare
= snd_cs4231_capture_prepare
,
1546 .trigger
= snd_cs4231_trigger
,
1547 .pointer
= snd_cs4231_capture_pointer
,
1550 static void snd_cs4231_pcm_free(snd_pcm_t
*pcm
)
1552 cs4231_t
*chip
= pcm
->private_data
;
1554 snd_pcm_lib_preallocate_free_for_all(pcm
);
1557 int snd_cs4231_pcm(cs4231_t
*chip
)
1562 if ((err
= snd_pcm_new(chip
->card
, "CS4231", 0, 1, 1, &pcm
)) < 0)
1565 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs4231_playback_ops
);
1566 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cs4231_capture_ops
);
1569 pcm
->private_data
= chip
;
1570 pcm
->private_free
= snd_cs4231_pcm_free
;
1571 pcm
->info_flags
= SNDRV_PCM_INFO_JOINT_DUPLEX
;
1572 strcpy(pcm
->name
, "CS4231");
1575 if (chip
->flags
& CS4231_FLAG_EBUS
) {
1576 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1577 snd_dma_pci_data(chip
->dev_u
.pdev
),
1582 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_SBUS
,
1583 snd_dma_sbus_data(chip
->dev_u
.sdev
),
1595 static void snd_cs4231_timer_free(snd_timer_t
*timer
)
1597 cs4231_t
*chip
= timer
->private_data
;
1601 int snd_cs4231_timer(cs4231_t
*chip
)
1607 /* Timer initialization */
1608 tid
.dev_class
= SNDRV_TIMER_CLASS_CARD
;
1609 tid
.dev_sclass
= SNDRV_TIMER_SCLASS_NONE
;
1610 tid
.card
= chip
->card
->number
;
1613 if ((err
= snd_timer_new(chip
->card
, "CS4231", &tid
, &timer
)) < 0)
1615 strcpy(timer
->name
, "CS4231");
1616 timer
->private_data
= chip
;
1617 timer
->private_free
= snd_cs4231_timer_free
;
1618 timer
->hw
= snd_cs4231_timer_table
;
1619 chip
->timer
= timer
;
1628 static int snd_cs4231_info_mux(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
*uinfo
)
1630 static char *texts
[4] = {
1631 "Line", "CD", "Mic", "Mix"
1633 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1635 snd_assert(chip
->card
!= NULL
, return -EINVAL
);
1636 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
1638 uinfo
->value
.enumerated
.items
= 4;
1639 if (uinfo
->value
.enumerated
.item
> 3)
1640 uinfo
->value
.enumerated
.item
= 3;
1641 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
1646 static int snd_cs4231_get_mux(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1648 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1649 unsigned long flags
;
1651 spin_lock_irqsave(&chip
->lock
, flags
);
1652 ucontrol
->value
.enumerated
.item
[0] =
1653 (chip
->image
[CS4231_LEFT_INPUT
] & CS4231_MIXS_ALL
) >> 6;
1654 ucontrol
->value
.enumerated
.item
[1] =
1655 (chip
->image
[CS4231_RIGHT_INPUT
] & CS4231_MIXS_ALL
) >> 6;
1656 spin_unlock_irqrestore(&chip
->lock
, flags
);
1661 static int snd_cs4231_put_mux(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1663 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1664 unsigned long flags
;
1665 unsigned short left
, right
;
1668 if (ucontrol
->value
.enumerated
.item
[0] > 3 ||
1669 ucontrol
->value
.enumerated
.item
[1] > 3)
1671 left
= ucontrol
->value
.enumerated
.item
[0] << 6;
1672 right
= ucontrol
->value
.enumerated
.item
[1] << 6;
1674 spin_lock_irqsave(&chip
->lock
, flags
);
1676 left
= (chip
->image
[CS4231_LEFT_INPUT
] & ~CS4231_MIXS_ALL
) | left
;
1677 right
= (chip
->image
[CS4231_RIGHT_INPUT
] & ~CS4231_MIXS_ALL
) | right
;
1678 change
= left
!= chip
->image
[CS4231_LEFT_INPUT
] ||
1679 right
!= chip
->image
[CS4231_RIGHT_INPUT
];
1680 snd_cs4231_out(chip
, CS4231_LEFT_INPUT
, left
);
1681 snd_cs4231_out(chip
, CS4231_RIGHT_INPUT
, right
);
1683 spin_unlock_irqrestore(&chip
->lock
, flags
);
1688 int snd_cs4231_info_single(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
*uinfo
)
1690 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
1692 uinfo
->type
= (mask
== 1) ?
1693 SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
1695 uinfo
->value
.integer
.min
= 0;
1696 uinfo
->value
.integer
.max
= mask
;
1701 int snd_cs4231_get_single(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1703 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1704 unsigned long flags
;
1705 int reg
= kcontrol
->private_value
& 0xff;
1706 int shift
= (kcontrol
->private_value
>> 8) & 0xff;
1707 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
1708 int invert
= (kcontrol
->private_value
>> 24) & 0xff;
1710 spin_lock_irqsave(&chip
->lock
, flags
);
1712 ucontrol
->value
.integer
.value
[0] = (chip
->image
[reg
] >> shift
) & mask
;
1714 spin_unlock_irqrestore(&chip
->lock
, flags
);
1717 ucontrol
->value
.integer
.value
[0] =
1718 (mask
- ucontrol
->value
.integer
.value
[0]);
1723 int snd_cs4231_put_single(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1725 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1726 unsigned long flags
;
1727 int reg
= kcontrol
->private_value
& 0xff;
1728 int shift
= (kcontrol
->private_value
>> 8) & 0xff;
1729 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
1730 int invert
= (kcontrol
->private_value
>> 24) & 0xff;
1734 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
1739 spin_lock_irqsave(&chip
->lock
, flags
);
1741 val
= (chip
->image
[reg
] & ~(mask
<< shift
)) | val
;
1742 change
= val
!= chip
->image
[reg
];
1743 snd_cs4231_out(chip
, reg
, val
);
1745 spin_unlock_irqrestore(&chip
->lock
, flags
);
1750 int snd_cs4231_info_double(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
*uinfo
)
1752 int mask
= (kcontrol
->private_value
>> 24) & 0xff;
1754 uinfo
->type
= mask
== 1 ?
1755 SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
1757 uinfo
->value
.integer
.min
= 0;
1758 uinfo
->value
.integer
.max
= mask
;
1763 int snd_cs4231_get_double(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1765 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1766 unsigned long flags
;
1767 int left_reg
= kcontrol
->private_value
& 0xff;
1768 int right_reg
= (kcontrol
->private_value
>> 8) & 0xff;
1769 int shift_left
= (kcontrol
->private_value
>> 16) & 0x07;
1770 int shift_right
= (kcontrol
->private_value
>> 19) & 0x07;
1771 int mask
= (kcontrol
->private_value
>> 24) & 0xff;
1772 int invert
= (kcontrol
->private_value
>> 22) & 1;
1774 spin_lock_irqsave(&chip
->lock
, flags
);
1776 ucontrol
->value
.integer
.value
[0] = (chip
->image
[left_reg
] >> shift_left
) & mask
;
1777 ucontrol
->value
.integer
.value
[1] = (chip
->image
[right_reg
] >> shift_right
) & mask
;
1779 spin_unlock_irqrestore(&chip
->lock
, flags
);
1782 ucontrol
->value
.integer
.value
[0] =
1783 (mask
- ucontrol
->value
.integer
.value
[0]);
1784 ucontrol
->value
.integer
.value
[1] =
1785 (mask
- ucontrol
->value
.integer
.value
[1]);
1791 int snd_cs4231_put_double(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
1793 cs4231_t
*chip
= snd_kcontrol_chip(kcontrol
);
1794 unsigned long flags
;
1795 int left_reg
= kcontrol
->private_value
& 0xff;
1796 int right_reg
= (kcontrol
->private_value
>> 8) & 0xff;
1797 int shift_left
= (kcontrol
->private_value
>> 16) & 0x07;
1798 int shift_right
= (kcontrol
->private_value
>> 19) & 0x07;
1799 int mask
= (kcontrol
->private_value
>> 24) & 0xff;
1800 int invert
= (kcontrol
->private_value
>> 22) & 1;
1802 unsigned short val1
, val2
;
1804 val1
= ucontrol
->value
.integer
.value
[0] & mask
;
1805 val2
= ucontrol
->value
.integer
.value
[1] & mask
;
1810 val1
<<= shift_left
;
1811 val2
<<= shift_right
;
1813 spin_lock_irqsave(&chip
->lock
, flags
);
1815 val1
= (chip
->image
[left_reg
] & ~(mask
<< shift_left
)) | val1
;
1816 val2
= (chip
->image
[right_reg
] & ~(mask
<< shift_right
)) | val2
;
1817 change
= val1
!= chip
->image
[left_reg
] || val2
!= chip
->image
[right_reg
];
1818 snd_cs4231_out(chip
, left_reg
, val1
);
1819 snd_cs4231_out(chip
, right_reg
, val2
);
1821 spin_unlock_irqrestore(&chip
->lock
, flags
);
1826 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1827 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1828 .info = snd_cs4231_info_single, \
1829 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1830 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1832 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1834 .info = snd_cs4231_info_double, \
1835 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1836 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1838 static snd_kcontrol_new_t snd_cs4231_controls
[] = {
1839 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT
, CS4231_RIGHT_OUTPUT
, 7, 7, 1, 1),
1840 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT
, CS4231_RIGHT_OUTPUT
, 0, 0, 63, 1),
1841 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN
, CS4231_RIGHT_LINE_IN
, 7, 7, 1, 1),
1842 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN
, CS4231_RIGHT_LINE_IN
, 0, 0, 31, 1),
1843 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT
, CS4231_AUX1_RIGHT_INPUT
, 7, 7, 1, 1),
1844 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT
, CS4231_AUX1_RIGHT_INPUT
, 0, 0, 31, 1),
1845 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT
, CS4231_AUX2_RIGHT_INPUT
, 7, 7, 1, 1),
1846 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT
, CS4231_AUX2_RIGHT_INPUT
, 0, 0, 31, 1),
1847 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL
, 7, 1, 1),
1848 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL
, 0, 15, 1),
1849 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL
, 6, 1, 1),
1850 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL
, 5, 1, 0),
1851 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT
, CS4231_RIGHT_INPUT
, 0, 0, 15, 0),
1853 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
1854 .name
= "Capture Source",
1855 .info
= snd_cs4231_info_mux
,
1856 .get
= snd_cs4231_get_mux
,
1857 .put
= snd_cs4231_put_mux
,
1859 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT
, CS4231_RIGHT_INPUT
, 5, 5, 1, 0),
1860 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK
, 0, 1, 0),
1861 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK
, 2, 63, 1),
1862 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
1863 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL
, 6, 1, 1),
1864 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL
, 7, 1, 1)
1867 int snd_cs4231_mixer(cs4231_t
*chip
)
1872 snd_assert(chip
!= NULL
&& chip
->pcm
!= NULL
, return -EINVAL
);
1876 strcpy(card
->mixername
, chip
->pcm
->name
);
1878 for (idx
= 0; idx
< ARRAY_SIZE(snd_cs4231_controls
); idx
++) {
1879 if ((err
= snd_ctl_add(card
,
1880 snd_ctl_new1(&snd_cs4231_controls
[idx
],
1889 static int cs4231_attach_begin(snd_card_t
**rcard
)
1895 if (dev
>= SNDRV_CARDS
)
1903 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
1907 strcpy(card
->driver
, "CS4231");
1908 strcpy(card
->shortname
, "Sun CS4231");
1914 static int cs4231_attach_finish(snd_card_t
*card
, cs4231_t
*chip
)
1918 if ((err
= snd_cs4231_pcm(chip
)) < 0)
1921 if ((err
= snd_cs4231_mixer(chip
)) < 0)
1924 if ((err
= snd_cs4231_timer(chip
)) < 0)
1927 if ((err
= snd_card_set_generic_dev(card
)) < 0)
1930 if ((err
= snd_card_register(card
)) < 0)
1933 chip
->next
= cs4231_list
;
1940 snd_card_free(card
);
1945 static int snd_cs4231_sbus_free(cs4231_t
*chip
)
1948 free_irq(chip
->irq
[0], chip
);
1951 sbus_iounmap(chip
->port
, chip
->regs_size
);
1954 snd_device_free(chip
->card
, chip
->timer
);
1961 static int snd_cs4231_sbus_dev_free(snd_device_t
*device
)
1963 cs4231_t
*cp
= device
->device_data
;
1965 return snd_cs4231_sbus_free(cp
);
1968 static snd_device_ops_t snd_cs4231_sbus_dev_ops
= {
1969 .dev_free
= snd_cs4231_sbus_dev_free
,
1972 static int __init
snd_cs4231_sbus_create(snd_card_t
*card
,
1973 struct sbus_dev
*sdev
,
1981 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1985 spin_lock_init(&chip
->lock
);
1986 init_MUTEX(&chip
->mce_mutex
);
1987 init_MUTEX(&chip
->open_mutex
);
1989 chip
->dev_u
.sdev
= sdev
;
1990 chip
->regs_size
= sdev
->reg_addrs
[0].reg_size
;
1991 memcpy(&chip
->image
, &snd_cs4231_original_image
,
1992 sizeof(snd_cs4231_original_image
));
1994 chip
->port
= sbus_ioremap(&sdev
->resource
[0], 0,
1995 chip
->regs_size
, "cs4231");
1997 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev
);
2001 if (request_irq(sdev
->irqs
[0], snd_cs4231_sbus_interrupt
,
2002 SA_SHIRQ
, "cs4231", chip
)) {
2003 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
2005 __irq_itoa(sdev
->irqs
[0]));
2006 snd_cs4231_sbus_free(chip
);
2009 chip
->irq
[0] = sdev
->irqs
[0];
2011 if (snd_cs4231_probe(chip
) < 0) {
2012 snd_cs4231_sbus_free(chip
);
2015 snd_cs4231_init(chip
);
2017 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
,
2018 chip
, &snd_cs4231_sbus_dev_ops
)) < 0) {
2019 snd_cs4231_sbus_free(chip
);
2027 static int cs4231_sbus_attach(struct sbus_dev
*sdev
)
2029 struct resource
*rp
= &sdev
->resource
[0];
2034 err
= cs4231_attach_begin(&card
);
2038 sprintf(card
->longname
, "%s at 0x%02lx:0x%08lx, irq %s",
2042 __irq_itoa(sdev
->irqs
[0]));
2044 if ((err
= snd_cs4231_sbus_create(card
, sdev
, dev
, &cp
)) < 0) {
2045 snd_card_free(card
);
2049 return cs4231_attach_finish(card
, cp
);
2054 static int snd_cs4231_ebus_free(cs4231_t
*chip
)
2056 if (chip
->eb2c
.regs
) {
2057 ebus_dma_unregister(&chip
->eb2c
);
2058 iounmap(chip
->eb2c
.regs
);
2060 if (chip
->eb2p
.regs
) {
2061 ebus_dma_unregister(&chip
->eb2p
);
2062 iounmap(chip
->eb2p
.regs
);
2066 iounmap(chip
->port
);
2068 snd_device_free(chip
->card
, chip
->timer
);
2075 static int snd_cs4231_ebus_dev_free(snd_device_t
*device
)
2077 cs4231_t
*cp
= device
->device_data
;
2079 return snd_cs4231_ebus_free(cp
);
2082 static snd_device_ops_t snd_cs4231_ebus_dev_ops
= {
2083 .dev_free
= snd_cs4231_ebus_dev_free
,
2086 static int __init
snd_cs4231_ebus_create(snd_card_t
*card
,
2087 struct linux_ebus_device
*edev
,
2095 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2099 spin_lock_init(&chip
->lock
);
2100 spin_lock_init(&chip
->eb2c
.lock
);
2101 spin_lock_init(&chip
->eb2p
.lock
);
2102 init_MUTEX(&chip
->mce_mutex
);
2103 init_MUTEX(&chip
->open_mutex
);
2104 chip
->flags
|= CS4231_FLAG_EBUS
;
2106 chip
->dev_u
.pdev
= edev
->bus
->self
;
2107 memcpy(&chip
->image
, &snd_cs4231_original_image
,
2108 sizeof(snd_cs4231_original_image
));
2109 strcpy(chip
->eb2c
.name
, "cs4231(capture)");
2110 chip
->eb2c
.flags
= EBUS_DMA_FLAG_USE_EBDMA_HANDLER
;
2111 chip
->eb2c
.callback
= snd_cs4231_ebus_capture_callback
;
2112 chip
->eb2c
.client_cookie
= chip
;
2113 chip
->eb2c
.irq
= edev
->irqs
[0];
2114 strcpy(chip
->eb2p
.name
, "cs4231(play)");
2115 chip
->eb2p
.flags
= EBUS_DMA_FLAG_USE_EBDMA_HANDLER
;
2116 chip
->eb2p
.callback
= snd_cs4231_ebus_play_callback
;
2117 chip
->eb2p
.client_cookie
= chip
;
2118 chip
->eb2p
.irq
= edev
->irqs
[1];
2120 chip
->port
= ioremap(edev
->resource
[0].start
, 0x10);
2121 chip
->eb2p
.regs
= ioremap(edev
->resource
[1].start
, 0x10);
2122 chip
->eb2c
.regs
= ioremap(edev
->resource
[2].start
, 0x10);
2123 if (!chip
->port
|| !chip
->eb2p
.regs
|| !chip
->eb2c
.regs
) {
2124 snd_cs4231_ebus_free(chip
);
2125 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev
);
2129 if (ebus_dma_register(&chip
->eb2c
)) {
2130 snd_cs4231_ebus_free(chip
);
2131 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev
);
2134 if (ebus_dma_irq_enable(&chip
->eb2c
, 1)) {
2135 snd_cs4231_ebus_free(chip
);
2136 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev
);
2140 if (ebus_dma_register(&chip
->eb2p
)) {
2141 snd_cs4231_ebus_free(chip
);
2142 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev
);
2145 if (ebus_dma_irq_enable(&chip
->eb2p
, 1)) {
2146 snd_cs4231_ebus_free(chip
);
2147 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev
);
2151 if (snd_cs4231_probe(chip
) < 0) {
2152 snd_cs4231_ebus_free(chip
);
2155 snd_cs4231_init(chip
);
2157 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
,
2158 chip
, &snd_cs4231_ebus_dev_ops
)) < 0) {
2159 snd_cs4231_ebus_free(chip
);
2167 static int cs4231_ebus_attach(struct linux_ebus_device
*edev
)
2173 err
= cs4231_attach_begin(&card
);
2177 sprintf(card
->longname
, "%s at 0x%lx, irq %s",
2179 edev
->resource
[0].start
,
2180 __irq_itoa(edev
->irqs
[0]));
2182 if ((err
= snd_cs4231_ebus_create(card
, edev
, dev
, &chip
)) < 0) {
2183 snd_card_free(card
);
2187 return cs4231_attach_finish(card
, chip
);
2191 static int __init
cs4231_init(void)
2194 struct sbus_bus
*sbus
;
2195 struct sbus_dev
*sdev
;
2198 struct linux_ebus
*ebus
;
2199 struct linux_ebus_device
*edev
;
2206 for_all_sbusdev(sdev
, sbus
) {
2207 if (!strcmp(sdev
->prom_name
, "SUNW,CS4231")) {
2208 if (cs4231_sbus_attach(sdev
) == 0)
2214 for_each_ebus(ebus
) {
2215 for_each_ebusdev(edev
, ebus
) {
2218 if (!strcmp(edev
->prom_name
, "SUNW,CS4231")) {
2220 } else if (!strcmp(edev
->prom_name
, "audio")) {
2223 prom_getstring(edev
->prom_node
, "compatible",
2224 compat
, sizeof(compat
));
2226 if (!strcmp(compat
, "SUNW,CS4231"))
2231 cs4231_ebus_attach(edev
) == 0)
2238 return (found
> 0) ? 0 : -EIO
;
2241 static void __exit
cs4231_exit(void)
2243 cs4231_t
*p
= cs4231_list
;
2246 cs4231_t
*next
= p
->next
;
2248 snd_card_free(p
->card
);
2256 module_init(cs4231_init
);
2257 module_exit(cs4231_exit
);