2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Despite the "SpeedStep" in the name, this is almost entirely unlike
6 * traditional SpeedStep.
8 * Modelled on speedstep.c
10 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
12 * WARNING WARNING WARNING
14 * This driver manipulates the PERF_CTL MSR, which is only somewhat
15 * documented. While it seems to work on my laptop, it has not been
16 * tested anywhere else, and it may not work for you, do strange
17 * things or simply crash.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/cpufreq.h>
24 #include <linux/config.h>
25 #include <linux/sched.h> /* current */
26 #include <linux/delay.h>
27 #include <linux/compiler.h>
29 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
30 #include <linux/acpi.h>
31 #include <acpi/processor.h>
35 #include <asm/processor.h>
36 #include <asm/cpufeature.h>
38 #include "speedstep-est-common.h"
40 #define PFX "speedstep-centrino: "
41 #define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
43 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
48 __u8 x86
; /* CPU family */
49 __u8 x86_model
; /* model */
50 __u8 x86_mask
; /* stepping */
62 static const struct cpu_id cpu_ids
[] = {
63 [CPU_BANIAS
] = { 6, 9, 5 },
64 [CPU_DOTHAN_A1
] = { 6, 13, 1 },
65 [CPU_DOTHAN_A2
] = { 6, 13, 2 },
66 [CPU_DOTHAN_B0
] = { 6, 13, 6 },
67 [CPU_MP4HT_D0
] = {15, 3, 4 },
68 [CPU_MP4HT_E0
] = {15, 4, 1 },
70 #define N_IDS ARRAY_SIZE(cpu_ids)
74 const struct cpu_id
*cpu_id
;
75 const char *model_name
;
76 unsigned max_freq
; /* max clock in kHz */
78 struct cpufreq_frequency_table
*op_points
; /* clock/voltage pairs */
80 static int centrino_verify_cpu_id(const struct cpuinfo_x86
*c
, const struct cpu_id
*x
);
82 /* Operating points for current CPU */
83 static struct cpu_model
*centrino_model
[NR_CPUS
];
84 static const struct cpu_id
*centrino_cpu
[NR_CPUS
];
86 static struct cpufreq_driver centrino_driver
;
88 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
90 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
91 frequency/voltage operating point; frequency in MHz, volts in mV.
92 This is stored as "index" in the structure. */
95 .frequency = (mhz) * 1000, \
96 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
100 * These voltage tables were derived from the Intel Pentium M
101 * datasheet, document 25261202.pdf, Table 5. I have verified they
102 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
106 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 static struct cpufreq_frequency_table banias_900
[] =
112 { .frequency
= CPUFREQ_TABLE_END
}
115 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
116 static struct cpufreq_frequency_table banias_1000
[] =
122 { .frequency
= CPUFREQ_TABLE_END
}
125 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
126 static struct cpufreq_frequency_table banias_1100
[] =
133 { .frequency
= CPUFREQ_TABLE_END
}
137 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
138 static struct cpufreq_frequency_table banias_1200
[] =
146 { .frequency
= CPUFREQ_TABLE_END
}
149 /* Intel Pentium M processor 1.30GHz (Banias) */
150 static struct cpufreq_frequency_table banias_1300
[] =
157 { .frequency
= CPUFREQ_TABLE_END
}
160 /* Intel Pentium M processor 1.40GHz (Banias) */
161 static struct cpufreq_frequency_table banias_1400
[] =
168 { .frequency
= CPUFREQ_TABLE_END
}
171 /* Intel Pentium M processor 1.50GHz (Banias) */
172 static struct cpufreq_frequency_table banias_1500
[] =
180 { .frequency
= CPUFREQ_TABLE_END
}
183 /* Intel Pentium M processor 1.60GHz (Banias) */
184 static struct cpufreq_frequency_table banias_1600
[] =
192 { .frequency
= CPUFREQ_TABLE_END
}
195 /* Intel Pentium M processor 1.70GHz (Banias) */
196 static struct cpufreq_frequency_table banias_1700
[] =
204 { .frequency
= CPUFREQ_TABLE_END
}
208 #define _BANIAS(cpuid, max, name) \
210 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
211 .max_freq = (max)*1000, \
212 .op_points = banias_##max, \
214 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
216 /* CPU models, their operating frequency range, and freq/voltage
218 static struct cpu_model models
[] =
220 _BANIAS(&cpu_ids
[CPU_BANIAS
], 900, " 900"),
230 /* NULL model_name is a wildcard */
231 { &cpu_ids
[CPU_DOTHAN_A1
], NULL
, 0, NULL
},
232 { &cpu_ids
[CPU_DOTHAN_A2
], NULL
, 0, NULL
},
233 { &cpu_ids
[CPU_DOTHAN_B0
], NULL
, 0, NULL
},
234 { &cpu_ids
[CPU_MP4HT_D0
], NULL
, 0, NULL
},
235 { &cpu_ids
[CPU_MP4HT_E0
], NULL
, 0, NULL
},
242 static int centrino_cpu_init_table(struct cpufreq_policy
*policy
)
244 struct cpuinfo_x86
*cpu
= &cpu_data
[policy
->cpu
];
245 struct cpu_model
*model
;
247 for(model
= models
; model
->cpu_id
!= NULL
; model
++)
248 if (centrino_verify_cpu_id(cpu
, model
->cpu_id
) &&
249 (model
->model_name
== NULL
||
250 strcmp(cpu
->x86_model_id
, model
->model_name
) == 0))
253 if (model
->cpu_id
== NULL
) {
254 /* No match at all */
255 dprintk(KERN_INFO PFX
"no support for CPU model \"%s\": "
256 "send /proc/cpuinfo to " MAINTAINER
"\n",
261 if (model
->op_points
== NULL
) {
262 /* Matched a non-match */
263 dprintk(KERN_INFO PFX
"no table support for CPU model \"%s\"\n",
265 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
266 dprintk(KERN_INFO PFX
"try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
271 centrino_model
[policy
->cpu
] = model
;
273 dprintk("found \"%s\": max frequency: %dkHz\n",
274 model
->model_name
, model
->max_freq
);
280 static inline int centrino_cpu_init_table(struct cpufreq_policy
*policy
) { return -ENODEV
; }
281 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
283 static int centrino_verify_cpu_id(const struct cpuinfo_x86
*c
, const struct cpu_id
*x
)
285 if ((c
->x86
== x
->x86
) &&
286 (c
->x86_model
== x
->x86_model
) &&
287 (c
->x86_mask
== x
->x86_mask
))
292 /* To be called only after centrino_model is initialized */
293 static unsigned extract_clock(unsigned msr
, unsigned int cpu
, int failsafe
)
298 * Extract clock in kHz from PERF_CTL value
299 * for centrino, as some DSDTs are buggy.
300 * Ideally, this can be done using the acpi_data structure.
302 if ((centrino_cpu
[cpu
] == &cpu_ids
[CPU_BANIAS
]) ||
303 (centrino_cpu
[cpu
] == &cpu_ids
[CPU_DOTHAN_A1
]) ||
304 (centrino_cpu
[cpu
] == &cpu_ids
[CPU_DOTHAN_B0
])) {
305 msr
= (msr
>> 8) & 0xff;
309 if ((!centrino_model
[cpu
]) || (!centrino_model
[cpu
]->op_points
))
313 for (i
=0;centrino_model
[cpu
]->op_points
[i
].frequency
!= CPUFREQ_TABLE_END
; i
++) {
314 if (msr
== centrino_model
[cpu
]->op_points
[i
].index
)
315 return centrino_model
[cpu
]->op_points
[i
].frequency
;
318 return centrino_model
[cpu
]->op_points
[i
-1].frequency
;
323 /* Return the current CPU frequency in kHz */
324 static unsigned int get_cur_freq(unsigned int cpu
)
328 cpumask_t saved_mask
;
330 saved_mask
= current
->cpus_allowed
;
331 set_cpus_allowed(current
, cpumask_of_cpu(cpu
));
332 if (smp_processor_id() != cpu
)
335 rdmsr(MSR_IA32_PERF_STATUS
, l
, h
);
336 clock_freq
= extract_clock(l
, cpu
, 0);
338 if (unlikely(clock_freq
== 0)) {
340 * On some CPUs, we can see transient MSR values (which are
341 * not present in _PSS), while CPU is doing some automatic
342 * P-state transition (like TM2). Get the last freq set
345 rdmsr(MSR_IA32_PERF_CTL
, l
, h
);
346 clock_freq
= extract_clock(l
, cpu
, 1);
349 set_cpus_allowed(current
, saved_mask
);
354 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
356 static struct acpi_processor_performance p
;
359 * centrino_cpu_init_acpi - register with ACPI P-States library
361 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
362 * in order to determine correct frequency and voltage pairings by reading
363 * the _PSS of the ACPI DSDT or SSDT tables.
365 static int centrino_cpu_init_acpi(struct cpufreq_policy
*policy
)
367 union acpi_object arg0
= {ACPI_TYPE_BUFFER
};
369 struct acpi_object_list arg_list
= {1, &arg0
};
370 unsigned long cur_freq
;
372 unsigned int cpu
= policy
->cpu
;
375 arg0
.buffer
.length
= 12;
376 arg0
.buffer
.pointer
= (u8
*) arg0_buf
;
377 arg0_buf
[0] = ACPI_PDC_REVISION_ID
;
379 arg0_buf
[2] = ACPI_PDC_EST_CAPABILITY_SMP_MSR
;
383 /* register with ACPI core */
384 if (acpi_processor_register_performance(&p
, cpu
)) {
385 dprintk(KERN_INFO PFX
"obtaining ACPI data failed\n");
389 /* verify the acpi_data */
390 if (p
.state_count
<= 1) {
391 dprintk("No P-States\n");
396 if ((p
.control_register
.space_id
!= ACPI_ADR_SPACE_FIXED_HARDWARE
) ||
397 (p
.status_register
.space_id
!= ACPI_ADR_SPACE_FIXED_HARDWARE
)) {
398 dprintk("Invalid control/status registers (%x - %x)\n",
399 p
.control_register
.space_id
, p
.status_register
.space_id
);
404 for (i
=0; i
<p
.state_count
; i
++) {
405 if (p
.states
[i
].control
!= p
.states
[i
].status
) {
406 dprintk("Different control (%llu) and status values (%llu)\n",
407 p
.states
[i
].control
, p
.states
[i
].status
);
412 if (!p
.states
[i
].core_frequency
) {
413 dprintk("Zero core frequency for state %u\n", i
);
418 if (p
.states
[i
].core_frequency
> p
.states
[0].core_frequency
) {
419 dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i
,
420 p
.states
[i
].core_frequency
, p
.states
[0].core_frequency
);
421 p
.states
[i
].core_frequency
= 0;
426 centrino_model
[cpu
] = kzalloc(sizeof(struct cpu_model
), GFP_KERNEL
);
427 if (!centrino_model
[cpu
]) {
432 centrino_model
[cpu
]->model_name
=NULL
;
433 centrino_model
[cpu
]->max_freq
= p
.states
[0].core_frequency
* 1000;
434 centrino_model
[cpu
]->op_points
= kmalloc(sizeof(struct cpufreq_frequency_table
) *
435 (p
.state_count
+ 1), GFP_KERNEL
);
436 if (!centrino_model
[cpu
]->op_points
) {
441 for (i
=0; i
<p
.state_count
; i
++) {
442 centrino_model
[cpu
]->op_points
[i
].index
= p
.states
[i
].control
;
443 centrino_model
[cpu
]->op_points
[i
].frequency
= p
.states
[i
].core_frequency
* 1000;
444 dprintk("adding state %i with frequency %u and control value %04x\n",
445 i
, centrino_model
[cpu
]->op_points
[i
].frequency
, centrino_model
[cpu
]->op_points
[i
].index
);
447 centrino_model
[cpu
]->op_points
[p
.state_count
].frequency
= CPUFREQ_TABLE_END
;
449 cur_freq
= get_cur_freq(cpu
);
451 for (i
=0; i
<p
.state_count
; i
++) {
452 if (!p
.states
[i
].core_frequency
) {
453 dprintk("skipping state %u\n", i
);
454 centrino_model
[cpu
]->op_points
[i
].frequency
= CPUFREQ_ENTRY_INVALID
;
458 if (extract_clock(centrino_model
[cpu
]->op_points
[i
].index
, cpu
, 0) !=
459 (centrino_model
[cpu
]->op_points
[i
].frequency
)) {
460 dprintk("Invalid encoded frequency (%u vs. %u)\n",
461 extract_clock(centrino_model
[cpu
]->op_points
[i
].index
, cpu
, 0),
462 centrino_model
[cpu
]->op_points
[i
].frequency
);
467 if (cur_freq
== centrino_model
[cpu
]->op_points
[i
].frequency
)
471 /* notify BIOS that we exist */
472 acpi_processor_notify_smm(THIS_MODULE
);
477 kfree(centrino_model
[cpu
]->op_points
);
479 kfree(centrino_model
[cpu
]);
481 acpi_processor_unregister_performance(&p
, cpu
);
482 dprintk(KERN_INFO PFX
"invalid ACPI data\n");
486 static inline int centrino_cpu_init_acpi(struct cpufreq_policy
*policy
) { return -ENODEV
; }
489 static int centrino_cpu_init(struct cpufreq_policy
*policy
)
491 struct cpuinfo_x86
*cpu
= &cpu_data
[policy
->cpu
];
497 /* Only Intel makes Enhanced Speedstep-capable CPUs */
498 if (cpu
->x86_vendor
!= X86_VENDOR_INTEL
|| !cpu_has(cpu
, X86_FEATURE_EST
))
501 if (is_const_loops_cpu(policy
->cpu
)) {
502 centrino_driver
.flags
|= CPUFREQ_CONST_LOOPS
;
505 if (centrino_cpu_init_acpi(policy
)) {
506 if (policy
->cpu
!= 0)
509 for (i
= 0; i
< N_IDS
; i
++)
510 if (centrino_verify_cpu_id(cpu
, &cpu_ids
[i
]))
514 centrino_cpu
[policy
->cpu
] = &cpu_ids
[i
];
516 if (!centrino_cpu
[policy
->cpu
]) {
517 dprintk(KERN_INFO PFX
"found unsupported CPU with "
518 "Enhanced SpeedStep: send /proc/cpuinfo to "
523 if (centrino_cpu_init_table(policy
)) {
528 /* Check to see if Enhanced SpeedStep is enabled, and try to
530 rdmsr(MSR_IA32_MISC_ENABLE
, l
, h
);
532 if (!(l
& (1<<16))) {
534 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l
);
535 wrmsr(MSR_IA32_MISC_ENABLE
, l
, h
);
537 /* check to see if it stuck */
538 rdmsr(MSR_IA32_MISC_ENABLE
, l
, h
);
539 if (!(l
& (1<<16))) {
540 printk(KERN_INFO PFX
"couldn't enable Enhanced SpeedStep\n");
545 freq
= get_cur_freq(policy
->cpu
);
547 policy
->governor
= CPUFREQ_DEFAULT_GOVERNOR
;
548 policy
->cpuinfo
.transition_latency
= 10000; /* 10uS transition latency */
551 dprintk("centrino_cpu_init: cur=%dkHz\n", policy
->cur
);
553 ret
= cpufreq_frequency_table_cpuinfo(policy
, centrino_model
[policy
->cpu
]->op_points
);
557 cpufreq_frequency_table_get_attr(centrino_model
[policy
->cpu
]->op_points
, policy
->cpu
);
562 static int centrino_cpu_exit(struct cpufreq_policy
*policy
)
564 unsigned int cpu
= policy
->cpu
;
566 if (!centrino_model
[cpu
])
569 cpufreq_frequency_table_put_attr(cpu
);
571 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
572 if (!centrino_model
[cpu
]->model_name
) {
573 dprintk("unregistering and freeing ACPI data\n");
574 acpi_processor_unregister_performance(&p
, cpu
);
575 kfree(centrino_model
[cpu
]->op_points
);
576 kfree(centrino_model
[cpu
]);
580 centrino_model
[cpu
] = NULL
;
586 * centrino_verify - verifies a new CPUFreq policy
587 * @policy: new policy
589 * Limit must be within this model's frequency range at least one
592 static int centrino_verify (struct cpufreq_policy
*policy
)
594 return cpufreq_frequency_table_verify(policy
, centrino_model
[policy
->cpu
]->op_points
);
598 * centrino_setpolicy - set a new CPUFreq policy
599 * @policy: new policy
600 * @target_freq: the target frequency
601 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
603 * Sets a new CPUFreq policy.
605 static int centrino_target (struct cpufreq_policy
*policy
,
606 unsigned int target_freq
,
607 unsigned int relation
)
609 unsigned int newstate
= 0;
610 unsigned int msr
, oldmsr
, h
, cpu
= policy
->cpu
;
611 struct cpufreq_freqs freqs
;
612 cpumask_t saved_mask
;
615 if (centrino_model
[cpu
] == NULL
)
619 * Support for SMP systems.
620 * Make sure we are running on the CPU that wants to change frequency
622 saved_mask
= current
->cpus_allowed
;
623 set_cpus_allowed(current
, policy
->cpus
);
624 if (!cpu_isset(smp_processor_id(), policy
->cpus
)) {
625 dprintk("couldn't limit to CPUs in this domain\n");
629 if (cpufreq_frequency_table_target(policy
, centrino_model
[cpu
]->op_points
, target_freq
,
630 relation
, &newstate
)) {
635 msr
= centrino_model
[cpu
]->op_points
[newstate
].index
;
636 rdmsr(MSR_IA32_PERF_CTL
, oldmsr
, h
);
638 if (msr
== (oldmsr
& 0xffff)) {
640 dprintk("no change needed - msr was and needs to be %x\n", oldmsr
);
645 freqs
.old
= extract_clock(oldmsr
, cpu
, 0);
646 freqs
.new = extract_clock(msr
, cpu
, 0);
648 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
649 target_freq
, freqs
.old
, freqs
.new, msr
);
651 cpufreq_notify_transition(&freqs
, CPUFREQ_PRECHANGE
);
653 /* all but 16 LSB are "reserved", so treat them with
659 wrmsr(MSR_IA32_PERF_CTL
, oldmsr
, h
);
661 cpufreq_notify_transition(&freqs
, CPUFREQ_POSTCHANGE
);
665 set_cpus_allowed(current
, saved_mask
);
669 static struct freq_attr
* centrino_attr
[] = {
670 &cpufreq_freq_attr_scaling_available_freqs
,
674 static struct cpufreq_driver centrino_driver
= {
675 .name
= "centrino", /* should be speedstep-centrino,
676 but there's a 16 char limit */
677 .init
= centrino_cpu_init
,
678 .exit
= centrino_cpu_exit
,
679 .verify
= centrino_verify
,
680 .target
= centrino_target
,
682 .attr
= centrino_attr
,
683 .owner
= THIS_MODULE
,
688 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
690 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
691 * unsupported devices, -ENOENT if there's no voltage table for this
692 * particular CPU model, -EINVAL on problems during initiatization,
693 * and zero on success.
695 * This is quite picky. Not only does the CPU have to advertise the
696 * "est" flag in the cpuid capability flags, we look for a specific
697 * CPU model and stepping, and we need to have the exact model name in
698 * our voltage tables. That is, be paranoid about not releasing
699 * someone's valuable magic smoke.
701 static int __init
centrino_init(void)
703 struct cpuinfo_x86
*cpu
= cpu_data
;
705 if (!cpu_has(cpu
, X86_FEATURE_EST
))
708 return cpufreq_register_driver(¢rino_driver
);
711 static void __exit
centrino_exit(void)
713 cpufreq_unregister_driver(¢rino_driver
);
716 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
717 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
718 MODULE_LICENSE ("GPL");
720 late_initcall(centrino_init
);
721 module_exit(centrino_exit
);