arch/arm/mach-ns9xxx/include/mach/regs-mem.h

   1 /*
   2  * arch/arm/mach-ns9xxx/include/mach/regs-mem.h
   3  *
   4  * Copyright (C) 2006 by Digi International Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #ifndef __ASM_ARCH_REGSMEM_H
  12 #define __ASM_ARCH_REGSMEM_H
  13
  14 #include <mach/hardware.h>
  15
  16 /* Memory Module */
  17
  18 /* Control register */
  19 #define MEM_CTRL        __REG(0xa0700000)
  20
  21 /* Status register */
  22 #define MEM_STAT        __REG(0xa0700004)
  23
  24 /* Configuration register */
  25 #define MEM_CONF        __REG(0xa0700008)
  26
  27 /* Dynamic Memory Control register */
  28 #define MEM_DMCTRL      __REG(0xa0700020)
  29
  30 /* Dynamic Memory Refresh Timer */
  31 #define MEM_DMRT        __REG(0xa0700024)
  32
  33 /* Dynamic Memory Read Configuration register */
  34 #define MEM_DMRC        __REG(0xa0700028)
  35
  36 /* Dynamic Memory Precharge Command Period (tRP) */
  37 #define MEM_DMPCP       __REG(0xa0700030)
  38
  39 /* Dynamic Memory Active to Precharge Command Period (tRAS) */
  40 #define MEM_DMAPCP      __REG(0xa0700034)
  41
  42 /* Dynamic Memory Self-Refresh Exit Time (tSREX) */
  43 #define MEM_DMSRET      __REG(0xa0700038)
  44
  45 /* Dynamic Memory Last Data Out to Active Time (tAPR) */
  46 #define MEM_DMLDOAT     __REG(0xa070003c)
  47
  48 /* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
  49 #define MEM_DMDIACT     __REG(0xa0700040)
  50
  51 /* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
  52 #define MEM_DMWRT       __REG(0xa0700044)
  53
  54 /* Dynamic Memory Active to Active Command Period (tRC) */
  55 #define MEM_DMAACP      __REG(0xa0700048)
  56
  57 /* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
  58 #define MEM_DMARP       __REG(0xa070004c)
  59
  60 /* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
  61 #define MEM_DMESRAC     __REG(0xa0700050)
  62
  63 /* Dynamic Memory Active Bank A to Active B Time (tRRD) */
  64 #define MEM_DMABAABT    __REG(0xa0700054)
  65
  66 /* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
  67 #define MEM_DMLMACT     __REG(0xa0700058)
  68
  69 /* Static Memory Extended Wait */
  70 #define MEM_SMEW        __REG(0xa0700080)
  71
  72 /* Dynamic Memory Configuration Register x */
  73 #define MEM_DMCONF(x)   __REG2(0xa0700100, (x) << 3)
  74
  75 /* Dynamic Memory RAS and CAS Delay x */
  76 #define MEM_DMRCD(x)    __REG2(0xa0700104, (x) << 3)
  77
  78 /* Static Memory Configuration Register x */
  79 #define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
  80
  81 /* Static Memory Configuration Register x: Write protect */
  82 #define MEM_SMC_PSMC            __REGBIT(20)
  83 #define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
  84 #define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
  85
  86 /* Static Memory Configuration Register x: Buffer enable */
  87 #define MEM_SMC_BSMC            __REGBIT(19)
  88 #define MEM_SMC_BSMC_OFF                __REGVAL(MEM_SMC_BSMC, 0)
  89 #define MEM_SMC_BSMC_ON                 __REGVAL(MEM_SMC_BSMC, 1)
  90
  91 /* Static Memory Configuration Register x: Extended Wait */
  92 #define MEM_SMC_EW              __REGBIT(8)
  93 #define MEM_SMC_EW_OFF                  __REGVAL(MEM_SMC_EW, 0)
  94 #define MEM_SMC_EW_ON                   __REGVAL(MEM_SMC_EW, 1)
  95
  96 /* Static Memory Configuration Register x: Byte lane state */
  97 #define MEM_SMC_PB              __REGBIT(7)
  98 #define MEM_SMC_PB_0                    __REGVAL(MEM_SMC_PB, 0)
  99 #define MEM_SMC_PB_1                    __REGVAL(MEM_SMC_PB, 1)
 100
 101 /* Static Memory Configuration Register x: Chip select polarity */
 102 #define MEM_SMC_PC              __REGBIT(6)
 103 #define MEM_SMC_PC_AL                   __REGVAL(MEM_SMC_PC, 0)
 104 #define MEM_SMC_PC_AH                   __REGVAL(MEM_SMC_PC, 1)
 105
 106 /* static memory configuration register x: page mode*/
 107 #define MEM_SMC_PM              __REGBIT(3)
 108 #define MEM_SMC_PM_DIS                  __REGVAL(MEM_SMC_PM, 0)
 109 #define MEM_SMC_PM_ASYNC                __REGVAL(MEM_SMC_PM, 1)
 110
 111 /* static memory configuration register x: Memory width */
 112 #define MEM_SMC_MW              __REGBITS(1, 0)
 113 #define MEM_SMC_MW_8                    __REGVAL(MEM_SMC_MW, 0)
 114 #define MEM_SMC_MW_16                   __REGVAL(MEM_SMC_MW, 1)
 115 #define MEM_SMC_MW_32                   __REGVAL(MEM_SMC_MW, 2)
 116
 117 /* Static Memory Write Enable Delay x */
 118 #define MEM_SMWED(x)    __REG2(0xa0700204, (x) << 3)
 119
 120 /* Static Memory Output Enable Delay x */
 121 #define MEM_SMOED(x)    __REG2(0xa0700208, (x) << 3)
 122
 123 /* Static Memory Read Delay x */
 124 #define MEM_SMRD(x)     __REG2(0xa070020c, (x) << 3)
 125
 126 /* Static Memory Page Mode Read Delay 0 */
 127 #define MEM_SMPMRD(x)   __REG2(0xa0700210, (x) << 3)
 128
 129 /* Static Memory Write Delay */
 130 #define MEM_SMWD(x)     __REG2(0xa0700214, (x) << 3)
 131
 132 /* Static Memory Turn Round Delay x */
 133 #define MEM_SWT(x)      __REG2(0xa0700218, (x) << 3)
 134
 135 #endif /* ifndef __ASM_ARCH_REGSMEM_H */