arch/arm/plat-mxc/include/mach/board-mx27ads.h

   1 /*
   2  * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
  15 #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
  16
  17 /* external interrupt multiplexer */
  18 #define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
  19
  20 #define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
  21 #define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
  22 #define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
  23 #define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
  24
  25 #define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
  26                                 MXC_MAX_VIRTUAL_INTS)
  27
  28 /*
  29  * @name Memory Size parameters
  30  */
  31
  32 /*
  33  * Size of SDRAM memory
  34  */
  35 #define SDRAM_MEM_SIZE          SZ_128M
  36
  37 /*
  38  * PBC Controller parameters
  39  */
  40
  41 /*
  42  * Base address of PBC controller, CS4
  43  */
  44 #define PBC_BASE_ADDRESS        0xf4300000
  45 #define PBC_REG_ADDR(offset)    (void __force __iomem *) \
  46                 (PBC_BASE_ADDRESS + (offset))
  47
  48 /*
  49  * PBC Interupt name definitions
  50  */
  51 #define PBC_GPIO1_0  0
  52 #define PBC_GPIO1_1  1
  53 #define PBC_GPIO1_2  2
  54 #define PBC_GPIO1_3  3
  55 #define PBC_GPIO1_4  4
  56 #define PBC_GPIO1_5  5
  57
  58 #define PBC_INTR_MAX_NUM 6
  59 #define PBC_INTR_SHARED_MAX_NUM 8
  60
  61 /* When the PBC address connection is fixed in h/w, defined as 1 */
  62 #define PBC_ADDR_SH             0
  63
  64 /* Offsets for the PBC Controller register */
  65 /*
  66  * PBC Board version register offset
  67  */
  68 #define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
  69 /*
  70  * PBC Board control register 1 set address.
  71  */
  72 #define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
  73 /*
  74  * PBC Board control register 1 clear address.
  75  */
  76 #define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
  77 /*
  78  * PBC Board control register 2 set address.
  79  */
  80 #define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
  81 /*
  82  * PBC Board control register 2 clear address.
  83  */
  84 #define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
  85 /*
  86  * PBC Board control register 3 set address.
  87  */
  88 #define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
  89 /*
  90  * PBC Board control register 3 clear address.
  91  */
  92 #define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
  93 /*
  94  * PBC Board control register 3 set address.
  95  */
  96 #define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
  97 /*
  98  * PBC Board control register 4 clear address.
  99  */
 100 #define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
 101 /*PBC_ADDR_SH
 102  * PBC Board status register 1.
 103  */
 104 #define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
 105 /*
 106  * PBC Board interrupt status register.
 107  */
 108 #define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
 109 /*
 110  * PBC Board interrupt current status register.
 111  */
 112 #define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
 113 /*
 114  * PBC Interrupt mask register set address.
 115  */
 116 #define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
 117 /*
 118  * PBC Interrupt mask register clear address.
 119  */
 120 #define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
 121 /*
 122  * External UART A.
 123  */
 124 #define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
 125 /*
 126  * UART 4 Expanding Signal Status.
 127  */
 128 #define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
 129 /*
 130  * UART 4 Expanding Signal Control Set.
 131  */
 132 #define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
 133 /*
 134  * UART 4 Expanding Signal Control Clear.
 135  */
 136 #define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
 137 /*
 138  * Ethernet Controller IO base address.
 139  */
 140 #define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
 141 /*
 142  * Ethernet Controller Memory base address.
 143  */
 144 #define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
 145 /*
 146  * Ethernet Controller DMA base address.
 147  */
 148 #define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
 149
 150 /* PBC Board Version Register bit definition */
 151 #define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
 152 #define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
 153
 154 /* PBC Board Control Register 1 bit definitions */
 155 #define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
 156 #define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
 157 #define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
 158 #define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
 159 #define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
 160
 161 /* PBC Board Control Register 2 bit definitions */
 162 #define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
 163 #define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
 164 #define PBC_BCTRL2_ATAFEC_EN    0X0010
 165 #define PBC_BCTRL2_ATAFEC_SEL   0X0020
 166 #define PBC_BCTRL2_ATA_EN       0X0040
 167 #define PBC_BCTRL2_IRDA_SD      0X0080
 168 #define PBC_BCTRL2_IRDA_EN      0X0100
 169 #define PBC_BCTRL2_CCTL10       0X0200
 170 #define PBC_BCTRL2_CCTL11       0X0400
 171
 172 /* PBC Board Control Register 3 bit definitions */
 173 #define PBC_BCTRL3_HSH_EN       0X0020
 174 #define PBC_BCTRL3_FSH_MOD      0X0040
 175 #define PBC_BCTRL3_OTG_HS_EN    0X0080
 176 #define PBC_BCTRL3_OTG_VBUS_EN  0X0100
 177 #define PBC_BCTRL3_FSH_VBUS_EN  0X0200
 178 #define PBC_BCTRL3_USB_OTG_ON   0X0800
 179 #define PBC_BCTRL3_USB_FSH_ON   0X1000
 180
 181 /* PBC Board Control Register 4 bit definitions */
 182 #define PBC_BCTRL4_REGEN_SEL    0X0001
 183 #define PBC_BCTRL4_USER_OFF     0X0002
 184 #define PBC_BCTRL4_VIB_EN       0X0004
 185 #define PBC_BCTRL4_PWRGT1_EN    0X0008
 186 #define PBC_BCTRL4_PWRGT2_EN    0X0010
 187 #define PBC_BCTRL4_STDBY_PRI    0X0020
 188
 189 #ifndef __ASSEMBLY__
 190 /*
 191  * Enumerations for SD cards and memory stick card. This corresponds to
 192  * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
 193  */
 194 enum mxc_card_no {
 195         MXC_CARD_SD2 = 0,
 196         MXC_CARD_SD3,
 197         MXC_CARD_MS,
 198         MXC_CARD_SD1,
 199         MXC_CARD_MIN = MXC_CARD_SD2,
 200         MXC_CARD_MAX = MXC_CARD_SD1,
 201 };
 202 #endif
 203
 204 #define MXC_CPLD_VER_1_50       0x01
 205
 206 /*
 207  * PBC BSTAT Register bit definitions
 208  */
 209 #define PBC_BSTAT_PRI_INT       0X0001
 210 #define PBC_BSTAT_USB_BYP       0X0002
 211 #define PBC_BSTAT_ATA_IOCS16    0X0004
 212 #define PBC_BSTAT_ATA_CBLID     0X0008
 213 #define PBC_BSTAT_ATA_DASP      0X0010
 214 #define PBC_BSTAT_PWR_RDY       0X0020
 215 #define PBC_BSTAT_SD3_WP        0X0100
 216 #define PBC_BSTAT_SD2_WP        0X0200
 217 #define PBC_BSTAT_SD1_WP        0X0400
 218 #define PBC_BSTAT_SD3_DET       0X0800
 219 #define PBC_BSTAT_SD2_DET       0X1000
 220 #define PBC_BSTAT_SD1_DET       0X2000
 221 #define PBC_BSTAT_MS_DET        0X4000
 222 #define PBC_BSTAT_SD3_DET_BIT   11
 223 #define PBC_BSTAT_SD2_DET_BIT   12
 224 #define PBC_BSTAT_SD1_DET_BIT   13
 225 #define PBC_BSTAT_MS_DET_BIT    14
 226 #define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
 227                                  ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
 228                                  ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
 229                                  ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
 230                                         0x0))))
 231
 232 /*
 233  * PBC UART Control Register bit definitions
 234  */
 235 #define PBC_UCTRL_DCE_DCD       0X0001
 236 #define PBC_UCTRL_DCE_DSR       0X0002
 237 #define PBC_UCTRL_DCE_RI        0X0004
 238 #define PBC_UCTRL_DTE_DTR       0X0100
 239
 240 /*
 241  * PBC UART Status Register bit definitions
 242  */
 243 #define PBC_USTAT_DTE_DCD       0X0001
 244 #define PBC_USTAT_DTE_DSR       0X0002
 245 #define PBC_USTAT_DTE_RI        0X0004
 246 #define PBC_USTAT_DCE_DTR       0X0100
 247
 248 /*
 249  * PBC Interupt mask register bit definitions
 250  */
 251 #define PBC_INTR_SD3_R_EN_BIT   4
 252 #define PBC_INTR_SD2_R_EN_BIT   0
 253 #define PBC_INTR_SD1_R_EN_BIT   6
 254 #define PBC_INTR_MS_R_EN_BIT    5
 255 #define PBC_INTR_SD3_EN_BIT     13
 256 #define PBC_INTR_SD2_EN_BIT     12
 257 #define PBC_INTR_MS_EN_BIT      14
 258 #define PBC_INTR_SD1_EN_BIT     15
 259
 260 #define PBC_INTR_SD2_R_EN       0x0001
 261 #define PBC_INTR_LOW_BAT        0X0002
 262 #define PBC_INTR_OTG_FSOVER     0X0004
 263 #define PBC_INTR_FSH_OVER       0X0008
 264 #define PBC_INTR_SD3_R_EN       0x0010
 265 #define PBC_INTR_MS_R_EN        0x0020
 266 #define PBC_INTR_SD1_R_EN       0x0040
 267 #define PBC_INTR_FEC_INT        0X0080
 268 #define PBC_INTR_ENET_INT       0X0100
 269 #define PBC_INTR_OTGFS_INT      0X0200
 270 #define PBC_INTR_XUART_INT      0X0400
 271 #define PBC_INTR_CCTL12         0X0800
 272 #define PBC_INTR_SD2_EN         0x1000
 273 #define PBC_INTR_SD3_EN         0x2000
 274 #define PBC_INTR_MS_EN          0x4000
 275 #define PBC_INTR_SD1_EN         0x8000
 276
 277
 278
 279 /* For interrupts like xuart, enet etc */
 280 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
 281 #define MXC_MAX_EXP_IO_LINES    16
 282
 283 /*
 284  * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
 285  *
 286  */
 287 #define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
 288 #define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
 289 #define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
 290 #define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
 291 #define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
 292 #define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
 293 #define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
 294 #define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
 295 #define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
 296 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
 297 #define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
 298 #define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
 299 #define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
 300 #define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
 301 #define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
 302
 303 /*
 304  * This is System IRQ used by CS8900A for interrupt generation
 305  * taken from platform.h
 306  */
 307 #define CS8900AIRQ              EXPIO_INT_ENET_INT
 308 /* This is I/O Base address used to access registers of CS8900A on MXC ADS */
 309 #define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
 310
 311 #define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
 312
 313 /*
 314 * This is used to detect if the CPLD version is for mx27 evb board rev-a
 315 */
 316 #define PBC_CPLD_VERSION_IS_REVA() \
 317         ((__raw_readw(PBC_VERSION_REG) & \
 318         (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
 319         == 0)
 320
 321 /* This is used to active or inactive ata signal in CPLD .
 322  *  It is dependent with hardware
 323  */
 324 #define PBC_ATA_SIGNAL_ACTIVE() \
 325         __raw_writew(           \
 326                 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
 327                 PBC_BCTRL2_CLEAR_REG)
 328
 329 #define PBC_ATA_SIGNAL_INACTIVE() \
 330         __raw_writew(  \
 331                 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
 332                 PBC_BCTRL2_SET_REG)
 333
 334 #define MXC_BD_LED1             (1 << 5)
 335 #define MXC_BD_LED2             (1 << 6)
 336 #define MXC_BD_LED_ON(led) \
 337         __raw_writew(led, PBC_BCTRL1_SET_REG)
 338 #define MXC_BD_LED_OFF(led) \
 339         __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
 340
 341 /* to determine the correct external crystal reference */
 342 #define CKIH_27MHZ_BIT_SET      (1 << 3)
 343
 344 #endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */