arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h

   1 /*
   2  *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
   3  *
   4  *  i.MX DMA registration and IRQ dispatching
   5  *
   6  * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
   7  * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
   8  * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301, USA.
  23  */
  24
  25 #ifndef __ASM_ARCH_MXC_DMA_H
  26 #define __ASM_ARCH_MXC_DMA_H
  27
  28 #define IMX_DMA_CHANNELS  16
  29
  30 #define DMA_MODE_READ           0
  31 #define DMA_MODE_WRITE          1
  32 #define DMA_MODE_MASK           1
  33
  34 #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
  35
  36 #define IMX_DMA_MEMSIZE_32      (0 << 4)
  37 #define IMX_DMA_MEMSIZE_8       (1 << 4)
  38 #define IMX_DMA_MEMSIZE_16      (2 << 4)
  39 #define IMX_DMA_TYPE_LINEAR     (0 << 10)
  40 #define IMX_DMA_TYPE_2D         (1 << 10)
  41 #define IMX_DMA_TYPE_FIFO       (2 << 10)
  42
  43 #define IMX_DMA_ERR_BURST     (1 << 0)
  44 #define IMX_DMA_ERR_REQUEST   (1 << 1)
  45 #define IMX_DMA_ERR_TRANSFER  (1 << 2)
  46 #define IMX_DMA_ERR_BUFFER    (1 << 3)
  47 #define IMX_DMA_ERR_TIMEOUT   (1 << 4)
  48
  49 int
  50 imx_dma_config_channel(int channel, unsigned int config_port,
  51         unsigned int config_mem, unsigned int dmareq, int hw_chaining);
  52
  53 void
  54 imx_dma_config_burstlen(int channel, unsigned int burstlen);
  55
  56 int
  57 imx_dma_setup_single(int channel, dma_addr_t dma_address,
  58                 unsigned int dma_length, unsigned int dev_addr,
  59                 unsigned int dmamode);
  60
  61 int
  62 imx_dma_setup_sg(int channel, struct scatterlist *sg,
  63                 unsigned int sgcount, unsigned int dma_length,
  64                 unsigned int dev_addr, unsigned int dmamode);
  65
  66 int
  67 imx_dma_setup_handlers(int channel,
  68                 void (*irq_handler) (int, void *),
  69                 void (*err_handler) (int, void *, int), void *data);
  70
  71 int
  72 imx_dma_setup_progression_handler(int channel,
  73                 void (*prog_handler) (int, void*, struct scatterlist*));
  74
  75 void imx_dma_enable(int channel);
  76
  77 void imx_dma_disable(int channel);
  78
  79 int imx_dma_request(int channel, const char *name);
  80
  81 void imx_dma_free(int channel);
  82
  83 enum imx_dma_prio {
  84         DMA_PRIO_HIGH = 0,
  85         DMA_PRIO_MEDIUM = 1,
  86         DMA_PRIO_LOW = 2
  87 };
  88
  89 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
  90
  91 #endif  /* _ASM_ARCH_MXC_DMA_H */