arch/arm/plat-mxc/include/mach/irqs.h

   1 /*
   2  *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_ARCH_MXC_IRQS_H__
  12 #define __ASM_ARCH_MXC_IRQS_H__
  13
  14 /*
  15  * So far all i.MX SoCs have 64 internal interrupts
  16  */
  17 #define MXC_INTERNAL_IRQS       64
  18
  19 #define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
  20
  21 #if defined CONFIG_ARCH_MX1
  22 #define MXC_GPIO_IRQS           (32 * 4)
  23 #elif defined CONFIG_ARCH_MX2
  24 #define MXC_GPIO_IRQS           (32 * 6)
  25 #elif defined CONFIG_ARCH_MX3
  26 #define MXC_GPIO_IRQS           (32 * 3)
  27 #elif defined CONFIG_ARCH_MX25
  28 #define MXC_GPIO_IRQS           (32 * 4)
  29 #elif defined CONFIG_ARCH_MXC91231
  30 #define MXC_GPIO_IRQS           (32 * 4)
  31 #endif
  32
  33 /*
  34  * The next 16 interrupts are for board specific purposes.  Since
  35  * the kernel can only run on one machine at a time, we can re-use
  36  * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
  37  * within sensible limits.
  38  */
  39 #define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
  40 #define MXC_BOARD_IRQS  16
  41
  42 #define MXC_IPU_IRQ_START       (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
  43
  44 #ifdef CONFIG_MX3_IPU_IRQS
  45 #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
  46 #else
  47 #define MX3_IPU_IRQS 0
  48 #endif
  49
  50 #define NR_IRQS                 (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
  51
  52 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
  53
  54 /* all normal IRQs can be FIQs */
  55 #define FIQ_START       0
  56 /* switch betwean IRQ and FIQ */
  57 extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
  58
  59 #endif /* __ASM_ARCH_MXC_IRQS_H__ */