arch/arm/plat-mxc/system.c

   1 /*
   2  * Copyright (C) 1999 ARM Limited
   3  * Copyright (C) 2000 Deep Blue Solutions Ltd
   4  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   6  * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/err.h>
  27 #include <linux/delay.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/common.h>
  31 #include <asm/proc-fns.h>
  32 #include <asm/system.h>
  33
  34 static void __iomem *wdog_base;
  35
  36 /*
  37  * Reset the system. It is called by machine_restart().
  38  */
  39 void arch_reset(char mode, const char *cmd)
  40 {
  41         unsigned int wcr_enable;
  42
  43 #ifdef CONFIG_ARCH_MXC91231
  44         if (cpu_is_mxc91231()) {
  45                 mxc91231_arch_reset(mode, cmd);
  46                 return;
  47         }
  48 #endif
  49         if (cpu_is_mx1()) {
  50                 wcr_enable = (1 << 0);
  51         } else {
  52                 struct clk *clk;
  53
  54                 clk = clk_get_sys("imx-wdt.0", NULL);
  55                 if (!IS_ERR(clk))
  56                         clk_enable(clk);
  57                 wcr_enable = (1 << 2);
  58         }
  59
  60         /* Assert SRS signal */
  61         __raw_writew(wcr_enable, wdog_base);
  62
  63         /* wait for reset to assert... */
  64         mdelay(500);
  65
  66         printk(KERN_ERR "Watchdog reset failed to assert reset\n");
  67
  68         /* delay to allow the serial port to show the message */
  69         mdelay(50);
  70
  71         /* we'll take a jump through zero as a poor second */
  72         cpu_reset(0);
  73 }
  74
  75 void mxc_arch_reset_init(void __iomem *base)
  76 {
  77         wdog_base = base;
  78 }