| blob | 414ef8b7e5753b7f5b31a2c26ec7f7e54dbc8cb5 |
1 /*
2 * Device Tree Source for AMCC Arches (dual 460GT board)
3 *
4 * (C) Copyright 2008 Applied Micro Circuits Corporation
5 * Victor Gallardo <vgallardo@amcc.com>
6 * Adam Graham <agraham@amcc.com>
7 *
8 * Based on the glacier.dts file
9 * Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
31 /dts-v1/;
33 / {
34 #address-cells = <2>;
35 #size-cells = <1>;
36 model = "amcc,arches";
37 compatible = "amcc,arches";
38 dcr-parent = <&{/cpus/cpu@0}>;
40 aliases {
41 ethernet0 = &EMAC0;
42 ethernet1 = &EMAC1;
43 ethernet2 = &EMAC2;
44 serial0 = &UART0;
45 };
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
51 cpu@0 {
52 device_type = "cpu";
53 model = "PowerPC,460GT";
54 reg = <0x00000000>;
55 clock-frequency = <0>; /* Filled in by U-Boot */
56 timebase-frequency = <0>; /* Filled in by U-Boot */
57 i-cache-line-size = <32>;
58 d-cache-line-size = <32>;
59 i-cache-size = <32768>;
60 d-cache-size = <32768>;
61 dcr-controller;
62 dcr-access-method = "native";
63 };
64 };
66 memory {
67 device_type = "memory";
68 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
69 };
71 UIC0: interrupt-controller0 {
72 compatible = "ibm,uic-460gt","ibm,uic";
73 interrupt-controller;
74 cell-index = <0>;
75 dcr-reg = <0x0c0 0x009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 };
81 UIC1: interrupt-controller1 {
82 compatible = "ibm,uic-460gt","ibm,uic";
83 interrupt-controller;
84 cell-index = <1>;
85 dcr-reg = <0x0d0 0x009>;
86 #address-cells = <0>;
87 #size-cells = <0>;
88 #interrupt-cells = <2>;
89 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
90 interrupt-parent = <&UIC0>;
91 };
93 UIC2: interrupt-controller2 {
94 compatible = "ibm,uic-460gt","ibm,uic";
95 interrupt-controller;
96 cell-index = <2>;
97 dcr-reg = <0x0e0 0x009>;
98 #address-cells = <0>;
99 #size-cells = <0>;
100 #interrupt-cells = <2>;
101 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
102 interrupt-parent = <&UIC0>;
103 };
105 UIC3: interrupt-controller3 {
106 compatible = "ibm,uic-460gt","ibm,uic";
107 interrupt-controller;
108 cell-index = <3>;
109 dcr-reg = <0x0f0 0x009>;
110 #address-cells = <0>;
111 #size-cells = <0>;
112 #interrupt-cells = <2>;
113 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
114 interrupt-parent = <&UIC0>;
115 };
117 SDR0: sdr {
118 compatible = "ibm,sdr-460gt";
119 dcr-reg = <0x00e 0x002>;
120 };
122 CPR0: cpr {
123 compatible = "ibm,cpr-460gt";
124 dcr-reg = <0x00c 0x002>;
125 };
127 L2C0: l2c {
128 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
129 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
130 0x030 0x008>; /* L2 cache DCR's */
131 cache-line-size = <32>; /* 32 bytes */
132 cache-size = <262144>; /* L2, 256K */
133 interrupt-parent = <&UIC1>;
134 interrupts = <11 1>;
135 };
137 plb {
138 compatible = "ibm,plb-460gt", "ibm,plb4";
139 #address-cells = <2>;
140 #size-cells = <1>;
141 ranges;
142 clock-frequency = <0>; /* Filled in by U-Boot */
144 SDRAM0: sdram {
145 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
146 dcr-reg = <0x010 0x002>;
147 };
149 MAL0: mcmal {
150 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
151 dcr-reg = <0x180 0x062>;
152 num-tx-chans = <3>;
153 num-rx-chans = <24>;
154 #address-cells = <0>;
155 #size-cells = <0>;
156 interrupt-parent = <&UIC2>;
157 interrupts = < /*TXEOB*/ 0x6 0x4
158 /*RXEOB*/ 0x7 0x4
159 /*SERR*/ 0x3 0x4
160 /*TXDE*/ 0x4 0x4
161 /*RXDE*/ 0x5 0x4>;
162 desc-base-addr-high = <0x8>;
163 };
165 POB0: opb {
166 compatible = "ibm,opb-460gt", "ibm,opb";
167 #address-cells = <1>;
168 #size-cells = <1>;
169 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
170 clock-frequency = <0>; /* Filled in by U-Boot */
172 EBC0: ebc {
173 compatible = "ibm,ebc-460gt", "ibm,ebc";
174 dcr-reg = <0x012 0x002>;
175 #address-cells = <2>;
176 #size-cells = <1>;
177 clock-frequency = <0>; /* Filled in by U-Boot */
178 /* ranges property is supplied by U-Boot */
179 interrupts = <0x6 0x4>;
180 interrupt-parent = <&UIC1>;
182 nor_flash@0,0 {
183 compatible = "amd,s29gl256n", "cfi-flash";
184 bank-width = <2>;
185 reg = <0x00000000 0x00000000 0x02000000>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 partition@0 {
189 label = "kernel";
190 reg = <0x00000000 0x001e0000>;
191 };
192 partition@1e0000 {
193 label = "dtb";
194 reg = <0x001e0000 0x00020000>;
195 };
196 partition@200000 {
197 label = "root";
198 reg = <0x00200000 0x00200000>;
199 };
200 partition@400000 {
201 label = "user";
202 reg = <0x00400000 0x01b60000>;
203 };
204 partition@1f60000 {
205 label = "env";
206 reg = <0x01f60000 0x00040000>;
207 };
208 partition@1fa0000 {
209 label = "u-boot";
210 reg = <0x01fa0000 0x00060000>;
211 };
212 };
213 };
215 UART0: serial@ef600300 {
216 device_type = "serial";
217 compatible = "ns16550";
218 reg = <0xef600300 0x00000008>;
219 virtual-reg = <0xef600300>;
220 clock-frequency = <0>; /* Filled in by U-Boot */
221 current-speed = <0>; /* Filled in by U-Boot */
222 interrupt-parent = <&UIC1>;
223 interrupts = <0x1 0x4>;
224 };
226 IIC0: i2c@ef600700 {
227 compatible = "ibm,iic-460gt", "ibm,iic";
228 reg = <0xef600700 0x00000014>;
229 interrupt-parent = <&UIC0>;
230 interrupts = <0x2 0x4>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 sttm@4a {
234 compatible = "ad,ad7414";
235 reg = <0x4a>;
236 interrupt-parent = <&UIC1>;
237 interrupts = <0x0 0x8>;
238 };
239 };
241 IIC1: i2c@ef600800 {
242 compatible = "ibm,iic-460gt", "ibm,iic";
243 reg = <0xef600800 0x00000014>;
244 interrupt-parent = <&UIC0>;
245 interrupts = <0x3 0x4>;
246 };
248 TAH0: emac-tah@ef601350 {
249 compatible = "ibm,tah-460gt", "ibm,tah";
250 reg = <0xef601350 0x00000030>;
251 };
253 TAH1: emac-tah@ef601450 {
254 compatible = "ibm,tah-460gt", "ibm,tah";
255 reg = <0xef601450 0x00000030>;
256 };
258 EMAC0: ethernet@ef600e00 {
259 device_type = "network";
260 compatible = "ibm,emac-460gt", "ibm,emac4sync";
261 interrupt-parent = <&EMAC0>;
262 interrupts = <0x0 0x1>;
263 #interrupt-cells = <1>;
264 #address-cells = <0>;
265 #size-cells = <0>;
266 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
267 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
268 reg = <0xef600e00 0x000000c4>;
269 local-mac-address = [000000000000]; /* Filled in by U-Boot */
270 mal-device = <&MAL0>;
271 mal-tx-channel = <0>;
272 mal-rx-channel = <0>;
273 cell-index = <0>;
274 max-frame-size = <9000>;
275 rx-fifo-size = <4096>;
276 tx-fifo-size = <2048>;
277 phy-mode = "sgmii";
278 phy-map = <0xffffffff>;
279 gpcs-address = <0x0000000a>;
280 tah-device = <&TAH0>;
281 tah-channel = <0>;
282 has-inverted-stacr-oc;
283 has-new-stacr-staopc;
284 };
286 EMAC1: ethernet@ef600f00 {
287 device_type = "network";
288 compatible = "ibm,emac-460gt", "ibm,emac4sync";
289 interrupt-parent = <&EMAC1>;
290 interrupts = <0x0 0x1>;
291 #interrupt-cells = <1>;
292 #address-cells = <0>;
293 #size-cells = <0>;
294 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
295 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
296 reg = <0xef600f00 0x000000c4>;
297 local-mac-address = [000000000000]; /* Filled in by U-Boot */
298 mal-device = <&MAL0>;
299 mal-tx-channel = <1>;
300 mal-rx-channel = <8>;
301 cell-index = <1>;
302 max-frame-size = <9000>;
303 rx-fifo-size = <4096>;
304 tx-fifo-size = <2048>;
305 phy-mode = "sgmii";
306 phy-map = <0x00000000>;
307 gpcs-address = <0x0000000b>;
308 tah-device = <&TAH1>;
309 tah-channel = <1>;
310 has-inverted-stacr-oc;
311 has-new-stacr-staopc;
312 mdio-device = <&EMAC0>;
313 };
315 EMAC2: ethernet@ef601100 {
316 device_type = "network";
317 compatible = "ibm,emac-460gt", "ibm,emac4sync";
318 interrupt-parent = <&EMAC2>;
319 interrupts = <0x0 0x1>;
320 #interrupt-cells = <1>;
321 #address-cells = <0>;
322 #size-cells = <0>;
323 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
324 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
325 reg = <0xef601100 0x000000c4>;
326 local-mac-address = [000000000000]; /* Filled in by U-Boot */
327 mal-device = <&MAL0>;
328 mal-tx-channel = <2>;
329 mal-rx-channel = <16>;
330 cell-index = <2>;
331 max-frame-size = <9000>;
332 rx-fifo-size = <4096>;
333 tx-fifo-size = <2048>;
334 phy-mode = "sgmii";
335 phy-map = <0x00000001>;
336 gpcs-address = <0x0000000C>;
337 has-inverted-stacr-oc;
338 has-new-stacr-staopc;
339 mdio-device = <&EMAC0>;
340 };
341 };
342 };
343 };