| blob | 910944edd886fdfa42994adedfbe4757668bd084 |
1 /*
2 * GE Fanuc PPC9A Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
17 /*
18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
19 */
21 /dts-v1/;
23 / {
24 model = "GEF_PPC9A";
25 compatible = "gef,ppc9a";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
87 /* flash@0,0 is a mirror of part of the memory in flash@1,0
88 flash@0,0 {
89 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
90 reg = <0x0 0x0 0x1000000>;
91 bank-width = <4>;
92 device-width = <2>;
93 #address-cells = <1>;
94 #size-cells = <1>;
95 partition@0 {
96 label = "firmware";
97 reg = <0x0 0x1000000>;
98 read-only;
99 };
100 };
101 */
103 flash@1,0 {
104 compatible = "gef,ppc9a-paged-flash", "cfi-flash";
105 reg = <0x1 0x0 0x8000000>;
106 bank-width = <4>;
107 device-width = <2>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 partition@0 {
111 label = "user";
112 reg = <0x0 0x7800000>;
113 };
114 partition@7800000 {
115 label = "firmware";
116 reg = <0x7800000 0x800000>;
117 read-only;
118 };
119 };
121 fpga@4,0 {
122 compatible = "gef,ppc9a-fpga-regs";
123 reg = <0x4 0x0 0x40>;
124 };
126 wdt@4,2000 {
127 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
128 "gef,fpga-wdt";
129 reg = <0x4 0x2000 0x8>;
130 interrupts = <0x1a 0x4>;
131 interrupt-parent = <&gef_pic>;
132 };
133 /* Second watchdog available, driver currently supports one.
134 wdt@4,2010 {
135 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
136 "gef,fpga-wdt";
137 reg = <0x4 0x2010 0x8>;
138 interrupts = <0x1b 0x4>;
139 interrupt-parent = <&gef_pic>;
140 };
141 */
142 gef_pic: pic@4,4000 {
143 #interrupt-cells = <1>;
144 interrupt-controller;
145 compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
146 reg = <0x4 0x4000 0x20>;
147 interrupts = <0x8
148 0x9>;
149 interrupt-parent = <&mpic>;
151 };
152 gef_gpio: gpio@7,14000 {
153 #gpio-cells = <2>;
154 compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
155 reg = <0x7 0x14000 0x24>;
156 gpio-controller;
157 };
158 };
160 soc@fef00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 #interrupt-cells = <2>;
164 device_type = "soc";
165 compatible = "fsl,mpc8641-soc", "simple-bus";
166 ranges = <0x0 0xfef00000 0x00100000>;
167 bus-frequency = <33333333>;
169 mcm-law@0 {
170 compatible = "fsl,mcm-law";
171 reg = <0x0 0x1000>;
172 fsl,num-laws = <10>;
173 };
175 mcm@1000 {
176 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
177 reg = <0x1000 0x1000>;
178 interrupts = <17 2>;
179 interrupt-parent = <&mpic>;
180 };
182 i2c1: i2c@3000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl-i2c";
186 reg = <0x3000 0x100>;
187 interrupts = <0x2b 0x2>;
188 interrupt-parent = <&mpic>;
189 dfsrr;
191 hwmon@48 {
192 compatible = "national,lm92";
193 reg = <0x48>;
194 };
196 hwmon@4c {
197 compatible = "adi,adt7461";
198 reg = <0x4c>;
199 };
201 rtc@51 {
202 compatible = "epson,rx8581";
203 reg = <0x00000051>;
204 };
206 eti@6b {
207 compatible = "dallas,ds1682";
208 reg = <0x6b>;
209 };
210 };
212 i2c2: i2c@3100 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl-i2c";
216 reg = <0x3100 0x100>;
217 interrupts = <0x2b 0x2>;
218 interrupt-parent = <&mpic>;
219 dfsrr;
220 };
222 dma@21300 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
226 reg = <0x21300 0x4>;
227 ranges = <0x0 0x21100 0x200>;
228 cell-index = <0>;
229 dma-channel@0 {
230 compatible = "fsl,mpc8641-dma-channel",
231 "fsl,eloplus-dma-channel";
232 reg = <0x0 0x80>;
233 cell-index = <0>;
234 interrupt-parent = <&mpic>;
235 interrupts = <20 2>;
236 };
237 dma-channel@80 {
238 compatible = "fsl,mpc8641-dma-channel",
239 "fsl,eloplus-dma-channel";
240 reg = <0x80 0x80>;
241 cell-index = <1>;
242 interrupt-parent = <&mpic>;
243 interrupts = <21 2>;
244 };
245 dma-channel@100 {
246 compatible = "fsl,mpc8641-dma-channel",
247 "fsl,eloplus-dma-channel";
248 reg = <0x100 0x80>;
249 cell-index = <2>;
250 interrupt-parent = <&mpic>;
251 interrupts = <22 2>;
252 };
253 dma-channel@180 {
254 compatible = "fsl,mpc8641-dma-channel",
255 "fsl,eloplus-dma-channel";
256 reg = <0x180 0x80>;
257 cell-index = <3>;
258 interrupt-parent = <&mpic>;
259 interrupts = <23 2>;
260 };
261 };
263 enet0: ethernet@24000 {
264 #address-cells = <1>;
265 #size-cells = <1>;
266 device_type = "network";
267 model = "eTSEC";
268 compatible = "gianfar";
269 reg = <0x24000 0x1000>;
270 ranges = <0x0 0x24000 0x1000>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
273 interrupt-parent = <&mpic>;
274 phy-handle = <&phy0>;
275 phy-connection-type = "gmii";
277 mdio@520 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "fsl,gianfar-mdio";
281 reg = <0x520 0x20>;
283 phy0: ethernet-phy@0 {
284 interrupt-parent = <&gef_pic>;
285 interrupts = <0x9 0x4>;
286 reg = <1>;
287 };
288 phy2: ethernet-phy@2 {
289 interrupt-parent = <&gef_pic>;
290 interrupts = <0x8 0x4>;
291 reg = <3>;
292 };
293 };
294 };
296 enet1: ethernet@26000 {
297 device_type = "network";
298 model = "eTSEC";
299 compatible = "gianfar";
300 reg = <0x26000 0x1000>;
301 local-mac-address = [ 00 00 00 00 00 00 ];
302 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
303 interrupt-parent = <&mpic>;
304 phy-handle = <&phy2>;
305 phy-connection-type = "gmii";
306 };
308 serial0: serial@4500 {
309 cell-index = <0>;
310 device_type = "serial";
311 compatible = "ns16550";
312 reg = <0x4500 0x100>;
313 clock-frequency = <0>;
314 interrupts = <0x2a 0x2>;
315 interrupt-parent = <&mpic>;
316 };
318 serial1: serial@4600 {
319 cell-index = <1>;
320 device_type = "serial";
321 compatible = "ns16550";
322 reg = <0x4600 0x100>;
323 clock-frequency = <0>;
324 interrupts = <0x1c 0x2>;
325 interrupt-parent = <&mpic>;
326 };
328 mpic: pic@40000 {
329 clock-frequency = <0>;
330 interrupt-controller;
331 #address-cells = <0>;
332 #interrupt-cells = <2>;
333 reg = <0x40000 0x40000>;
334 compatible = "chrp,open-pic";
335 device_type = "open-pic";
336 };
338 global-utilities@e0000 {
339 compatible = "fsl,mpc8641-guts";
340 reg = <0xe0000 0x1000>;
341 fsl,has-rstcr;
342 };
343 };
345 pci0: pcie@fef08000 {
346 compatible = "fsl,mpc8641-pcie";
347 device_type = "pci";
348 #interrupt-cells = <1>;
349 #size-cells = <2>;
350 #address-cells = <3>;
351 reg = <0xfef08000 0x1000>;
352 bus-range = <0x0 0xff>;
353 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
354 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
355 clock-frequency = <33333333>;
356 interrupt-parent = <&mpic>;
357 interrupts = <0x18 0x2>;
358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
359 interrupt-map = <
360 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
361 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
362 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
363 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
364 >;
366 pcie@0 {
367 reg = <0 0 0 0 0>;
368 #size-cells = <2>;
369 #address-cells = <3>;
370 device_type = "pci";
371 ranges = <0x02000000 0x0 0x80000000
372 0x02000000 0x0 0x80000000
373 0x0 0x40000000
375 0x01000000 0x0 0x00000000
376 0x01000000 0x0 0x00000000
377 0x0 0x00400000>;
378 };
379 };
380 };