| blob | 35a63183eeccbac072b9b4c58801340bd3f7f755 |
1 /*
2 * GE Fanuc SBC610 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
17 /*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
19 */
21 /dts-v1/;
23 / {
24 model = "GEF_SBC610";
25 compatible = "gef,sbc610";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0
80 2 0 0xe0000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00008000 // FPGA
83 5 0 0xfc008000 0x00008000 // AFIX FPGA
84 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
85 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
87 fpga@4,0 {
88 compatible = "gef,fpga-regs";
89 reg = <0x4 0x0 0x40>;
90 };
92 wdt@4,2000 {
93 compatible = "gef,fpga-wdt";
94 reg = <0x4 0x2000 0x8>;
95 interrupts = <0x1a 0x4>;
96 interrupt-parent = <&gef_pic>;
97 };
98 /* Second watchdog available, driver currently supports one.
99 wdt@4,2010 {
100 compatible = "gef,fpga-wdt";
101 reg = <0x4 0x2010 0x8>;
102 interrupts = <0x1b 0x4>;
103 interrupt-parent = <&gef_pic>;
104 };
105 */
106 gef_pic: pic@4,4000 {
107 #interrupt-cells = <1>;
108 interrupt-controller;
109 compatible = "gef,fpga-pic";
110 reg = <0x4 0x4000 0x20>;
111 interrupts = <0x8
112 0x9>;
113 interrupt-parent = <&mpic>;
115 };
116 gef_gpio: gpio@7,14000 {
117 #gpio-cells = <2>;
118 compatible = "gef,sbc610-gpio";
119 reg = <0x7 0x14000 0x24>;
120 gpio-controller;
121 };
122 };
124 soc@fef00000 {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 #interrupt-cells = <2>;
128 device_type = "soc";
129 compatible = "simple-bus";
130 ranges = <0x0 0xfef00000 0x00100000>;
131 bus-frequency = <33333333>;
133 mcm-law@0 {
134 compatible = "fsl,mcm-law";
135 reg = <0x0 0x1000>;
136 fsl,num-laws = <10>;
137 };
139 mcm@1000 {
140 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
141 reg = <0x1000 0x1000>;
142 interrupts = <17 2>;
143 interrupt-parent = <&mpic>;
144 };
146 i2c1: i2c@3000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl-i2c";
150 reg = <0x3000 0x100>;
151 interrupts = <0x2b 0x2>;
152 interrupt-parent = <&mpic>;
153 dfsrr;
155 hwmon@48 {
156 compatible = "national,lm92";
157 reg = <0x48>;
158 };
160 hwmon@4c {
161 compatible = "adi,adt7461";
162 reg = <0x4c>;
163 };
165 rtc@51 {
166 compatible = "epson,rx8581";
167 reg = <0x00000051>;
168 };
170 eti@6b {
171 compatible = "dallas,ds1682";
172 reg = <0x6b>;
173 };
174 };
176 i2c2: i2c@3100 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl-i2c";
180 reg = <0x3100 0x100>;
181 interrupts = <0x2b 0x2>;
182 interrupt-parent = <&mpic>;
183 dfsrr;
184 };
186 dma@21300 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
190 reg = <0x21300 0x4>;
191 ranges = <0x0 0x21100 0x200>;
192 cell-index = <0>;
193 dma-channel@0 {
194 compatible = "fsl,mpc8641-dma-channel",
195 "fsl,eloplus-dma-channel";
196 reg = <0x0 0x80>;
197 cell-index = <0>;
198 interrupt-parent = <&mpic>;
199 interrupts = <20 2>;
200 };
201 dma-channel@80 {
202 compatible = "fsl,mpc8641-dma-channel",
203 "fsl,eloplus-dma-channel";
204 reg = <0x80 0x80>;
205 cell-index = <1>;
206 interrupt-parent = <&mpic>;
207 interrupts = <21 2>;
208 };
209 dma-channel@100 {
210 compatible = "fsl,mpc8641-dma-channel",
211 "fsl,eloplus-dma-channel";
212 reg = <0x100 0x80>;
213 cell-index = <2>;
214 interrupt-parent = <&mpic>;
215 interrupts = <22 2>;
216 };
217 dma-channel@180 {
218 compatible = "fsl,mpc8641-dma-channel",
219 "fsl,eloplus-dma-channel";
220 reg = <0x180 0x80>;
221 cell-index = <3>;
222 interrupt-parent = <&mpic>;
223 interrupts = <23 2>;
224 };
225 };
227 enet0: ethernet@24000 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 device_type = "network";
231 model = "eTSEC";
232 compatible = "gianfar";
233 reg = <0x24000 0x1000>;
234 ranges = <0x0 0x24000 0x1000>;
235 local-mac-address = [ 00 00 00 00 00 00 ];
236 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
237 interrupt-parent = <&mpic>;
238 phy-handle = <&phy0>;
239 phy-connection-type = "gmii";
241 mdio@520 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,gianfar-mdio";
245 reg = <0x520 0x20>;
247 phy0: ethernet-phy@0 {
248 interrupt-parent = <&gef_pic>;
249 interrupts = <0x9 0x4>;
250 reg = <1>;
251 };
252 phy2: ethernet-phy@2 {
253 interrupt-parent = <&gef_pic>;
254 interrupts = <0x8 0x4>;
255 reg = <3>;
256 };
257 };
258 };
260 enet1: ethernet@26000 {
261 device_type = "network";
262 model = "eTSEC";
263 compatible = "gianfar";
264 reg = <0x26000 0x1000>;
265 local-mac-address = [ 00 00 00 00 00 00 ];
266 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
267 interrupt-parent = <&mpic>;
268 phy-handle = <&phy2>;
269 phy-connection-type = "gmii";
270 };
272 serial0: serial@4500 {
273 cell-index = <0>;
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0x4500 0x100>;
277 clock-frequency = <0>;
278 interrupts = <0x2a 0x2>;
279 interrupt-parent = <&mpic>;
280 };
282 serial1: serial@4600 {
283 cell-index = <1>;
284 device_type = "serial";
285 compatible = "ns16550";
286 reg = <0x4600 0x100>;
287 clock-frequency = <0>;
288 interrupts = <0x1c 0x2>;
289 interrupt-parent = <&mpic>;
290 };
292 mpic: pic@40000 {
293 clock-frequency = <0>;
294 interrupt-controller;
295 #address-cells = <0>;
296 #interrupt-cells = <2>;
297 reg = <0x40000 0x40000>;
298 compatible = "chrp,open-pic";
299 device_type = "open-pic";
300 };
302 global-utilities@e0000 {
303 compatible = "fsl,mpc8641-guts";
304 reg = <0xe0000 0x1000>;
305 fsl,has-rstcr;
306 };
307 };
309 pci0: pcie@fef08000 {
310 compatible = "fsl,mpc8641-pcie";
311 device_type = "pci";
312 #interrupt-cells = <1>;
313 #size-cells = <2>;
314 #address-cells = <3>;
315 reg = <0xfef08000 0x1000>;
316 bus-range = <0x0 0xff>;
317 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
318 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
319 clock-frequency = <33333333>;
320 interrupt-parent = <&mpic>;
321 interrupts = <0x18 0x2>;
322 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
323 interrupt-map = <
324 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
325 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
326 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
327 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
328 >;
330 pcie@0 {
331 reg = <0 0 0 0 0>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 device_type = "pci";
335 ranges = <0x02000000 0x0 0x80000000
336 0x02000000 0x0 0x80000000
337 0x0 0x40000000
339 0x01000000 0x0 0x00000000
340 0x01000000 0x0 0x00000000
341 0x0 0x00400000>;
342 };
343 };
344 };