| blob | 230febb9b72f81a01ed6bfe9b55f7b88dae25ba2 |
1 /*
2 * MPC8349E MDS Device Tree Source
3 *
4 * Copyright 2005, 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8349EMDS";
16 compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 PowerPC,8349@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>; // from bootloader
41 bus-frequency = <0>; // from bootloader
42 clock-frequency = <0>; // from bootloader
43 };
44 };
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
49 };
51 bcsr@e2400000 {
52 compatible = "fsl,mpc8349mds-bcsr";
53 reg = <0xe2400000 0x8000>;
54 };
56 soc8349@e0000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 device_type = "soc";
60 compatible = "simple-bus";
61 ranges = <0x0 0xe0000000 0x00100000>;
62 reg = <0xe0000000 0x00000200>;
63 bus-frequency = <0>;
65 wdt@200 {
66 device_type = "watchdog";
67 compatible = "mpc83xx_wdt";
68 reg = <0x200 0x100>;
69 };
71 i2c@3000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 cell-index = <0>;
75 compatible = "fsl-i2c";
76 reg = <0x3000 0x100>;
77 interrupts = <14 0x8>;
78 interrupt-parent = <&ipic>;
79 dfsrr;
81 rtc@68 {
82 compatible = "dallas,ds1374";
83 reg = <0x68>;
84 };
85 };
87 i2c@3100 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <1>;
91 compatible = "fsl-i2c";
92 reg = <0x3100 0x100>;
93 interrupts = <15 0x8>;
94 interrupt-parent = <&ipic>;
95 dfsrr;
96 };
98 spi@7000 {
99 cell-index = <0>;
100 compatible = "fsl,spi";
101 reg = <0x7000 0x1000>;
102 interrupts = <16 0x8>;
103 interrupt-parent = <&ipic>;
104 mode = "cpu";
105 };
107 dma@82a8 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
111 reg = <0x82a8 4>;
112 ranges = <0 0x8100 0x1a8>;
113 interrupt-parent = <&ipic>;
114 interrupts = <71 8>;
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
118 reg = <0 0x80>;
119 cell-index = <0>;
120 interrupt-parent = <&ipic>;
121 interrupts = <71 8>;
122 };
123 dma-channel@80 {
124 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
125 reg = <0x80 0x80>;
126 cell-index = <1>;
127 interrupt-parent = <&ipic>;
128 interrupts = <71 8>;
129 };
130 dma-channel@100 {
131 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
132 reg = <0x100 0x80>;
133 cell-index = <2>;
134 interrupt-parent = <&ipic>;
135 interrupts = <71 8>;
136 };
137 dma-channel@180 {
138 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
139 reg = <0x180 0x28>;
140 cell-index = <3>;
141 interrupt-parent = <&ipic>;
142 interrupts = <71 8>;
143 };
144 };
146 /* phy type (ULPI or SERIAL) are only types supported for MPH */
147 /* port = 0 or 1 */
148 usb@22000 {
149 compatible = "fsl-usb2-mph";
150 reg = <0x22000 0x1000>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 interrupt-parent = <&ipic>;
154 interrupts = <39 0x8>;
155 phy_type = "ulpi";
156 port0;
157 };
158 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
159 usb@23000 {
160 compatible = "fsl-usb2-dr";
161 reg = <0x23000 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164 interrupt-parent = <&ipic>;
165 interrupts = <38 0x8>;
166 dr_mode = "otg";
167 phy_type = "ulpi";
168 };
170 enet0: ethernet@24000 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 cell-index = <0>;
174 device_type = "network";
175 model = "TSEC";
176 compatible = "gianfar";
177 reg = <0x24000 0x1000>;
178 ranges = <0x0 0x24000 0x1000>;
179 local-mac-address = [ 00 00 00 00 00 00 ];
180 interrupts = <32 0x8 33 0x8 34 0x8>;
181 interrupt-parent = <&ipic>;
182 tbi-handle = <&tbi0>;
183 phy-handle = <&phy0>;
184 linux,network-index = <0>;
186 mdio@520 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl,gianfar-mdio";
190 reg = <0x520 0x20>;
192 phy0: ethernet-phy@0 {
193 interrupt-parent = <&ipic>;
194 interrupts = <17 0x8>;
195 reg = <0x0>;
196 device_type = "ethernet-phy";
197 };
199 phy1: ethernet-phy@1 {
200 interrupt-parent = <&ipic>;
201 interrupts = <18 0x8>;
202 reg = <0x1>;
203 device_type = "ethernet-phy";
204 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
213 enet1: ethernet@25000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "TSEC";
219 compatible = "gianfar";
220 reg = <0x25000 0x1000>;
221 ranges = <0x0 0x25000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <35 0x8 36 0x8 37 0x8>;
224 interrupt-parent = <&ipic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy1>;
227 linux,network-index = <1>;
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
242 serial0: serial@4500 {
243 cell-index = <0>;
244 device_type = "serial";
245 compatible = "ns16550";
246 reg = <0x4500 0x100>;
247 clock-frequency = <0>;
248 interrupts = <9 0x8>;
249 interrupt-parent = <&ipic>;
250 };
252 serial1: serial@4600 {
253 cell-index = <1>;
254 device_type = "serial";
255 compatible = "ns16550";
256 reg = <0x4600 0x100>;
257 clock-frequency = <0>;
258 interrupts = <10 0x8>;
259 interrupt-parent = <&ipic>;
260 };
262 crypto@30000 {
263 compatible = "fsl,sec2.0";
264 reg = <0x30000 0x10000>;
265 interrupts = <11 0x8>;
266 interrupt-parent = <&ipic>;
267 fsl,num-channels = <4>;
268 fsl,channel-fifo-len = <24>;
269 fsl,exec-units-mask = <0x7e>;
270 fsl,descriptor-types-mask = <0x01010ebf>;
271 };
273 /* IPIC
274 * interrupts cell = <intr #, sense>
275 * sense values match linux IORESOURCE_IRQ_* defines:
276 * sense == 8: Level, low assertion
277 * sense == 2: Edge, high-to-low change
278 */
279 ipic: pic@700 {
280 interrupt-controller;
281 #address-cells = <0>;
282 #interrupt-cells = <2>;
283 reg = <0x700 0x100>;
284 device_type = "ipic";
285 };
286 };
288 pci0: pci@e0008500 {
289 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
290 interrupt-map = <
292 /* IDSEL 0x11 */
293 0x8800 0x0 0x0 0x1 &ipic 20 0x8
294 0x8800 0x0 0x0 0x2 &ipic 21 0x8
295 0x8800 0x0 0x0 0x3 &ipic 22 0x8
296 0x8800 0x0 0x0 0x4 &ipic 23 0x8
298 /* IDSEL 0x12 */
299 0x9000 0x0 0x0 0x1 &ipic 22 0x8
300 0x9000 0x0 0x0 0x2 &ipic 23 0x8
301 0x9000 0x0 0x0 0x3 &ipic 20 0x8
302 0x9000 0x0 0x0 0x4 &ipic 21 0x8
304 /* IDSEL 0x13 */
305 0x9800 0x0 0x0 0x1 &ipic 23 0x8
306 0x9800 0x0 0x0 0x2 &ipic 20 0x8
307 0x9800 0x0 0x0 0x3 &ipic 21 0x8
308 0x9800 0x0 0x0 0x4 &ipic 22 0x8
310 /* IDSEL 0x15 */
311 0xa800 0x0 0x0 0x1 &ipic 20 0x8
312 0xa800 0x0 0x0 0x2 &ipic 21 0x8
313 0xa800 0x0 0x0 0x3 &ipic 22 0x8
314 0xa800 0x0 0x0 0x4 &ipic 23 0x8
316 /* IDSEL 0x16 */
317 0xb000 0x0 0x0 0x1 &ipic 23 0x8
318 0xb000 0x0 0x0 0x2 &ipic 20 0x8
319 0xb000 0x0 0x0 0x3 &ipic 21 0x8
320 0xb000 0x0 0x0 0x4 &ipic 22 0x8
322 /* IDSEL 0x17 */
323 0xb800 0x0 0x0 0x1 &ipic 22 0x8
324 0xb800 0x0 0x0 0x2 &ipic 23 0x8
325 0xb800 0x0 0x0 0x3 &ipic 20 0x8
326 0xb800 0x0 0x0 0x4 &ipic 21 0x8
328 /* IDSEL 0x18 */
329 0xc000 0x0 0x0 0x1 &ipic 21 0x8
330 0xc000 0x0 0x0 0x2 &ipic 22 0x8
331 0xc000 0x0 0x0 0x3 &ipic 23 0x8
332 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
333 interrupt-parent = <&ipic>;
334 interrupts = <66 0x8>;
335 bus-range = <0 0>;
336 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
337 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
338 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
339 clock-frequency = <66666666>;
340 #interrupt-cells = <1>;
341 #size-cells = <2>;
342 #address-cells = <3>;
343 reg = <0xe0008500 0x100 /* internal registers */
344 0xe0008300 0x8>; /* config space access registers */
345 compatible = "fsl,mpc8349-pci";
346 device_type = "pci";
347 };
349 pci1: pci@e0008600 {
350 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
351 interrupt-map = <
353 /* IDSEL 0x11 */
354 0x8800 0x0 0x0 0x1 &ipic 20 0x8
355 0x8800 0x0 0x0 0x2 &ipic 21 0x8
356 0x8800 0x0 0x0 0x3 &ipic 22 0x8
357 0x8800 0x0 0x0 0x4 &ipic 23 0x8
359 /* IDSEL 0x12 */
360 0x9000 0x0 0x0 0x1 &ipic 22 0x8
361 0x9000 0x0 0x0 0x2 &ipic 23 0x8
362 0x9000 0x0 0x0 0x3 &ipic 20 0x8
363 0x9000 0x0 0x0 0x4 &ipic 21 0x8
365 /* IDSEL 0x13 */
366 0x9800 0x0 0x0 0x1 &ipic 23 0x8
367 0x9800 0x0 0x0 0x2 &ipic 20 0x8
368 0x9800 0x0 0x0 0x3 &ipic 21 0x8
369 0x9800 0x0 0x0 0x4 &ipic 22 0x8
371 /* IDSEL 0x15 */
372 0xa800 0x0 0x0 0x1 &ipic 20 0x8
373 0xa800 0x0 0x0 0x2 &ipic 21 0x8
374 0xa800 0x0 0x0 0x3 &ipic 22 0x8
375 0xa800 0x0 0x0 0x4 &ipic 23 0x8
377 /* IDSEL 0x16 */
378 0xb000 0x0 0x0 0x1 &ipic 23 0x8
379 0xb000 0x0 0x0 0x2 &ipic 20 0x8
380 0xb000 0x0 0x0 0x3 &ipic 21 0x8
381 0xb000 0x0 0x0 0x4 &ipic 22 0x8
383 /* IDSEL 0x17 */
384 0xb800 0x0 0x0 0x1 &ipic 22 0x8
385 0xb800 0x0 0x0 0x2 &ipic 23 0x8
386 0xb800 0x0 0x0 0x3 &ipic 20 0x8
387 0xb800 0x0 0x0 0x4 &ipic 21 0x8
389 /* IDSEL 0x18 */
390 0xc000 0x0 0x0 0x1 &ipic 21 0x8
391 0xc000 0x0 0x0 0x2 &ipic 22 0x8
392 0xc000 0x0 0x0 0x3 &ipic 23 0x8
393 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
394 interrupt-parent = <&ipic>;
395 interrupts = <67 0x8>;
396 bus-range = <0 0>;
397 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
398 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
399 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
400 clock-frequency = <66666666>;
401 #interrupt-cells = <1>;
402 #size-cells = <2>;
403 #address-cells = <3>;
404 reg = <0xe0008600 0x100 /* internal registers */
405 0xe0008380 0x8>; /* config space access registers */
406 compatible = "fsl,mpc8349-pci";
407 device_type = "pci";
408 };
409 };