| blob | 855782c5e5ecc4043329f6edfa50ccc6fea078c3 |
1 /*
2 * MPC8377E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "fsl,mpc8377emds";
16 compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
34 PowerPC,8377@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 };
45 };
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
50 };
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
60 // booting from NOR flash
61 ranges = <0 0x0 0xfe000000 0x02000000
62 1 0x0 0xf8000000 0x00008000
63 3 0x0 0xe0600000 0x00008000>;
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0 0x0 0x2000000>;
70 bank-width = <2>;
71 device-width = <1>;
73 u-boot@0 {
74 reg = <0x0 0x100000>;
75 read-only;
76 };
78 fs@100000 {
79 reg = <0x100000 0x800000>;
80 };
82 kernel@1d00000 {
83 reg = <0x1d00000 0x200000>;
84 };
86 dtb@1f00000 {
87 reg = <0x1f00000 0x100000>;
88 };
89 };
91 bcsr@1,0 {
92 reg = <1 0x0 0x8000>;
93 compatible = "fsl,mpc837xmds-bcsr";
94 };
96 nand@3,0 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8377-fcm-nand",
100 "fsl,elbc-fcm-nand";
101 reg = <3 0x0 0x8000>;
103 u-boot@0 {
104 reg = <0x0 0x100000>;
105 read-only;
106 };
108 kernel@100000 {
109 reg = <0x100000 0x300000>;
110 };
112 fs@400000 {
113 reg = <0x400000 0x1c00000>;
114 };
115 };
116 };
118 soc@e0000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 device_type = "soc";
122 compatible = "simple-bus";
123 ranges = <0x0 0xe0000000 0x00100000>;
124 reg = <0xe0000000 0x00000200>;
125 bus-frequency = <0>;
127 wdt@200 {
128 compatible = "mpc83xx_wdt";
129 reg = <0x200 0x100>;
130 };
132 sleep-nexus {
133 #address-cells = <1>;
134 #size-cells = <1>;
135 compatible = "simple-bus";
136 sleep = <&pmc 0x0c000000>;
137 ranges;
139 i2c@3000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 cell-index = <0>;
143 compatible = "fsl-i2c";
144 reg = <0x3000 0x100>;
145 interrupts = <14 0x8>;
146 interrupt-parent = <&ipic>;
147 dfsrr;
149 rtc@68 {
150 compatible = "dallas,ds1374";
151 reg = <0x68>;
152 interrupts = <19 0x8>;
153 interrupt-parent = <&ipic>;
154 };
155 };
157 sdhci@2e000 {
158 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
159 reg = <0x2e000 0x1000>;
160 interrupts = <42 0x8>;
161 interrupt-parent = <&ipic>;
162 sdhci,wp-inverted;
163 /* Filled in by U-Boot */
164 clock-frequency = <0>;
165 };
166 };
168 i2c@3100 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 cell-index = <1>;
172 compatible = "fsl-i2c";
173 reg = <0x3100 0x100>;
174 interrupts = <15 0x8>;
175 interrupt-parent = <&ipic>;
176 dfsrr;
177 };
179 spi@7000 {
180 cell-index = <0>;
181 compatible = "fsl,spi";
182 reg = <0x7000 0x1000>;
183 interrupts = <16 0x8>;
184 interrupt-parent = <&ipic>;
185 mode = "cpu";
186 };
188 usb@23000 {
189 compatible = "fsl-usb2-dr";
190 reg = <0x23000 0x1000>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 interrupt-parent = <&ipic>;
194 interrupts = <38 0x8>;
195 dr_mode = "host";
196 phy_type = "ulpi";
197 sleep = <&pmc 0x00c00000>;
198 };
200 enet0: ethernet@24000 {
201 #address-cells = <1>;
202 #size-cells = <1>;
203 cell-index = <0>;
204 device_type = "network";
205 model = "eTSEC";
206 compatible = "gianfar";
207 reg = <0x24000 0x1000>;
208 ranges = <0x0 0x24000 0x1000>;
209 local-mac-address = [ 00 00 00 00 00 00 ];
210 interrupts = <32 0x8 33 0x8 34 0x8>;
211 phy-connection-type = "mii";
212 interrupt-parent = <&ipic>;
213 tbi-handle = <&tbi0>;
214 phy-handle = <&phy2>;
215 sleep = <&pmc 0xc0000000>;
216 fsl,magic-packet;
218 mdio@520 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,gianfar-mdio";
222 reg = <0x520 0x20>;
224 phy2: ethernet-phy@2 {
225 interrupt-parent = <&ipic>;
226 interrupts = <17 0x8>;
227 reg = <0x2>;
228 device_type = "ethernet-phy";
229 };
231 phy3: ethernet-phy@3 {
232 interrupt-parent = <&ipic>;
233 interrupts = <18 0x8>;
234 reg = <0x3>;
235 device_type = "ethernet-phy";
236 };
238 tbi0: tbi-phy@11 {
239 reg = <0x11>;
240 device_type = "tbi-phy";
241 };
242 };
243 };
245 enet1: ethernet@25000 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 cell-index = <1>;
249 device_type = "network";
250 model = "eTSEC";
251 compatible = "gianfar";
252 reg = <0x25000 0x1000>;
253 ranges = <0x0 0x25000 0x1000>;
254 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <35 0x8 36 0x8 37 0x8>;
256 phy-connection-type = "mii";
257 interrupt-parent = <&ipic>;
258 tbi-handle = <&tbi1>;
259 phy-handle = <&phy3>;
260 sleep = <&pmc 0x30000000>;
261 fsl,magic-packet;
263 mdio@520 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,gianfar-tbi";
267 reg = <0x520 0x20>;
269 tbi1: tbi-phy@11 {
270 reg = <0x11>;
271 device_type = "tbi-phy";
272 };
273 };
274 };
276 serial0: serial@4500 {
277 cell-index = <0>;
278 device_type = "serial";
279 compatible = "ns16550";
280 reg = <0x4500 0x100>;
281 clock-frequency = <0>;
282 interrupts = <9 0x8>;
283 interrupt-parent = <&ipic>;
284 };
286 serial1: serial@4600 {
287 cell-index = <1>;
288 device_type = "serial";
289 compatible = "ns16550";
290 reg = <0x4600 0x100>;
291 clock-frequency = <0>;
292 interrupts = <10 0x8>;
293 interrupt-parent = <&ipic>;
294 };
296 dma@82a8 {
297 #address-cells = <1>;
298 #size-cells = <1>;
299 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
300 reg = <0x82a8 4>;
301 ranges = <0 0x8100 0x1a8>;
302 interrupt-parent = <&ipic>;
303 interrupts = <0x47 8>;
304 cell-index = <0>;
305 dma-channel@0 {
306 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
307 reg = <0 0x80>;
308 cell-index = <0>;
309 interrupt-parent = <&ipic>;
310 interrupts = <0x47 8>;
311 };
312 dma-channel@80 {
313 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
314 reg = <0x80 0x80>;
315 cell-index = <1>;
316 interrupt-parent = <&ipic>;
317 interrupts = <0x47 8>;
318 };
319 dma-channel@100 {
320 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
321 reg = <0x100 0x80>;
322 cell-index = <2>;
323 interrupt-parent = <&ipic>;
324 interrupts = <0x47 8>;
325 };
326 dma-channel@180 {
327 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
328 reg = <0x180 0x28>;
329 cell-index = <3>;
330 interrupt-parent = <&ipic>;
331 interrupts = <0x47 8>;
332 };
333 };
335 crypto@30000 {
336 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
337 "fsl,sec2.1", "fsl,sec2.0";
338 reg = <0x30000 0x10000>;
339 interrupts = <11 0x8>;
340 interrupt-parent = <&ipic>;
341 fsl,num-channels = <4>;
342 fsl,channel-fifo-len = <24>;
343 fsl,exec-units-mask = <0x9fe>;
344 fsl,descriptor-types-mask = <0x3ab0ebf>;
345 sleep = <&pmc 0x03000000>;
346 };
348 sata@18000 {
349 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
350 reg = <0x18000 0x1000>;
351 interrupts = <44 0x8>;
352 interrupt-parent = <&ipic>;
353 sleep = <&pmc 0x000000c0>;
354 };
356 sata@19000 {
357 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
358 reg = <0x19000 0x1000>;
359 interrupts = <45 0x8>;
360 interrupt-parent = <&ipic>;
361 sleep = <&pmc 0x00000030>;
362 };
364 /* IPIC
365 * interrupts cell = <intr #, sense>
366 * sense values match linux IORESOURCE_IRQ_* defines:
367 * sense == 8: Level, low assertion
368 * sense == 2: Edge, high-to-low change
369 */
370 ipic: pic@700 {
371 compatible = "fsl,ipic";
372 interrupt-controller;
373 #address-cells = <0>;
374 #interrupt-cells = <2>;
375 reg = <0x700 0x100>;
376 };
378 pmc: power@b00 {
379 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
380 reg = <0xb00 0x100 0xa00 0x100>;
381 interrupts = <80 0x8>;
382 interrupt-parent = <&ipic>;
383 };
384 };
386 pci0: pci@e0008500 {
387 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
388 interrupt-map = <
390 /* IDSEL 0x11 */
391 0x8800 0x0 0x0 0x1 &ipic 20 0x8
392 0x8800 0x0 0x0 0x2 &ipic 21 0x8
393 0x8800 0x0 0x0 0x3 &ipic 22 0x8
394 0x8800 0x0 0x0 0x4 &ipic 23 0x8
396 /* IDSEL 0x12 */
397 0x9000 0x0 0x0 0x1 &ipic 22 0x8
398 0x9000 0x0 0x0 0x2 &ipic 23 0x8
399 0x9000 0x0 0x0 0x3 &ipic 20 0x8
400 0x9000 0x0 0x0 0x4 &ipic 21 0x8
402 /* IDSEL 0x13 */
403 0x9800 0x0 0x0 0x1 &ipic 23 0x8
404 0x9800 0x0 0x0 0x2 &ipic 20 0x8
405 0x9800 0x0 0x0 0x3 &ipic 21 0x8
406 0x9800 0x0 0x0 0x4 &ipic 22 0x8
408 /* IDSEL 0x15 */
409 0xa800 0x0 0x0 0x1 &ipic 20 0x8
410 0xa800 0x0 0x0 0x2 &ipic 21 0x8
411 0xa800 0x0 0x0 0x3 &ipic 22 0x8
412 0xa800 0x0 0x0 0x4 &ipic 23 0x8
414 /* IDSEL 0x16 */
415 0xb000 0x0 0x0 0x1 &ipic 23 0x8
416 0xb000 0x0 0x0 0x2 &ipic 20 0x8
417 0xb000 0x0 0x0 0x3 &ipic 21 0x8
418 0xb000 0x0 0x0 0x4 &ipic 22 0x8
420 /* IDSEL 0x17 */
421 0xb800 0x0 0x0 0x1 &ipic 22 0x8
422 0xb800 0x0 0x0 0x2 &ipic 23 0x8
423 0xb800 0x0 0x0 0x3 &ipic 20 0x8
424 0xb800 0x0 0x0 0x4 &ipic 21 0x8
426 /* IDSEL 0x18 */
427 0xc000 0x0 0x0 0x1 &ipic 21 0x8
428 0xc000 0x0 0x0 0x2 &ipic 22 0x8
429 0xc000 0x0 0x0 0x3 &ipic 23 0x8
430 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
431 interrupt-parent = <&ipic>;
432 interrupts = <66 0x8>;
433 bus-range = <0x0 0x0>;
434 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
435 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
436 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
437 sleep = <&pmc 0x00010000>;
438 clock-frequency = <0>;
439 #interrupt-cells = <1>;
440 #size-cells = <2>;
441 #address-cells = <3>;
442 reg = <0xe0008500 0x100 /* internal registers */
443 0xe0008300 0x8>; /* config space access registers */
444 compatible = "fsl,mpc8349-pci";
445 device_type = "pci";
446 };
448 pci1: pcie@e0009000 {
449 #address-cells = <3>;
450 #size-cells = <2>;
451 #interrupt-cells = <1>;
452 device_type = "pci";
453 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
454 reg = <0xe0009000 0x00001000>;
455 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
456 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
457 bus-range = <0 255>;
458 interrupt-map-mask = <0xf800 0 0 7>;
459 interrupt-map = <0 0 0 1 &ipic 1 8
460 0 0 0 2 &ipic 1 8
461 0 0 0 3 &ipic 1 8
462 0 0 0 4 &ipic 1 8>;
463 sleep = <&pmc 0x00300000>;
464 clock-frequency = <0>;
466 pcie@0 {
467 #address-cells = <3>;
468 #size-cells = <2>;
469 device_type = "pci";
470 reg = <0 0 0 0 0>;
471 ranges = <0x02000000 0 0xa8000000
472 0x02000000 0 0xa8000000
473 0 0x10000000
474 0x01000000 0 0x00000000
475 0x01000000 0 0x00000000
476 0 0x00800000>;
477 };
478 };
480 pci2: pcie@e000a000 {
481 #address-cells = <3>;
482 #size-cells = <2>;
483 #interrupt-cells = <1>;
484 device_type = "pci";
485 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
486 reg = <0xe000a000 0x00001000>;
487 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
488 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
489 bus-range = <0 255>;
490 interrupt-map-mask = <0xf800 0 0 7>;
491 interrupt-map = <0 0 0 1 &ipic 2 8
492 0 0 0 2 &ipic 2 8
493 0 0 0 3 &ipic 2 8
494 0 0 0 4 &ipic 2 8>;
495 sleep = <&pmc 0x000c0000>;
496 clock-frequency = <0>;
498 pcie@0 {
499 #address-cells = <3>;
500 #size-cells = <2>;
501 device_type = "pci";
502 reg = <0 0 0 0 0>;
503 ranges = <0x02000000 0 0xc8000000
504 0x02000000 0 0xc8000000
505 0 0x10000000
506 0x01000000 0 0x00000000
507 0x01000000 0 0x00000000
508 0 0x00800000>;
509 };
510 };
511 };