| blob | d95b26021e625edcce2178df75ff5a1372a08908 |
1 /*
2 * MPC8536 DS Device Tree Source
3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
31 cpus {
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
36 PowerPC,8536@0 {
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
43 memory {
44 device_type = "memory";
45 reg = <0 0 0 0>; // Filled by U-Boot
46 };
48 soc@fffe00000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
115 reg = <0x21300 4>;
116 ranges = <0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8536-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8536-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8536-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8536-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
152 usb@22000 {
153 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
154 reg = <0x22000 0x1000>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupt-parent = <&mpic>;
158 interrupts = <28 0x2>;
159 phy_type = "ulpi";
160 };
162 usb@23000 {
163 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
164 reg = <0x23000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupt-parent = <&mpic>;
168 interrupts = <46 0x2>;
169 phy_type = "ulpi";
170 };
172 enet0: ethernet@24000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 cell-index = <0>;
176 device_type = "network";
177 model = "eTSEC";
178 compatible = "gianfar";
179 reg = <0x24000 0x1000>;
180 ranges = <0x0 0x24000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <29 2 30 2 34 2>;
183 interrupt-parent = <&mpic>;
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy1>;
186 phy-connection-type = "rgmii-id";
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-mdio";
192 reg = <0x520 0x20>;
194 phy0: ethernet-phy@0 {
195 interrupt-parent = <&mpic>;
196 interrupts = <10 0x1>;
197 reg = <0>;
198 device_type = "ethernet-phy";
199 };
200 phy1: ethernet-phy@1 {
201 interrupt-parent = <&mpic>;
202 interrupts = <10 0x1>;
203 reg = <1>;
204 device_type = "ethernet-phy";
205 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
213 enet1: ethernet@26000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "eTSEC";
219 compatible = "gianfar";
220 reg = <0x26000 0x1000>;
221 ranges = <0x0 0x26000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <31 2 32 2 33 2>;
224 interrupt-parent = <&mpic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
242 usb@2b000 {
243 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
244 reg = <0x2b000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupt-parent = <&mpic>;
248 interrupts = <60 0x2>;
249 dr_mode = "peripheral";
250 phy_type = "ulpi";
251 };
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
261 serial0: serial@4500 {
262 cell-index = <0>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4500 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 0x2>;
268 interrupt-parent = <&mpic>;
269 };
271 serial1: serial@4600 {
272 cell-index = <1>;
273 device_type = "serial";
274 compatible = "ns16550";
275 reg = <0x4600 0x100>;
276 clock-frequency = <0>;
277 interrupts = <42 0x2>;
278 interrupt-parent = <&mpic>;
279 };
281 crypto@30000 {
282 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
283 "fsl,sec2.1", "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <45 2 58 2>;
286 interrupt-parent = <&mpic>;
287 fsl,num-channels = <4>;
288 fsl,channel-fifo-len = <24>;
289 fsl,exec-units-mask = <0x9fe>;
290 fsl,descriptor-types-mask = <0x3ab0ebf>;
291 };
293 sata@18000 {
294 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
295 reg = <0x18000 0x1000>;
296 cell-index = <1>;
297 interrupts = <74 0x2>;
298 interrupt-parent = <&mpic>;
299 };
301 sata@19000 {
302 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
303 reg = <0x19000 0x1000>;
304 cell-index = <2>;
305 interrupts = <41 0x2>;
306 interrupt-parent = <&mpic>;
307 };
309 global-utilities@e0000 { //global utilities block
310 compatible = "fsl,mpc8548-guts";
311 reg = <0xe0000 0x1000>;
312 fsl,has-rstcr;
313 };
315 mpic: pic@40000 {
316 clock-frequency = <0>;
317 interrupt-controller;
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 reg = <0x40000 0x40000>;
321 compatible = "chrp,open-pic";
322 device_type = "open-pic";
323 big-endian;
324 };
326 msi@41600 {
327 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
328 reg = <0x41600 0x80>;
329 msi-available-ranges = <0 0x100>;
330 interrupts = <
331 0xe0 0
332 0xe1 0
333 0xe2 0
334 0xe3 0
335 0xe4 0
336 0xe5 0
337 0xe6 0
338 0xe7 0>;
339 interrupt-parent = <&mpic>;
340 };
341 };
343 pci0: pci@fffe08000 {
344 compatible = "fsl,mpc8540-pci";
345 device_type = "pci";
346 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-map = <
349 /* IDSEL 0x11 J17 Slot 1 */
350 0x8800 0 0 1 &mpic 1 1
351 0x8800 0 0 2 &mpic 2 1
352 0x8800 0 0 3 &mpic 3 1
353 0x8800 0 0 4 &mpic 4 1>;
355 interrupt-parent = <&mpic>;
356 interrupts = <24 0x2>;
357 bus-range = <0 0xff>;
358 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
359 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
360 clock-frequency = <66666666>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <0xf 0xffe08000 0 0x1000>;
365 };
367 pci1: pcie@fffe09000 {
368 compatible = "fsl,mpc8548-pcie";
369 device_type = "pci";
370 #interrupt-cells = <1>;
371 #size-cells = <2>;
372 #address-cells = <3>;
373 reg = <0xf 0xffe09000 0 0x1000>;
374 bus-range = <0 0xff>;
375 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
376 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
377 clock-frequency = <33333333>;
378 interrupt-parent = <&mpic>;
379 interrupts = <25 0x2>;
380 interrupt-map-mask = <0xf800 0 0 7>;
381 interrupt-map = <
382 /* IDSEL 0x0 */
383 0000 0 0 1 &mpic 4 1
384 0000 0 0 2 &mpic 5 1
385 0000 0 0 3 &mpic 6 1
386 0000 0 0 4 &mpic 7 1
387 >;
388 pcie@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 device_type = "pci";
393 ranges = <0x02000000 0 0xf8000000
394 0x02000000 0 0xf8000000
395 0 0x08000000
397 0x01000000 0 0x00000000
398 0x01000000 0 0x00000000
399 0 0x00010000>;
400 };
401 };
403 pci2: pcie@fffe0a000 {
404 compatible = "fsl,mpc8548-pcie";
405 device_type = "pci";
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 reg = <0xf 0xffe0a000 0 0x1000>;
410 bus-range = <0 0xff>;
411 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
412 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
413 clock-frequency = <33333333>;
414 interrupt-parent = <&mpic>;
415 interrupts = <26 0x2>;
416 interrupt-map-mask = <0xf800 0 0 7>;
417 interrupt-map = <
418 /* IDSEL 0x0 */
419 0000 0 0 1 &mpic 0 1
420 0000 0 0 2 &mpic 1 1
421 0000 0 0 3 &mpic 2 1
422 0000 0 0 4 &mpic 3 1
423 >;
424 pcie@0 {
425 reg = <0 0 0 0 0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x02000000 0 0xf8000000
430 0x02000000 0 0xf8000000
431 0 0x08000000
433 0x01000000 0 0x00000000
434 0x01000000 0 0x00000000
435 0 0x00010000>;
436 };
437 };
439 pci3: pcie@fffe0b000 {
440 compatible = "fsl,mpc8548-pcie";
441 device_type = "pci";
442 #interrupt-cells = <1>;
443 #size-cells = <2>;
444 #address-cells = <3>;
445 reg = <0xf 0xffe0b000 0 0x1000>;
446 bus-range = <0 0xff>;
447 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
448 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
449 clock-frequency = <33333333>;
450 interrupt-parent = <&mpic>;
451 interrupts = <27 0x2>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <
454 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 8 1
456 0000 0 0 2 &mpic 9 1
457 0000 0 0 3 &mpic 10 1
458 0000 0 0 4 &mpic 11 1
459 >;
461 pcie@0 {
462 reg = <0 0 0 0 0>;
463 #size-cells = <2>;
464 #address-cells = <3>;
465 device_type = "pci";
466 ranges = <0x02000000 0 0xe0000000
467 0x02000000 0 0xe0000000
468 0 0x20000000
470 0x01000000 0 0x00000000
471 0x01000000 0 0x00000000
472 0 0x00100000>;
473 };
474 };
475 };