| blob | 9dc292962a9a395a6b6f6daace2313f1258720c8 |
1 /*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8540ADS";
16 compatible = "MPC8540ADS", "MPC85xxADS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 PowerPC,8540@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
44 };
45 };
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
50 };
52 soc8540@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 device_type = "soc";
56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>;
58 bus-frequency = <0>;
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
66 ecm@1000 {
67 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller";
75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>;
78 };
80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller";
82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K
85 interrupt-parent = <&mpic>;
86 interrupts = <16 2>;
87 };
89 i2c@3000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <0>;
93 compatible = "fsl-i2c";
94 reg = <0x3000 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
100 dma@21300 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
104 reg = <0x21300 0x4>;
105 ranges = <0x0 0x21100 0x200>;
106 cell-index = <0>;
107 dma-channel@0 {
108 compatible = "fsl,mpc8540-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x0 0x80>;
111 cell-index = <0>;
112 interrupt-parent = <&mpic>;
113 interrupts = <20 2>;
114 };
115 dma-channel@80 {
116 compatible = "fsl,mpc8540-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x80 0x80>;
119 cell-index = <1>;
120 interrupt-parent = <&mpic>;
121 interrupts = <21 2>;
122 };
123 dma-channel@100 {
124 compatible = "fsl,mpc8540-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x100 0x80>;
127 cell-index = <2>;
128 interrupt-parent = <&mpic>;
129 interrupts = <22 2>;
130 };
131 dma-channel@180 {
132 compatible = "fsl,mpc8540-dma-channel",
133 "fsl,eloplus-dma-channel";
134 reg = <0x180 0x80>;
135 cell-index = <3>;
136 interrupt-parent = <&mpic>;
137 interrupts = <23 2>;
138 };
139 };
141 enet0: ethernet@24000 {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 cell-index = <0>;
145 device_type = "network";
146 model = "TSEC";
147 compatible = "gianfar";
148 reg = <0x24000 0x1000>;
149 ranges = <0x0 0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>;
153 tbi-handle = <&tbi0>;
154 phy-handle = <&phy0>;
156 mdio@520 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,gianfar-mdio";
160 reg = <0x520 0x20>;
162 phy0: ethernet-phy@0 {
163 interrupt-parent = <&mpic>;
164 interrupts = <5 1>;
165 reg = <0x0>;
166 device_type = "ethernet-phy";
167 };
168 phy1: ethernet-phy@1 {
169 interrupt-parent = <&mpic>;
170 interrupts = <5 1>;
171 reg = <0x1>;
172 device_type = "ethernet-phy";
173 };
174 phy3: ethernet-phy@3 {
175 interrupt-parent = <&mpic>;
176 interrupts = <7 1>;
177 reg = <0x3>;
178 device_type = "ethernet-phy";
179 };
180 tbi0: tbi-phy@11 {
181 reg = <0x11>;
182 device_type = "tbi-phy";
183 };
184 };
185 };
187 enet1: ethernet@25000 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 cell-index = <1>;
191 device_type = "network";
192 model = "TSEC";
193 compatible = "gianfar";
194 reg = <0x25000 0x1000>;
195 ranges = <0x0 0x25000 0x1000>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <35 2 36 2 40 2>;
198 interrupt-parent = <&mpic>;
199 tbi-handle = <&tbi1>;
200 phy-handle = <&phy1>;
202 mdio@520 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,gianfar-tbi";
206 reg = <0x520 0x20>;
208 tbi1: tbi-phy@11 {
209 reg = <0x11>;
210 device_type = "tbi-phy";
211 };
212 };
213 };
215 enet2: ethernet@26000 {
216 #address-cells = <1>;
217 #size-cells = <1>;
218 cell-index = <2>;
219 device_type = "network";
220 model = "FEC";
221 compatible = "gianfar";
222 reg = <0x26000 0x1000>;
223 ranges = <0x0 0x26000 0x1000>;
224 local-mac-address = [ 00 00 00 00 00 00 ];
225 interrupts = <41 2>;
226 interrupt-parent = <&mpic>;
227 tbi-handle = <&tbi2>;
228 phy-handle = <&phy3>;
230 mdio@520 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,gianfar-tbi";
234 reg = <0x520 0x20>;
236 tbi2: tbi-phy@11 {
237 reg = <0x11>;
238 device_type = "tbi-phy";
239 };
240 };
241 };
243 serial0: serial@4500 {
244 cell-index = <0>;
245 device_type = "serial";
246 compatible = "ns16550";
247 reg = <0x4500 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot?
249 interrupts = <42 2>;
250 interrupt-parent = <&mpic>;
251 };
253 serial1: serial@4600 {
254 cell-index = <1>;
255 device_type = "serial";
256 compatible = "ns16550";
257 reg = <0x4600 0x100>; // reg base, size
258 clock-frequency = <0>; // should we fill in in uboot?
259 interrupts = <42 2>;
260 interrupt-parent = <&mpic>;
261 };
262 mpic: pic@40000 {
263 interrupt-controller;
264 #address-cells = <0>;
265 #interrupt-cells = <2>;
266 reg = <0x40000 0x40000>;
267 compatible = "chrp,open-pic";
268 device_type = "open-pic";
269 };
270 };
272 pci0: pci@e0008000 {
273 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
274 interrupt-map = <
276 /* IDSEL 0x02 */
277 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
278 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
279 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
280 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
282 /* IDSEL 0x03 */
283 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
284 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
285 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
286 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
288 /* IDSEL 0x04 */
289 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
290 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
291 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
292 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
294 /* IDSEL 0x05 */
295 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
296 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
297 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
298 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
300 /* IDSEL 0x0c */
301 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
302 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
303 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
304 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
306 /* IDSEL 0x0d */
307 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
308 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
309 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
310 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
312 /* IDSEL 0x0e */
313 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
314 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
315 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
316 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
318 /* IDSEL 0x0f */
319 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
320 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
321 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
322 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
324 /* IDSEL 0x12 */
325 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
326 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
327 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
328 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
330 /* IDSEL 0x13 */
331 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
332 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
333 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
334 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
336 /* IDSEL 0x14 */
337 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
338 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
339 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
340 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
342 /* IDSEL 0x15 */
343 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
344 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
345 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
346 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
347 interrupt-parent = <&mpic>;
348 interrupts = <24 2>;
349 bus-range = <0 0>;
350 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
351 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
352 clock-frequency = <66666666>;
353 #interrupt-cells = <1>;
354 #size-cells = <2>;
355 #address-cells = <3>;
356 reg = <0xe0008000 0x1000>;
357 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
358 device_type = "pci";
359 };
360 };