| blob | 00c2bbda70134db027f1d169d9d1814c4317d545 |
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 rapidio0 = &rio0;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 PowerPC,8568@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
50 memory {
51 device_type = "memory";
52 reg = <0x0 0x10000000>;
53 };
55 bcsr@f8000000 {
56 compatible = "fsl,mpc8568mds-bcsr";
57 reg = <0xf8000000 0x8000>;
58 };
60 soc8568@e0000000 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 device_type = "soc";
64 compatible = "simple-bus";
65 ranges = <0x0 0xe0000000 0x100000>;
66 bus-frequency = <0>;
68 ecm-law@0 {
69 compatible = "fsl,ecm-law";
70 reg = <0x0 0x1000>;
71 fsl,num-laws = <10>;
72 };
74 ecm@1000 {
75 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
76 reg = <0x1000 0x1000>;
77 interrupts = <17 2>;
78 interrupt-parent = <&mpic>;
79 };
81 memory-controller@2000 {
82 compatible = "fsl,8568-memory-controller";
83 reg = <0x2000 0x1000>;
84 interrupt-parent = <&mpic>;
85 interrupts = <18 2>;
86 };
88 L2: l2-cache-controller@20000 {
89 compatible = "fsl,8568-l2-cache-controller";
90 reg = <0x20000 0x1000>;
91 cache-line-size = <32>; // 32 bytes
92 cache-size = <0x80000>; // L2, 512K
93 interrupt-parent = <&mpic>;
94 interrupts = <16 2>;
95 };
97 i2c@3000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 cell-index = <0>;
101 compatible = "fsl-i2c";
102 reg = <0x3000 0x100>;
103 interrupts = <43 2>;
104 interrupt-parent = <&mpic>;
105 dfsrr;
107 rtc@68 {
108 compatible = "dallas,ds1374";
109 reg = <0x68>;
110 };
111 };
113 i2c@3100 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 cell-index = <1>;
117 compatible = "fsl-i2c";
118 reg = <0x3100 0x100>;
119 interrupts = <43 2>;
120 interrupt-parent = <&mpic>;
121 dfsrr;
122 };
124 dma@21300 {
125 #address-cells = <1>;
126 #size-cells = <1>;
127 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
128 reg = <0x21300 0x4>;
129 ranges = <0x0 0x21100 0x200>;
130 cell-index = <0>;
131 dma-channel@0 {
132 compatible = "fsl,mpc8568-dma-channel",
133 "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <20 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,mpc8568-dma-channel",
141 "fsl,eloplus-dma-channel";
142 reg = <0x80 0x80>;
143 cell-index = <1>;
144 interrupt-parent = <&mpic>;
145 interrupts = <21 2>;
146 };
147 dma-channel@100 {
148 compatible = "fsl,mpc8568-dma-channel",
149 "fsl,eloplus-dma-channel";
150 reg = <0x100 0x80>;
151 cell-index = <2>;
152 interrupt-parent = <&mpic>;
153 interrupts = <22 2>;
154 };
155 dma-channel@180 {
156 compatible = "fsl,mpc8568-dma-channel",
157 "fsl,eloplus-dma-channel";
158 reg = <0x180 0x80>;
159 cell-index = <3>;
160 interrupt-parent = <&mpic>;
161 interrupts = <23 2>;
162 };
163 };
165 enet0: ethernet@24000 {
166 #address-cells = <1>;
167 #size-cells = <1>;
168 cell-index = <0>;
169 device_type = "network";
170 model = "eTSEC";
171 compatible = "gianfar";
172 reg = <0x24000 0x1000>;
173 ranges = <0x0 0x24000 0x1000>;
174 local-mac-address = [ 00 00 00 00 00 00 ];
175 interrupts = <29 2 30 2 34 2>;
176 interrupt-parent = <&mpic>;
177 tbi-handle = <&tbi0>;
178 phy-handle = <&phy2>;
180 mdio@520 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,gianfar-mdio";
184 reg = <0x520 0x20>;
186 phy0: ethernet-phy@7 {
187 interrupt-parent = <&mpic>;
188 interrupts = <1 1>;
189 reg = <0x7>;
190 device_type = "ethernet-phy";
191 };
192 phy1: ethernet-phy@1 {
193 interrupt-parent = <&mpic>;
194 interrupts = <2 1>;
195 reg = <0x1>;
196 device_type = "ethernet-phy";
197 };
198 phy2: ethernet-phy@2 {
199 interrupt-parent = <&mpic>;
200 interrupts = <1 1>;
201 reg = <0x2>;
202 device_type = "ethernet-phy";
203 };
204 phy3: ethernet-phy@3 {
205 interrupt-parent = <&mpic>;
206 interrupts = <2 1>;
207 reg = <0x3>;
208 device_type = "ethernet-phy";
209 };
210 tbi0: tbi-phy@11 {
211 reg = <0x11>;
212 device_type = "tbi-phy";
213 };
214 };
215 };
217 enet1: ethernet@25000 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 cell-index = <1>;
221 device_type = "network";
222 model = "eTSEC";
223 compatible = "gianfar";
224 reg = <0x25000 0x1000>;
225 ranges = <0x0 0x25000 0x1000>;
226 local-mac-address = [ 00 00 00 00 00 00 ];
227 interrupts = <35 2 36 2 40 2>;
228 interrupt-parent = <&mpic>;
229 tbi-handle = <&tbi1>;
230 phy-handle = <&phy3>;
232 mdio@520 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,gianfar-tbi";
236 reg = <0x520 0x20>;
238 tbi1: tbi-phy@11 {
239 reg = <0x11>;
240 device_type = "tbi-phy";
241 };
242 };
243 };
245 serial0: serial@4500 {
246 cell-index = <0>;
247 device_type = "serial";
248 compatible = "ns16550";
249 reg = <0x4500 0x100>;
250 clock-frequency = <0>;
251 interrupts = <42 2>;
252 interrupt-parent = <&mpic>;
253 };
255 global-utilities@e0000 { //global utilities block
256 compatible = "fsl,mpc8548-guts";
257 reg = <0xe0000 0x1000>;
258 fsl,has-rstcr;
259 };
261 serial1: serial@4600 {
262 cell-index = <1>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4600 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 2>;
268 interrupt-parent = <&mpic>;
269 };
271 crypto@30000 {
272 compatible = "fsl,sec2.1", "fsl,sec2.0";
273 reg = <0x30000 0x10000>;
274 interrupts = <45 2>;
275 interrupt-parent = <&mpic>;
276 fsl,num-channels = <4>;
277 fsl,channel-fifo-len = <24>;
278 fsl,exec-units-mask = <0xfe>;
279 fsl,descriptor-types-mask = <0x12b0ebf>;
280 };
282 mpic: pic@40000 {
283 interrupt-controller;
284 #address-cells = <0>;
285 #interrupt-cells = <2>;
286 reg = <0x40000 0x40000>;
287 compatible = "chrp,open-pic";
288 device_type = "open-pic";
289 };
291 msi@41600 {
292 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
293 reg = <0x41600 0x80>;
294 msi-available-ranges = <0 0x100>;
295 interrupts = <
296 0xe0 0
297 0xe1 0
298 0xe2 0
299 0xe3 0
300 0xe4 0
301 0xe5 0
302 0xe6 0
303 0xe7 0>;
304 interrupt-parent = <&mpic>;
305 };
307 par_io@e0100 {
308 reg = <0xe0100 0x100>;
309 device_type = "par_io";
310 num-ports = <7>;
312 pio1: ucc_pin@01 {
313 pio-map = <
314 /* port pin dir open_drain assignment has_irq */
315 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
316 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
317 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
318 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
319 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
320 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
321 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
322 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
323 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
324 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
325 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
326 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
327 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
328 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
329 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
330 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
331 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
332 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
333 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
334 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
335 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
336 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
337 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
338 };
340 pio2: ucc_pin@02 {
341 pio-map = <
342 /* port pin dir open_drain assignment has_irq */
343 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
344 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
345 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
346 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
347 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
348 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
349 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
350 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
351 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
352 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
353 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
354 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
355 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
356 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
357 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
358 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
359 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
360 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
361 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
362 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
363 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
364 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
365 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
366 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
367 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
368 };
369 };
370 };
372 qe@e0080000 {
373 #address-cells = <1>;
374 #size-cells = <1>;
375 device_type = "qe";
376 compatible = "fsl,qe";
377 ranges = <0x0 0xe0080000 0x40000>;
378 reg = <0xe0080000 0x480>;
379 brg-frequency = <0>;
380 bus-frequency = <396000000>;
381 fsl,qe-num-riscs = <2>;
382 fsl,qe-num-snums = <28>;
384 muram@10000 {
385 #address-cells = <1>;
386 #size-cells = <1>;
387 compatible = "fsl,qe-muram", "fsl,cpm-muram";
388 ranges = <0x0 0x10000 0x10000>;
390 data-only@0 {
391 compatible = "fsl,qe-muram-data",
392 "fsl,cpm-muram-data";
393 reg = <0x0 0x10000>;
394 };
395 };
397 spi@4c0 {
398 cell-index = <0>;
399 compatible = "fsl,spi";
400 reg = <0x4c0 0x40>;
401 interrupts = <2>;
402 interrupt-parent = <&qeic>;
403 mode = "cpu";
404 };
406 spi@500 {
407 cell-index = <1>;
408 compatible = "fsl,spi";
409 reg = <0x500 0x40>;
410 interrupts = <1>;
411 interrupt-parent = <&qeic>;
412 mode = "cpu";
413 };
415 enet2: ucc@2000 {
416 device_type = "network";
417 compatible = "ucc_geth";
418 cell-index = <1>;
419 reg = <0x2000 0x200>;
420 interrupts = <32>;
421 interrupt-parent = <&qeic>;
422 local-mac-address = [ 00 00 00 00 00 00 ];
423 rx-clock-name = "none";
424 tx-clock-name = "clk16";
425 pio-handle = <&pio1>;
426 phy-handle = <&phy0>;
427 phy-connection-type = "rgmii-id";
428 };
430 enet3: ucc@3000 {
431 device_type = "network";
432 compatible = "ucc_geth";
433 cell-index = <2>;
434 reg = <0x3000 0x200>;
435 interrupts = <33>;
436 interrupt-parent = <&qeic>;
437 local-mac-address = [ 00 00 00 00 00 00 ];
438 rx-clock-name = "none";
439 tx-clock-name = "clk16";
440 pio-handle = <&pio2>;
441 phy-handle = <&phy1>;
442 phy-connection-type = "rgmii-id";
443 };
445 mdio@2120 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <0x2120 0x18>;
449 compatible = "fsl,ucc-mdio";
451 /* These are the same PHYs as on
452 * gianfar's MDIO bus */
453 qe_phy0: ethernet-phy@07 {
454 interrupt-parent = <&mpic>;
455 interrupts = <1 1>;
456 reg = <0x7>;
457 device_type = "ethernet-phy";
458 };
459 qe_phy1: ethernet-phy@01 {
460 interrupt-parent = <&mpic>;
461 interrupts = <2 1>;
462 reg = <0x1>;
463 device_type = "ethernet-phy";
464 };
465 qe_phy2: ethernet-phy@02 {
466 interrupt-parent = <&mpic>;
467 interrupts = <1 1>;
468 reg = <0x2>;
469 device_type = "ethernet-phy";
470 };
471 qe_phy3: ethernet-phy@03 {
472 interrupt-parent = <&mpic>;
473 interrupts = <2 1>;
474 reg = <0x3>;
475 device_type = "ethernet-phy";
476 };
477 };
479 qeic: interrupt-controller@80 {
480 interrupt-controller;
481 compatible = "fsl,qe-ic";
482 #address-cells = <0>;
483 #interrupt-cells = <1>;
484 reg = <0x80 0x80>;
485 big-endian;
486 interrupts = <46 2 46 2>; //high:30 low:30
487 interrupt-parent = <&mpic>;
488 };
490 };
492 pci0: pci@e0008000 {
493 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
494 interrupt-map = <
495 /* IDSEL 0x12 AD18 */
496 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
497 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
498 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
499 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
501 /* IDSEL 0x13 AD19 */
502 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
503 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
504 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
505 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
507 interrupt-parent = <&mpic>;
508 interrupts = <24 2>;
509 bus-range = <0 255>;
510 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
511 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
512 clock-frequency = <66666666>;
513 #interrupt-cells = <1>;
514 #size-cells = <2>;
515 #address-cells = <3>;
516 reg = <0xe0008000 0x1000>;
517 compatible = "fsl,mpc8540-pci";
518 device_type = "pci";
519 };
521 /* PCI Express */
522 pci1: pcie@e000a000 {
523 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
524 interrupt-map = <
526 /* IDSEL 0x0 (PEX) */
527 00000 0x0 0x0 0x1 &mpic 0x0 0x1
528 00000 0x0 0x0 0x2 &mpic 0x1 0x1
529 00000 0x0 0x0 0x3 &mpic 0x2 0x1
530 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
532 interrupt-parent = <&mpic>;
533 interrupts = <26 2>;
534 bus-range = <0 255>;
535 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
536 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
537 clock-frequency = <33333333>;
538 #interrupt-cells = <1>;
539 #size-cells = <2>;
540 #address-cells = <3>;
541 reg = <0xe000a000 0x1000>;
542 compatible = "fsl,mpc8548-pcie";
543 device_type = "pci";
544 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>;
547 #address-cells = <3>;
548 device_type = "pci";
549 ranges = <0x2000000 0x0 0xa0000000
550 0x2000000 0x0 0xa0000000
551 0x0 0x10000000
553 0x1000000 0x0 0x0
554 0x1000000 0x0 0x0
555 0x0 0x800000>;
556 };
557 };
559 rio0: rapidio@e00c00000 {
560 #address-cells = <2>;
561 #size-cells = <2>;
562 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
563 reg = <0xe00c0000 0x20000>;
564 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
565 interrupts = <48 2 /* error */
566 49 2 /* bell_outb */
567 50 2 /* bell_inb */
568 53 2 /* msg1_tx */
569 54 2 /* msg1_rx */
570 55 2 /* msg2_tx */
571 56 2 /* msg2_rx */>;
572 interrupt-parent = <&mpic>;
573 };
574 };