| blob | 06332d61830a094e181f3790e4314c007d9ef0df |
1 /*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 ethernet5 = &enet5;
28 ethernet7 = &enet7;
29 pci1 = &pci1;
30 rapidio0 = &rio0;
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>;
45 bus-frequency = <0>;
46 clock-frequency = <0>;
47 next-level-cache = <&L2>;
48 };
49 };
51 memory {
52 device_type = "memory";
53 };
55 localbus@e0005000 {
56 #address-cells = <2>;
57 #size-cells = <1>;
58 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
59 reg = <0xe0005000 0x1000>;
60 interrupts = <19 2>;
61 interrupt-parent = <&mpic>;
63 ranges = <0x0 0x0 0xfe000000 0x02000000
64 0x1 0x0 0xf8000000 0x00008000
65 0x2 0x0 0xf0000000 0x04000000
66 0x3 0x0 0xfc000000 0x00008000
67 0x4 0x0 0xf8008000 0x00008000
68 0x5 0x0 0xf8010000 0x00008000>;
70 nor@0,0 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "cfi-flash";
74 reg = <0x0 0x0 0x02000000>;
75 bank-width = <1>;
76 device-width = <1>;
77 partition@0 {
78 label = "ramdisk";
79 reg = <0x00000000 0x01c00000>;
80 };
81 partition@1c00000 {
82 label = "kernel";
83 reg = <0x01c00000 0x002e0000>;
84 };
85 partiton@1ee0000 {
86 label = "dtb";
87 reg = <0x01ee0000 0x00020000>;
88 };
89 partition@1f00000 {
90 label = "firmware";
91 reg = <0x01f00000 0x00080000>;
92 read-only;
93 };
94 partition@1f80000 {
95 label = "u-boot";
96 reg = <0x01f80000 0x00080000>;
97 read-only;
98 };
99 };
101 bcsr@1,0 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "fsl,mpc8569mds-bcsr";
105 reg = <1 0 0x8000>;
106 ranges = <0 1 0 0x8000>;
108 bcsr17: gpio-controller@11 {
109 #gpio-cells = <2>;
110 compatible = "fsl,mpc8569mds-bcsr-gpio";
111 reg = <0x11 0x1>;
112 gpio-controller;
113 };
114 };
116 nand@3,0 {
117 compatible = "fsl,mpc8569-fcm-nand",
118 "fsl,elbc-fcm-nand";
119 reg = <3 0 0x8000>;
120 };
122 pib@4,0 {
123 compatible = "fsl,mpc8569mds-pib";
124 reg = <4 0 0x8000>;
125 };
127 pib@5,0 {
128 compatible = "fsl,mpc8569mds-pib";
129 reg = <5 0 0x8000>;
130 };
131 };
133 soc@e0000000 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 device_type = "soc";
137 compatible = "fsl,mpc8569-immr", "simple-bus";
138 ranges = <0x0 0xe0000000 0x100000>;
139 bus-frequency = <0>;
141 ecm-law@0 {
142 compatible = "fsl,ecm-law";
143 reg = <0x0 0x1000>;
144 fsl,num-laws = <10>;
145 };
147 ecm@1000 {
148 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
149 reg = <0x1000 0x1000>;
150 interrupts = <17 2>;
151 interrupt-parent = <&mpic>;
152 };
154 memory-controller@2000 {
155 compatible = "fsl,mpc8569-memory-controller";
156 reg = <0x2000 0x1000>;
157 interrupt-parent = <&mpic>;
158 interrupts = <18 2>;
159 };
161 i2c@3000 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 cell-index = <0>;
165 compatible = "fsl-i2c";
166 reg = <0x3000 0x100>;
167 interrupts = <43 2>;
168 interrupt-parent = <&mpic>;
169 dfsrr;
171 rtc@68 {
172 compatible = "dallas,ds1374";
173 reg = <0x68>;
174 };
175 };
177 i2c@3100 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 cell-index = <1>;
181 compatible = "fsl-i2c";
182 reg = <0x3100 0x100>;
183 interrupts = <43 2>;
184 interrupt-parent = <&mpic>;
185 dfsrr;
186 };
188 serial0: serial@4500 {
189 cell-index = <0>;
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <0x4500 0x100>;
193 clock-frequency = <0>;
194 interrupts = <42 2>;
195 interrupt-parent = <&mpic>;
196 };
198 serial1: serial@4600 {
199 cell-index = <1>;
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <0x4600 0x100>;
203 clock-frequency = <0>;
204 interrupts = <42 2>;
205 interrupt-parent = <&mpic>;
206 };
208 L2: l2-cache-controller@20000 {
209 compatible = "fsl,mpc8569-l2-cache-controller";
210 reg = <0x20000 0x1000>;
211 cache-line-size = <32>; // 32 bytes
212 cache-size = <0x80000>; // L2, 512K
213 interrupt-parent = <&mpic>;
214 interrupts = <16 2>;
215 };
217 dma@21300 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
221 reg = <0x21300 0x4>;
222 ranges = <0x0 0x21100 0x200>;
223 cell-index = <0>;
224 dma-channel@0 {
225 compatible = "fsl,mpc8569-dma-channel",
226 "fsl,eloplus-dma-channel";
227 reg = <0x0 0x80>;
228 cell-index = <0>;
229 interrupt-parent = <&mpic>;
230 interrupts = <20 2>;
231 };
232 dma-channel@80 {
233 compatible = "fsl,mpc8569-dma-channel",
234 "fsl,eloplus-dma-channel";
235 reg = <0x80 0x80>;
236 cell-index = <1>;
237 interrupt-parent = <&mpic>;
238 interrupts = <21 2>;
239 };
240 dma-channel@100 {
241 compatible = "fsl,mpc8569-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x100 0x80>;
244 cell-index = <2>;
245 interrupt-parent = <&mpic>;
246 interrupts = <22 2>;
247 };
248 dma-channel@180 {
249 compatible = "fsl,mpc8569-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x180 0x80>;
252 cell-index = <3>;
253 interrupt-parent = <&mpic>;
254 interrupts = <23 2>;
255 };
256 };
258 sdhci@2e000 {
259 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
260 reg = <0x2e000 0x1000>;
261 interrupts = <72 0x8>;
262 interrupt-parent = <&mpic>;
263 /* Filled in by U-Boot */
264 clock-frequency = <0>;
265 status = "disabled";
266 sdhci,1-bit-only;
267 };
269 crypto@30000 {
270 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
271 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
272 reg = <0x30000 0x10000>;
273 interrupts = <45 2 58 2>;
274 interrupt-parent = <&mpic>;
275 fsl,num-channels = <4>;
276 fsl,channel-fifo-len = <24>;
277 fsl,exec-units-mask = <0xbfe>;
278 fsl,descriptor-types-mask = <0x3ab0ebf>;
279 };
281 mpic: pic@40000 {
282 interrupt-controller;
283 #address-cells = <0>;
284 #interrupt-cells = <2>;
285 reg = <0x40000 0x40000>;
286 compatible = "chrp,open-pic";
287 device_type = "open-pic";
288 };
290 msi@41600 {
291 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
292 reg = <0x41600 0x80>;
293 msi-available-ranges = <0 0x100>;
294 interrupts = <
295 0xe0 0
296 0xe1 0
297 0xe2 0
298 0xe3 0
299 0xe4 0
300 0xe5 0
301 0xe6 0
302 0xe7 0>;
303 interrupt-parent = <&mpic>;
304 };
306 global-utilities@e0000 {
307 compatible = "fsl,mpc8569-guts";
308 reg = <0xe0000 0x1000>;
309 fsl,has-rstcr;
310 };
312 par_io@e0100 {
313 #address-cells = <1>;
314 #size-cells = <1>;
315 reg = <0xe0100 0x100>;
316 ranges = <0x0 0xe0100 0x100>;
317 device_type = "par_io";
318 num-ports = <7>;
320 qe_pio_e: gpio-controller@80 {
321 #gpio-cells = <2>;
322 compatible = "fsl,mpc8569-qe-pario-bank",
323 "fsl,mpc8323-qe-pario-bank";
324 reg = <0x80 0x18>;
325 gpio-controller;
326 };
328 qe_pio_f: gpio-controller@a0 {
329 #gpio-cells = <2>;
330 compatible = "fsl,mpc8569-qe-pario-bank",
331 "fsl,mpc8323-qe-pario-bank";
332 reg = <0xa0 0x18>;
333 gpio-controller;
334 };
336 pio1: ucc_pin@01 {
337 pio-map = <
338 /* port pin dir open_drain assignment has_irq */
339 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
340 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
341 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
342 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
343 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
344 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
345 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
346 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
347 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
348 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
349 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
350 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
351 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
352 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
353 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
354 };
356 pio2: ucc_pin@02 {
357 pio-map = <
358 /* port pin dir open_drain assignment has_irq */
359 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
360 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
361 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
362 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
363 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
364 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
365 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
366 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
367 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
368 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
369 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
370 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
371 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
372 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
373 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
374 };
376 pio3: ucc_pin@03 {
377 pio-map = <
378 /* port pin dir open_drain assignment has_irq */
379 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
380 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
381 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
382 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
383 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
384 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
385 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
386 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
387 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
388 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
389 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
390 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
391 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
392 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
393 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
394 };
396 pio4: ucc_pin@04 {
397 pio-map = <
398 /* port pin dir open_drain assignment has_irq */
399 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
400 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
401 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
402 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
403 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
404 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
405 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
406 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
407 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
408 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
409 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
410 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
411 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
412 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
413 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
414 };
415 };
416 };
418 qe@e0080000 {
419 #address-cells = <1>;
420 #size-cells = <1>;
421 device_type = "qe";
422 compatible = "fsl,qe";
423 ranges = <0x0 0xe0080000 0x40000>;
424 reg = <0xe0080000 0x480>;
425 brg-frequency = <0>;
426 bus-frequency = <0>;
427 fsl,qe-num-riscs = <4>;
428 fsl,qe-num-snums = <46>;
430 qeic: interrupt-controller@80 {
431 interrupt-controller;
432 compatible = "fsl,qe-ic";
433 #address-cells = <0>;
434 #interrupt-cells = <1>;
435 reg = <0x80 0x80>;
436 interrupts = <46 2 46 2>; //high:30 low:30
437 interrupt-parent = <&mpic>;
438 };
440 timer@440 {
441 compatible = "fsl,mpc8569-qe-gtm",
442 "fsl,qe-gtm", "fsl,gtm";
443 reg = <0x440 0x40>;
444 interrupts = <12 13 14 15>;
445 interrupt-parent = <&qeic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
450 spi@4c0 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
454 reg = <0x4c0 0x40>;
455 cell-index = <0>;
456 interrupts = <2>;
457 interrupt-parent = <&qeic>;
458 gpios = <&qe_pio_e 30 0>;
459 mode = "cpu-qe";
461 serial-flash@0 {
462 compatible = "stm,m25p40";
463 reg = <0>;
464 spi-max-frequency = <25000000>;
465 };
466 };
468 spi@500 {
469 cell-index = <1>;
470 compatible = "fsl,spi";
471 reg = <0x500 0x40>;
472 interrupts = <1>;
473 interrupt-parent = <&qeic>;
474 mode = "cpu";
475 };
477 usb@6c0 {
478 compatible = "fsl,mpc8569-qe-usb",
479 "fsl,mpc8323-qe-usb";
480 reg = <0x6c0 0x40 0x8b00 0x100>;
481 interrupts = <11>;
482 interrupt-parent = <&qeic>;
483 fsl,fullspeed-clock = "clk5";
484 fsl,lowspeed-clock = "brg10";
485 gpios = <&qe_pio_f 3 0 /* USBOE */
486 &qe_pio_f 4 0 /* USBTP */
487 &qe_pio_f 5 0 /* USBTN */
488 &qe_pio_f 6 0 /* USBRP */
489 &qe_pio_f 8 0 /* USBRN */
490 &bcsr17 6 0 /* SPEED */
491 &bcsr17 5 1>; /* POWER */
492 };
494 enet0: ucc@2000 {
495 device_type = "network";
496 compatible = "ucc_geth";
497 cell-index = <1>;
498 reg = <0x2000 0x200>;
499 interrupts = <32>;
500 interrupt-parent = <&qeic>;
501 local-mac-address = [ 00 00 00 00 00 00 ];
502 rx-clock-name = "none";
503 tx-clock-name = "clk12";
504 pio-handle = <&pio1>;
505 phy-handle = <&qe_phy0>;
506 phy-connection-type = "rgmii-id";
507 };
509 mdio@2120 {
510 #address-cells = <1>;
511 #size-cells = <0>;
512 reg = <0x2120 0x18>;
513 compatible = "fsl,ucc-mdio";
515 qe_phy0: ethernet-phy@07 {
516 interrupt-parent = <&mpic>;
517 interrupts = <1 1>;
518 reg = <0x7>;
519 device_type = "ethernet-phy";
520 };
521 qe_phy1: ethernet-phy@01 {
522 interrupt-parent = <&mpic>;
523 interrupts = <2 1>;
524 reg = <0x1>;
525 device_type = "ethernet-phy";
526 };
527 qe_phy2: ethernet-phy@02 {
528 interrupt-parent = <&mpic>;
529 interrupts = <3 1>;
530 reg = <0x2>;
531 device_type = "ethernet-phy";
532 };
533 qe_phy3: ethernet-phy@03 {
534 interrupt-parent = <&mpic>;
535 interrupts = <4 1>;
536 reg = <0x3>;
537 device_type = "ethernet-phy";
538 };
539 qe_phy5: ethernet-phy@04 {
540 interrupt-parent = <&mpic>;
541 reg = <0x04>;
542 device_type = "ethernet-phy";
543 };
544 qe_phy7: ethernet-phy@06 {
545 interrupt-parent = <&mpic>;
546 reg = <0x6>;
547 device_type = "ethernet-phy";
548 };
549 tbi-phy@11 {
550 reg = <0x11>;
551 device_type = "tbi-phy";
552 };
553 };
554 mdio@3520 {
555 #address-cells = <1>;
556 #size-cells = <0>;
557 reg = <0x3520 0x18>;
558 compatible = "fsl,ucc-mdio";
560 tbi0: tbi-phy@15 {
561 reg = <0x15>;
562 device_type = "tbi-phy";
563 };
564 };
565 mdio@3720 {
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <0x3720 0x38>;
569 compatible = "fsl,ucc-mdio";
570 tbi1: tbi-phy@17 {
571 reg = <0x17>;
572 device_type = "tbi-phy";
573 };
574 };
576 enet2: ucc@2200 {
577 device_type = "network";
578 compatible = "ucc_geth";
579 cell-index = <3>;
580 reg = <0x2200 0x200>;
581 interrupts = <34>;
582 interrupt-parent = <&qeic>;
583 local-mac-address = [ 00 00 00 00 00 00 ];
584 rx-clock-name = "none";
585 tx-clock-name = "clk12";
586 pio-handle = <&pio3>;
587 phy-handle = <&qe_phy2>;
588 phy-connection-type = "rgmii-id";
589 };
591 enet1: ucc@3000 {
592 device_type = "network";
593 compatible = "ucc_geth";
594 cell-index = <2>;
595 reg = <0x3000 0x200>;
596 interrupts = <33>;
597 interrupt-parent = <&qeic>;
598 local-mac-address = [ 00 00 00 00 00 00 ];
599 rx-clock-name = "none";
600 tx-clock-name = "clk17";
601 pio-handle = <&pio2>;
602 phy-handle = <&qe_phy1>;
603 phy-connection-type = "rgmii-id";
604 };
606 enet3: ucc@3200 {
607 device_type = "network";
608 compatible = "ucc_geth";
609 cell-index = <4>;
610 reg = <0x3200 0x200>;
611 interrupts = <35>;
612 interrupt-parent = <&qeic>;
613 local-mac-address = [ 00 00 00 00 00 00 ];
614 rx-clock-name = "none";
615 tx-clock-name = "clk17";
616 pio-handle = <&pio4>;
617 phy-handle = <&qe_phy3>;
618 phy-connection-type = "rgmii-id";
619 };
621 enet5: ucc@3400 {
622 device_type = "network";
623 compatible = "ucc_geth";
624 cell-index = <6>;
625 reg = <0x3400 0x200>;
626 interrupts = <41>;
627 interrupt-parent = <&qeic>;
628 local-mac-address = [ 00 00 00 00 00 00 ];
629 rx-clock-name = "none";
630 tx-clock-name = "none";
631 tbi-handle = <&tbi0>;
632 phy-handle = <&qe_phy5>;
633 phy-connection-type = "sgmii";
634 };
636 enet7: ucc@3600 {
637 device_type = "network";
638 compatible = "ucc_geth";
639 cell-index = <8>;
640 reg = <0x3600 0x200>;
641 interrupts = <43>;
642 interrupt-parent = <&qeic>;
643 local-mac-address = [ 00 00 00 00 00 00 ];
644 rx-clock-name = "none";
645 tx-clock-name = "none";
646 tbi-handle = <&tbi1>;
647 phy-handle = <&qe_phy7>;
648 phy-connection-type = "sgmii";
649 };
651 muram@10000 {
652 #address-cells = <1>;
653 #size-cells = <1>;
654 compatible = "fsl,qe-muram", "fsl,cpm-muram";
655 ranges = <0x0 0x10000 0x20000>;
657 data-only@0 {
658 compatible = "fsl,qe-muram-data",
659 "fsl,cpm-muram-data";
660 reg = <0x0 0x20000>;
661 };
662 };
664 };
666 /* PCI Express */
667 pci1: pcie@e000a000 {
668 compatible = "fsl,mpc8548-pcie";
669 device_type = "pci";
670 #interrupt-cells = <1>;
671 #size-cells = <2>;
672 #address-cells = <3>;
673 reg = <0xe000a000 0x1000>;
674 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
675 interrupt-map = <
676 /* IDSEL 0x0 (PEX) */
677 00000 0x0 0x0 0x1 &mpic 0x0 0x1
678 00000 0x0 0x0 0x2 &mpic 0x1 0x1
679 00000 0x0 0x0 0x3 &mpic 0x2 0x1
680 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
682 interrupt-parent = <&mpic>;
683 interrupts = <26 2>;
684 bus-range = <0 255>;
685 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
686 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
687 clock-frequency = <33333333>;
688 pcie@0 {
689 reg = <0x0 0x0 0x0 0x0 0x0>;
690 #size-cells = <2>;
691 #address-cells = <3>;
692 device_type = "pci";
693 ranges = <0x2000000 0x0 0xa0000000
694 0x2000000 0x0 0xa0000000
695 0x0 0x10000000
697 0x1000000 0x0 0x0
698 0x1000000 0x0 0x0
699 0x0 0x800000>;
700 };
701 };
703 rio0: rapidio@e00c00000 {
704 #address-cells = <2>;
705 #size-cells = <2>;
706 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
707 reg = <0xe00c0000 0x20000>;
708 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
709 interrupts = <48 2 /* error */
710 49 2 /* bell_outb */
711 50 2 /* bell_inb */
712 53 2 /* msg1_tx */
713 54 2 /* msg1_rx */
714 55 2 /* msg2_tx */
715 56 2 /* msg2_rx */>;
716 interrupt-parent = <&mpic>;
717 };
718 };