| blob | f468d215f71675df5414339a4d79fd063a3772cf |
1 /*
2 * MPC8610 HPCD Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
9 */
11 /dts-v1/;
13 / {
14 model = "MPC8610HPCD";
15 compatible = "fsl,MPC8610HPCD";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 pci0 = &pci0;
23 pci1 = &pci1;
24 pci2 = &pci2;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 PowerPC,8610@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
38 timebase-frequency = <0>; // From uboot
39 bus-frequency = <0>; // From uboot
40 clock-frequency = <0>; // From uboot
41 };
42 };
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x20000000>; // 512M at 0x0
47 };
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <19 2>;
55 interrupt-parent = <&mpic>;
56 ranges = <0 0 0xf8000000 0x08000000
57 1 0 0xf0000000 0x08000000
58 2 0 0xe8400000 0x00008000
59 4 0 0xe8440000 0x00008000
60 5 0 0xe8480000 0x00008000
61 6 0 0xe84c0000 0x00008000
62 3 0 0xe8000000 0x00000020>;
64 flash@0,0 {
65 compatible = "cfi-flash";
66 reg = <0 0 0x8000000>;
67 bank-width = <2>;
68 device-width = <1>;
69 };
71 flash@1,0 {
72 compatible = "cfi-flash";
73 reg = <1 0 0x8000000>;
74 bank-width = <2>;
75 device-width = <1>;
76 };
78 flash@2,0 {
79 compatible = "fsl,mpc8610-fcm-nand",
80 "fsl,elbc-fcm-nand";
81 reg = <2 0 0x8000>;
82 };
84 flash@4,0 {
85 compatible = "fsl,mpc8610-fcm-nand",
86 "fsl,elbc-fcm-nand";
87 reg = <4 0 0x8000>;
88 };
90 flash@5,0 {
91 compatible = "fsl,mpc8610-fcm-nand",
92 "fsl,elbc-fcm-nand";
93 reg = <5 0 0x8000>;
94 };
96 flash@6,0 {
97 compatible = "fsl,mpc8610-fcm-nand",
98 "fsl,elbc-fcm-nand";
99 reg = <6 0 0x8000>;
100 };
102 board-control@3,0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,fpga-pixis";
106 reg = <3 0 0x20>;
107 ranges = <0 3 0 0x20>;
109 sdcsr_pio: gpio-controller@a {
110 #gpio-cells = <2>;
111 compatible = "fsl,fpga-pixis-gpio-bank";
112 reg = <0xa 1>;
113 gpio-controller;
114 };
115 };
116 };
118 soc@e0000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 #interrupt-cells = <2>;
122 device_type = "soc";
123 compatible = "fsl,mpc8610-immr", "simple-bus";
124 ranges = <0x0 0xe0000000 0x00100000>;
125 bus-frequency = <0>;
127 mcm-law@0 {
128 compatible = "fsl,mcm-law";
129 reg = <0x0 0x1000>;
130 fsl,num-laws = <10>;
131 };
133 mcm@1000 {
134 compatible = "fsl,mpc8610-mcm", "fsl,mcm";
135 reg = <0x1000 0x1000>;
136 interrupts = <17 2>;
137 interrupt-parent = <&mpic>;
138 };
140 i2c@3000 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 cell-index = <0>;
144 compatible = "fsl-i2c";
145 reg = <0x3000 0x100>;
146 interrupts = <43 2>;
147 interrupt-parent = <&mpic>;
148 dfsrr;
150 cs4270:codec@4f {
151 compatible = "cirrus,cs4270";
152 reg = <0x4f>;
153 /* MCLK source is a stand-alone oscillator */
154 clock-frequency = <12288000>;
155 };
156 };
158 i2c@3100 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 cell-index = <1>;
162 compatible = "fsl-i2c";
163 reg = <0x3100 0x100>;
164 interrupts = <43 2>;
165 interrupt-parent = <&mpic>;
166 dfsrr;
167 };
169 serial0: serial@4500 {
170 cell-index = <0>;
171 device_type = "serial";
172 compatible = "ns16550";
173 reg = <0x4500 0x100>;
174 clock-frequency = <0>;
175 interrupts = <42 2>;
176 interrupt-parent = <&mpic>;
177 };
179 serial1: serial@4600 {
180 cell-index = <1>;
181 device_type = "serial";
182 compatible = "ns16550";
183 reg = <0x4600 0x100>;
184 clock-frequency = <0>;
185 interrupts = <42 2>;
186 interrupt-parent = <&mpic>;
187 };
189 spi@7000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "fsl,mpc8610-spi", "fsl,spi";
193 reg = <0x7000 0x40>;
194 cell-index = <0>;
195 interrupts = <59 2>;
196 interrupt-parent = <&mpic>;
197 mode = "cpu";
198 gpios = <&sdcsr_pio 7 0>;
200 mmc-slot@0 {
201 compatible = "fsl,mpc8610hpcd-mmc-slot",
202 "mmc-spi-slot";
203 reg = <0>;
204 gpios = <&sdcsr_pio 0 1 /* nCD */
205 &sdcsr_pio 1 0>; /* WP */
206 voltage-ranges = <3300 3300>;
207 spi-max-frequency = <50000000>;
208 };
209 };
211 display@2c000 {
212 compatible = "fsl,diu";
213 reg = <0x2c000 100>;
214 interrupts = <72 2>;
215 interrupt-parent = <&mpic>;
216 };
218 mpic: interrupt-controller@40000 {
219 interrupt-controller;
220 #address-cells = <0>;
221 #interrupt-cells = <2>;
222 reg = <0x40000 0x40000>;
223 compatible = "chrp,open-pic";
224 device_type = "open-pic";
225 };
227 msi@41600 {
228 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
229 reg = <0x41600 0x80>;
230 msi-available-ranges = <0 0x100>;
231 interrupts = <
232 0xe0 0
233 0xe1 0
234 0xe2 0
235 0xe3 0
236 0xe4 0
237 0xe5 0
238 0xe6 0
239 0xe7 0>;
240 interrupt-parent = <&mpic>;
241 };
243 global-utilities@e0000 {
244 compatible = "fsl,mpc8610-guts";
245 reg = <0xe0000 0x1000>;
246 fsl,has-rstcr;
247 };
249 wdt@e4000 {
250 compatible = "fsl,mpc8610-wdt";
251 reg = <0xe4000 0x100>;
252 };
254 ssi@16000 {
255 compatible = "fsl,mpc8610-ssi";
256 cell-index = <0>;
257 reg = <0x16000 0x100>;
258 interrupt-parent = <&mpic>;
259 interrupts = <62 2>;
260 fsl,mode = "i2s-slave";
261 codec-handle = <&cs4270>;
262 fsl,playback-dma = <&dma00>;
263 fsl,capture-dma = <&dma01>;
264 fsl,fifo-depth = <8>;
265 };
267 ssi@16100 {
268 compatible = "fsl,mpc8610-ssi";
269 cell-index = <1>;
270 reg = <0x16100 0x100>;
271 interrupt-parent = <&mpic>;
272 interrupts = <63 2>;
273 fsl,fifo-depth = <8>;
274 };
276 dma@21300 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
280 cell-index = <0>;
281 reg = <0x21300 0x4>; /* DMA general status register */
282 ranges = <0x0 0x21100 0x200>;
284 dma00: dma-channel@0 {
285 compatible = "fsl,mpc8610-dma-channel",
286 "fsl,ssi-dma-channel";
287 cell-index = <0>;
288 reg = <0x0 0x80>;
289 interrupt-parent = <&mpic>;
290 interrupts = <20 2>;
291 };
292 dma01: dma-channel@1 {
293 compatible = "fsl,mpc8610-dma-channel",
294 "fsl,ssi-dma-channel";
295 cell-index = <1>;
296 reg = <0x80 0x80>;
297 interrupt-parent = <&mpic>;
298 interrupts = <21 2>;
299 };
300 dma-channel@2 {
301 compatible = "fsl,mpc8610-dma-channel",
302 "fsl,eloplus-dma-channel";
303 cell-index = <2>;
304 reg = <0x100 0x80>;
305 interrupt-parent = <&mpic>;
306 interrupts = <22 2>;
307 };
308 dma-channel@3 {
309 compatible = "fsl,mpc8610-dma-channel",
310 "fsl,eloplus-dma-channel";
311 cell-index = <3>;
312 reg = <0x180 0x80>;
313 interrupt-parent = <&mpic>;
314 interrupts = <23 2>;
315 };
316 };
318 dma@c300 {
319 #address-cells = <1>;
320 #size-cells = <1>;
321 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
322 cell-index = <1>;
323 reg = <0xc300 0x4>; /* DMA general status register */
324 ranges = <0x0 0xc100 0x200>;
326 dma-channel@0 {
327 compatible = "fsl,mpc8610-dma-channel",
328 "fsl,eloplus-dma-channel";
329 cell-index = <0>;
330 reg = <0x0 0x80>;
331 interrupt-parent = <&mpic>;
332 interrupts = <76 2>;
333 };
334 dma-channel@1 {
335 compatible = "fsl,mpc8610-dma-channel",
336 "fsl,eloplus-dma-channel";
337 cell-index = <1>;
338 reg = <0x80 0x80>;
339 interrupt-parent = <&mpic>;
340 interrupts = <77 2>;
341 };
342 dma-channel@2 {
343 compatible = "fsl,mpc8610-dma-channel",
344 "fsl,eloplus-dma-channel";
345 cell-index = <2>;
346 reg = <0x100 0x80>;
347 interrupt-parent = <&mpic>;
348 interrupts = <78 2>;
349 };
350 dma-channel@3 {
351 compatible = "fsl,mpc8610-dma-channel",
352 "fsl,eloplus-dma-channel";
353 cell-index = <3>;
354 reg = <0x180 0x80>;
355 interrupt-parent = <&mpic>;
356 interrupts = <79 2>;
357 };
358 };
360 };
362 pci0: pci@e0008000 {
363 compatible = "fsl,mpc8610-pci";
364 device_type = "pci";
365 #interrupt-cells = <1>;
366 #size-cells = <2>;
367 #address-cells = <3>;
368 reg = <0xe0008000 0x1000>;
369 bus-range = <0 0>;
370 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
371 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
372 clock-frequency = <33333333>;
373 interrupt-parent = <&mpic>;
374 interrupts = <24 2>;
375 interrupt-map-mask = <0xf800 0 0 7>;
376 interrupt-map = <
377 /* IDSEL 0x11 */
378 0x8800 0 0 1 &mpic 4 1
379 0x8800 0 0 2 &mpic 5 1
380 0x8800 0 0 3 &mpic 6 1
381 0x8800 0 0 4 &mpic 7 1
383 /* IDSEL 0x12 */
384 0x9000 0 0 1 &mpic 5 1
385 0x9000 0 0 2 &mpic 6 1
386 0x9000 0 0 3 &mpic 7 1
387 0x9000 0 0 4 &mpic 4 1
388 >;
389 };
391 pci1: pcie@e000a000 {
392 compatible = "fsl,mpc8641-pcie";
393 device_type = "pci";
394 #interrupt-cells = <1>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 reg = <0xe000a000 0x1000>;
398 bus-range = <1 3>;
399 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
400 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
401 clock-frequency = <33333333>;
402 interrupt-parent = <&mpic>;
403 interrupts = <26 2>;
404 interrupt-map-mask = <0xf800 0 0 7>;
406 interrupt-map = <
407 /* IDSEL 0x1b */
408 0xd800 0 0 1 &mpic 2 1
410 /* IDSEL 0x1c*/
411 0xe000 0 0 1 &mpic 1 1
412 0xe000 0 0 2 &mpic 1 1
413 0xe000 0 0 3 &mpic 1 1
414 0xe000 0 0 4 &mpic 1 1
416 /* IDSEL 0x1f */
417 0xf800 0 0 1 &mpic 3 2
418 0xf800 0 0 2 &mpic 0 1
419 >;
421 pcie@0 {
422 reg = <0 0 0 0 0>;
423 #size-cells = <2>;
424 #address-cells = <3>;
425 device_type = "pci";
426 ranges = <0x02000000 0x0 0xa0000000
427 0x02000000 0x0 0xa0000000
428 0x0 0x10000000
429 0x01000000 0x0 0x00000000
430 0x01000000 0x0 0x00000000
431 0x0 0x00100000>;
432 uli1575@0 {
433 reg = <0 0 0 0 0>;
434 #size-cells = <2>;
435 #address-cells = <3>;
436 ranges = <0x02000000 0x0 0xa0000000
437 0x02000000 0x0 0xa0000000
438 0x0 0x10000000
439 0x01000000 0x0 0x00000000
440 0x01000000 0x0 0x00000000
441 0x0 0x00100000>;
443 isa@1e {
444 device_type = "isa";
445 #size-cells = <1>;
446 #address-cells = <2>;
447 reg = <0xf000 0 0 0 0>;
448 ranges = <1 0 0x01000000 0 0
449 0x00001000>;
451 rtc@70 {
452 compatible = "pnpPNP,b00";
453 reg = <1 0x70 2>;
454 };
455 };
456 };
457 };
458 };
460 pci2: pcie@e0009000 {
461 #address-cells = <3>;
462 #size-cells = <2>;
463 #interrupt-cells = <1>;
464 device_type = "pci";
465 compatible = "fsl,mpc8641-pcie";
466 reg = <0xe0009000 0x00001000>;
467 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
468 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
469 bus-range = <0 255>;
470 interrupt-map-mask = <0xf800 0 0 7>;
471 interrupt-map = <0x0000 0 0 1 &mpic 4 1
472 0x0000 0 0 2 &mpic 5 1
473 0x0000 0 0 3 &mpic 6 1
474 0x0000 0 0 4 &mpic 7 1>;
475 interrupt-parent = <&mpic>;
476 interrupts = <25 2>;
477 clock-frequency = <33333333>;
478 };
479 };