arch/sh/kernel/cpu/irq/ipr.c

   1 /*
   2  * Interrupt handling for IPR-based IRQ.
   3  *
   4  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   5  * Copyright (C) 2000  Kazumoto Kojima
   6  * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
   7  * Copyright (C) 2006  Paul Mundt
   8  *
   9  * Supported system:
  10  *      On-chip supporting modules (TMU, RTC, etc.).
  11  *      On-chip supporting modules for SH7709/SH7709A/SH7729.
  12  *      Hitachi SolutionEngine external I/O:
  13  *              MS7709SE01, MS7709ASE01, and MS7750SE01
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/topology.h>
  25
  26 static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
  27 {
  28         struct irq_chip *chip = get_irq_chip(irq);
  29         return (void *)((char *)chip - offsetof(struct ipr_desc, chip));
  30 }
  31
  32 static void disable_ipr_irq(unsigned int irq)
  33 {
  34         struct ipr_data *p = get_irq_chip_data(irq);
  35         unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
  36         /* Set the priority in IPR to 0 */
  37         __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
  38         (void)__raw_readw(addr);        /* Read back to flush write posting */
  39 }
  40
  41 static void enable_ipr_irq(unsigned int irq)
  42 {
  43         struct ipr_data *p = get_irq_chip_data(irq);
  44         unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
  45         /* Set priority in IPR back to original value */
  46         __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
  47 }
  48
  49 /*
  50  * The shift value is now the number of bits to shift, not the number of
  51  * bits/4. This is to make it easier to read the value directly from the
  52  * datasheets. The IPR address is calculated using the ipr_offset table.
  53  */
  54 void register_ipr_controller(struct ipr_desc *desc)
  55 {
  56         int i;
  57
  58         desc->chip.mask = disable_ipr_irq;
  59         desc->chip.unmask = enable_ipr_irq;
  60         desc->chip.mask_ack = disable_ipr_irq;
  61
  62         for (i = 0; i < desc->nr_irqs; i++) {
  63                 struct ipr_data *p = desc->ipr_data + i;
  64                 struct irq_desc *irq_desc;
  65
  66                 BUG_ON(p->ipr_idx >= desc->nr_offsets);
  67                 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
  68
  69                 irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
  70                 if (unlikely(!irq_desc)) {
  71                         printk(KERN_INFO "can not get irq_desc for %d\n",
  72                                p->irq);
  73                         continue;
  74                 }
  75
  76                 disable_irq_nosync(p->irq);
  77                 set_irq_chip_and_handler_name(p->irq, &desc->chip,
  78                                       handle_level_irq, "level");
  79                 set_irq_chip_data(p->irq, p);
  80                 disable_ipr_irq(p->irq);
  81         }
  82 }
  83 EXPORT_SYMBOL(register_ipr_controller);