arch/sh/kernel/cpu/sh4a/setup-sh7343.c

   1 /*
   2  * SH7343 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/uio_driver.h>
  15 #include <linux/sh_timer.h>
  16 #include <asm/clock.h>
  17
  18 static struct resource iic0_resources[] = {
  19         [0] = {
  20                 .name   = "IIC0",
  21                 .start  = 0x04470000,
  22                 .end    = 0x04470017,
  23                 .flags  = IORESOURCE_MEM,
  24         },
  25         [1] = {
  26                 .start  = 96,
  27                 .end    = 99,
  28                 .flags  = IORESOURCE_IRQ,
  29        },
  30 };
  31
  32 static struct platform_device iic0_device = {
  33         .name           = "i2c-sh_mobile",
  34         .id             = 0, /* "i2c0" clock */
  35         .num_resources  = ARRAY_SIZE(iic0_resources),
  36         .resource       = iic0_resources,
  37 };
  38
  39 static struct resource iic1_resources[] = {
  40         [0] = {
  41                 .name   = "IIC1",
  42                 .start  = 0x04750000,
  43                 .end    = 0x04750017,
  44                 .flags  = IORESOURCE_MEM,
  45         },
  46         [1] = {
  47                 .start  = 44,
  48                 .end    = 47,
  49                 .flags  = IORESOURCE_IRQ,
  50        },
  51 };
  52
  53 static struct platform_device iic1_device = {
  54         .name           = "i2c-sh_mobile",
  55         .id             = 1, /* "i2c1" clock */
  56         .num_resources  = ARRAY_SIZE(iic1_resources),
  57         .resource       = iic1_resources,
  58 };
  59
  60 static struct uio_info vpu_platform_data = {
  61         .name = "VPU4",
  62         .version = "0",
  63         .irq = 60,
  64 };
  65
  66 static struct resource vpu_resources[] = {
  67         [0] = {
  68                 .name   = "VPU",
  69                 .start  = 0xfe900000,
  70                 .end    = 0xfe9022eb,
  71                 .flags  = IORESOURCE_MEM,
  72         },
  73         [1] = {
  74                 /* place holder for contiguous memory */
  75         },
  76 };
  77
  78 static struct platform_device vpu_device = {
  79         .name           = "uio_pdrv_genirq",
  80         .id             = 0,
  81         .dev = {
  82                 .platform_data  = &vpu_platform_data,
  83         },
  84         .resource       = vpu_resources,
  85         .num_resources  = ARRAY_SIZE(vpu_resources),
  86 };
  87
  88 static struct uio_info veu_platform_data = {
  89         .name = "VEU",
  90         .version = "0",
  91         .irq = 54,
  92 };
  93
  94 static struct resource veu_resources[] = {
  95         [0] = {
  96                 .name   = "VEU",
  97                 .start  = 0xfe920000,
  98                 .end    = 0xfe9200b7,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 /* place holder for contiguous memory */
 103         },
 104 };
 105
 106 static struct platform_device veu_device = {
 107         .name           = "uio_pdrv_genirq",
 108         .id             = 1,
 109         .dev = {
 110                 .platform_data  = &veu_platform_data,
 111         },
 112         .resource       = veu_resources,
 113         .num_resources  = ARRAY_SIZE(veu_resources),
 114 };
 115
 116 static struct uio_info jpu_platform_data = {
 117         .name = "JPU",
 118         .version = "0",
 119         .irq = 27,
 120 };
 121
 122 static struct resource jpu_resources[] = {
 123         [0] = {
 124                 .name   = "JPU",
 125                 .start  = 0xfea00000,
 126                 .end    = 0xfea102d3,
 127                 .flags  = IORESOURCE_MEM,
 128         },
 129         [1] = {
 130                 /* place holder for contiguous memory */
 131         },
 132 };
 133
 134 static struct platform_device jpu_device = {
 135         .name           = "uio_pdrv_genirq",
 136         .id             = 2,
 137         .dev = {
 138                 .platform_data  = &jpu_platform_data,
 139         },
 140         .resource       = jpu_resources,
 141         .num_resources  = ARRAY_SIZE(jpu_resources),
 142 };
 143
 144 static struct sh_timer_config cmt_platform_data = {
 145         .name = "CMT",
 146         .channel_offset = 0x60,
 147         .timer_bit = 5,
 148         .clk = "cmt0",
 149         .clockevent_rating = 125,
 150         .clocksource_rating = 200,
 151 };
 152
 153 static struct resource cmt_resources[] = {
 154         [0] = {
 155                 .name   = "CMT",
 156                 .start  = 0x044a0060,
 157                 .end    = 0x044a006b,
 158                 .flags  = IORESOURCE_MEM,
 159         },
 160         [1] = {
 161                 .start  = 104,
 162                 .flags  = IORESOURCE_IRQ,
 163         },
 164 };
 165
 166 static struct platform_device cmt_device = {
 167         .name           = "sh_cmt",
 168         .id             = 0,
 169         .dev = {
 170                 .platform_data  = &cmt_platform_data,
 171         },
 172         .resource       = cmt_resources,
 173         .num_resources  = ARRAY_SIZE(cmt_resources),
 174 };
 175
 176 static struct sh_timer_config tmu0_platform_data = {
 177         .name = "TMU0",
 178         .channel_offset = 0x04,
 179         .timer_bit = 0,
 180         .clk = "tmu0",
 181         .clockevent_rating = 200,
 182 };
 183
 184 static struct resource tmu0_resources[] = {
 185         [0] = {
 186                 .name   = "TMU0",
 187                 .start  = 0xffd80008,
 188                 .end    = 0xffd80013,
 189                 .flags  = IORESOURCE_MEM,
 190         },
 191         [1] = {
 192                 .start  = 16,
 193                 .flags  = IORESOURCE_IRQ,
 194         },
 195 };
 196
 197 static struct platform_device tmu0_device = {
 198         .name           = "sh_tmu",
 199         .id             = 0,
 200         .dev = {
 201                 .platform_data  = &tmu0_platform_data,
 202         },
 203         .resource       = tmu0_resources,
 204         .num_resources  = ARRAY_SIZE(tmu0_resources),
 205 };
 206
 207 static struct sh_timer_config tmu1_platform_data = {
 208         .name = "TMU1",
 209         .channel_offset = 0x10,
 210         .timer_bit = 1,
 211         .clk = "tmu0",
 212         .clocksource_rating = 200,
 213 };
 214
 215 static struct resource tmu1_resources[] = {
 216         [0] = {
 217                 .name   = "TMU1",
 218                 .start  = 0xffd80014,
 219                 .end    = 0xffd8001f,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = 17,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device tmu1_device = {
 229         .name           = "sh_tmu",
 230         .id             = 1,
 231         .dev = {
 232                 .platform_data  = &tmu1_platform_data,
 233         },
 234         .resource       = tmu1_resources,
 235         .num_resources  = ARRAY_SIZE(tmu1_resources),
 236 };
 237
 238 static struct sh_timer_config tmu2_platform_data = {
 239         .name = "TMU2",
 240         .channel_offset = 0x1c,
 241         .timer_bit = 2,
 242         .clk = "tmu0",
 243 };
 244
 245 static struct resource tmu2_resources[] = {
 246         [0] = {
 247                 .name   = "TMU2",
 248                 .start  = 0xffd80020,
 249                 .end    = 0xffd8002b,
 250                 .flags  = IORESOURCE_MEM,
 251         },
 252         [1] = {
 253                 .start  = 18,
 254                 .flags  = IORESOURCE_IRQ,
 255         },
 256 };
 257
 258 static struct platform_device tmu2_device = {
 259         .name           = "sh_tmu",
 260         .id             = 2,
 261         .dev = {
 262                 .platform_data  = &tmu2_platform_data,
 263         },
 264         .resource       = tmu2_resources,
 265         .num_resources  = ARRAY_SIZE(tmu2_resources),
 266 };
 267
 268 static struct plat_sci_port sci_platform_data[] = {
 269         {
 270                 .mapbase        = 0xffe00000,
 271                 .flags          = UPF_BOOT_AUTOCONF,
 272                 .type           = PORT_SCIF,
 273                 .irqs           = { 80, 80, 80, 80 },
 274                 .clk            = "scif0",
 275         }, {
 276                 .mapbase        = 0xffe10000,
 277                 .flags          = UPF_BOOT_AUTOCONF,
 278                 .type           = PORT_SCIF,
 279                 .irqs           = { 81, 81, 81, 81 },
 280                 .clk            = "scif1",
 281         }, {
 282                 .mapbase        = 0xffe20000,
 283                 .flags          = UPF_BOOT_AUTOCONF,
 284                 .type           = PORT_SCIF,
 285                 .irqs           = { 82, 82, 82, 82 },
 286                 .clk            = "scif2",
 287         }, {
 288                 .mapbase        = 0xffe30000,
 289                 .flags          = UPF_BOOT_AUTOCONF,
 290                 .type           = PORT_SCIF,
 291                 .irqs           = { 83, 83, 83, 83 },
 292                 .clk            = "scif3",
 293         }, {
 294                 .flags = 0,
 295         }
 296 };
 297
 298 static struct platform_device sci_device = {
 299         .name           = "sh-sci",
 300         .id             = -1,
 301         .dev            = {
 302                 .platform_data  = sci_platform_data,
 303         },
 304 };
 305
 306 static struct platform_device *sh7343_devices[] __initdata = {
 307         &cmt_device,
 308         &tmu0_device,
 309         &tmu1_device,
 310         &tmu2_device,
 311         &iic0_device,
 312         &iic1_device,
 313         &sci_device,
 314         &vpu_device,
 315         &veu_device,
 316         &jpu_device,
 317 };
 318
 319 static int __init sh7343_devices_setup(void)
 320 {
 321         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 322         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 323         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 324
 325         return platform_add_devices(sh7343_devices,
 326                                     ARRAY_SIZE(sh7343_devices));
 327 }
 328 arch_initcall(sh7343_devices_setup);
 329
 330 static struct platform_device *sh7343_early_devices[] __initdata = {
 331         &cmt_device,
 332         &tmu0_device,
 333         &tmu1_device,
 334         &tmu2_device,
 335 };
 336
 337 void __init plat_early_device_setup(void)
 338 {
 339         early_platform_add_devices(sh7343_early_devices,
 340                                    ARRAY_SIZE(sh7343_early_devices));
 341 }
 342
 343 enum {
 344         UNUSED = 0,
 345
 346         /* interrupt sources */
 347         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 348         DMAC0, DMAC1, DMAC2, DMAC3,
 349         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 350         MFI, VPU, TPU, Z3D4, USBI0, USBI1,
 351         MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
 352         DMAC4, DMAC5, DMAC_DADERR,
 353         KEYSC,
 354         SCIF, SCIF1, SCIF2, SCIF3,
 355         SIOF0, SIOF1, SIO,
 356         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 357         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 358         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 359         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
 360         IRDA,
 361         SDHI0, SDHI1, SDHI2, SDHI3,
 362         CMT, TSIF, SIU,
 363         TMU0, TMU1, TMU2,
 364         JPU, LCDC,
 365
 366         /* interrupt groups */
 367
 368         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
 369 };
 370
 371 static struct intc_vect vectors[] __initdata = {
 372         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 373         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 374         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 375         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 376         INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
 377         INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
 378         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 379         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 380         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 381         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 382         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
 383         INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
 384         INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
 385         INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
 386         INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
 387         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 388         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 389         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
 390         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
 391         INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
 392         INTC_VECT(SIO, 0xd00),
 393         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 394         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 395         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
 396         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
 397         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 398         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 399         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 400         INTC_VECT(SIU, 0xf80),
 401         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 402         INTC_VECT(TMU2, 0x440),
 403         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 404 };
 405
 406 static struct intc_group groups[] __initdata = {
 407         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 408         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 409         INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
 410         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 411         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 412                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 413         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 414         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 415         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
 416         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 417         INTC_GROUP(USB, USBI0, USBI1),
 418 };
 419
 420 static struct intc_mask_reg mask_registers[] __initdata = {
 421         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 422           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 423         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 424           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 425         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 426           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 427         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 428           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 429         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 430           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
 431         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 432           { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
 433         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 434           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 435             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 436         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 437           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
 438         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 439           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
 440         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 441           { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
 442         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 443           { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
 444         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 445           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 446 };
 447
 448 static struct intc_prio_reg prio_registers[] __initdata = {
 449         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 450         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 451         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 452         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 453         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
 454         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
 455         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
 456         { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
 457         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 458         { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
 459         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 460           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 461 };
 462
 463 static struct intc_sense_reg sense_registers[] __initdata = {
 464         { 0xa414001c, 16, 2, /* ICR1 */
 465           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 466 };
 467
 468 static struct intc_mask_reg ack_registers[] __initdata = {
 469         { 0xa4140024, 0, 8, /* INTREQ00 */
 470           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 471 };
 472
 473 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
 474                              mask_registers, prio_registers, sense_registers,
 475                              ack_registers);
 476
 477 void __init plat_irq_setup(void)
 478 {
 479         register_intc_controller(&intc_desc);
 480 }