arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/usb/m66592.h>
  17 #include <linux/sh_timer.h>
  18 #include <asm/clock.h>
  19 #include <asm/mmzone.h>
  20 #include <asm/dma-sh.h>
  21 #include <cpu/sh7722.h>
  22
  23 static struct resource rtc_resources[] = {
  24         [0] = {
  25                 .start  = 0xa465fec0,
  26                 .end    = 0xa465fec0 + 0x58 - 1,
  27                 .flags  = IORESOURCE_IO,
  28         },
  29         [1] = {
  30                 /* Period IRQ */
  31                 .start  = 45,
  32                 .flags  = IORESOURCE_IRQ,
  33         },
  34         [2] = {
  35                 /* Carry IRQ */
  36                 .start  = 46,
  37                 .flags  = IORESOURCE_IRQ,
  38         },
  39         [3] = {
  40                 /* Alarm IRQ */
  41                 .start  = 44,
  42                 .flags  = IORESOURCE_IRQ,
  43         },
  44 };
  45
  46 static struct platform_device rtc_device = {
  47         .name           = "sh-rtc",
  48         .id             = -1,
  49         .num_resources  = ARRAY_SIZE(rtc_resources),
  50         .resource       = rtc_resources,
  51         .archdata = {
  52                 .hwblk_id = HWBLK_RTC,
  53         },
  54 };
  55
  56 static struct m66592_platdata usbf_platdata = {
  57         .on_chip = 1,
  58 };
  59
  60 static struct resource usbf_resources[] = {
  61         [0] = {
  62                 .name   = "USBF",
  63                 .start  = 0x04480000,
  64                 .end    = 0x044800FF,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         [1] = {
  68                 .start  = 65,
  69                 .end    = 65,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 static struct platform_device usbf_device = {
  75         .name           = "m66592_udc",
  76         .id             = 0, /* "usbf0" clock */
  77         .dev = {
  78                 .dma_mask               = NULL,
  79                 .coherent_dma_mask      = 0xffffffff,
  80                 .platform_data          = &usbf_platdata,
  81         },
  82         .num_resources  = ARRAY_SIZE(usbf_resources),
  83         .resource       = usbf_resources,
  84         .archdata = {
  85                 .hwblk_id = HWBLK_USBF,
  86         },
  87 };
  88
  89 static struct resource iic_resources[] = {
  90         [0] = {
  91                 .name   = "IIC",
  92                 .start  = 0x04470000,
  93                 .end    = 0x04470017,
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97                 .start  = 96,
  98                 .end    = 99,
  99                 .flags  = IORESOURCE_IRQ,
 100        },
 101 };
 102
 103 static struct platform_device iic_device = {
 104         .name           = "i2c-sh_mobile",
 105         .id             = 0, /* "i2c0" clock */
 106         .num_resources  = ARRAY_SIZE(iic_resources),
 107         .resource       = iic_resources,
 108         .archdata = {
 109                 .hwblk_id = HWBLK_IIC,
 110         },
 111 };
 112
 113 static struct uio_info vpu_platform_data = {
 114         .name = "VPU4",
 115         .version = "0",
 116         .irq = 60,
 117 };
 118
 119 static struct resource vpu_resources[] = {
 120         [0] = {
 121                 .name   = "VPU",
 122                 .start  = 0xfe900000,
 123                 .end    = 0xfe9022eb,
 124                 .flags  = IORESOURCE_MEM,
 125         },
 126         [1] = {
 127                 /* place holder for contiguous memory */
 128         },
 129 };
 130
 131 static struct platform_device vpu_device = {
 132         .name           = "uio_pdrv_genirq",
 133         .id             = 0,
 134         .dev = {
 135                 .platform_data  = &vpu_platform_data,
 136         },
 137         .resource       = vpu_resources,
 138         .num_resources  = ARRAY_SIZE(vpu_resources),
 139         .archdata = {
 140                 .hwblk_id = HWBLK_VPU,
 141         },
 142 };
 143
 144 static struct uio_info veu_platform_data = {
 145         .name = "VEU",
 146         .version = "0",
 147         .irq = 54,
 148 };
 149
 150 static struct resource veu_resources[] = {
 151         [0] = {
 152                 .name   = "VEU",
 153                 .start  = 0xfe920000,
 154                 .end    = 0xfe9200b7,
 155                 .flags  = IORESOURCE_MEM,
 156         },
 157         [1] = {
 158                 /* place holder for contiguous memory */
 159         },
 160 };
 161
 162 static struct platform_device veu_device = {
 163         .name           = "uio_pdrv_genirq",
 164         .id             = 1,
 165         .dev = {
 166                 .platform_data  = &veu_platform_data,
 167         },
 168         .resource       = veu_resources,
 169         .num_resources  = ARRAY_SIZE(veu_resources),
 170         .archdata = {
 171                 .hwblk_id = HWBLK_VEU,
 172         },
 173 };
 174
 175 static struct uio_info jpu_platform_data = {
 176         .name = "JPU",
 177         .version = "0",
 178         .irq = 27,
 179 };
 180
 181 static struct resource jpu_resources[] = {
 182         [0] = {
 183                 .name   = "JPU",
 184                 .start  = 0xfea00000,
 185                 .end    = 0xfea102d3,
 186                 .flags  = IORESOURCE_MEM,
 187         },
 188         [1] = {
 189                 /* place holder for contiguous memory */
 190         },
 191 };
 192
 193 static struct platform_device jpu_device = {
 194         .name           = "uio_pdrv_genirq",
 195         .id             = 2,
 196         .dev = {
 197                 .platform_data  = &jpu_platform_data,
 198         },
 199         .resource       = jpu_resources,
 200         .num_resources  = ARRAY_SIZE(jpu_resources),
 201         .archdata = {
 202                 .hwblk_id = HWBLK_JPU,
 203         },
 204 };
 205
 206 static struct sh_timer_config cmt_platform_data = {
 207         .name = "CMT",
 208         .channel_offset = 0x60,
 209         .timer_bit = 5,
 210         .clk = "cmt0",
 211         .clockevent_rating = 125,
 212         .clocksource_rating = 125,
 213 };
 214
 215 static struct resource cmt_resources[] = {
 216         [0] = {
 217                 .name   = "CMT",
 218                 .start  = 0x044a0060,
 219                 .end    = 0x044a006b,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = 104,
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device cmt_device = {
 229         .name           = "sh_cmt",
 230         .id             = 0,
 231         .dev = {
 232                 .platform_data  = &cmt_platform_data,
 233         },
 234         .resource       = cmt_resources,
 235         .num_resources  = ARRAY_SIZE(cmt_resources),
 236         .archdata = {
 237                 .hwblk_id = HWBLK_CMT,
 238         },
 239 };
 240
 241 static struct sh_timer_config tmu0_platform_data = {
 242         .name = "TMU0",
 243         .channel_offset = 0x04,
 244         .timer_bit = 0,
 245         .clk = "tmu0",
 246         .clockevent_rating = 200,
 247 };
 248
 249 static struct resource tmu0_resources[] = {
 250         [0] = {
 251                 .name   = "TMU0",
 252                 .start  = 0xffd80008,
 253                 .end    = 0xffd80013,
 254                 .flags  = IORESOURCE_MEM,
 255         },
 256         [1] = {
 257                 .start  = 16,
 258                 .flags  = IORESOURCE_IRQ,
 259         },
 260 };
 261
 262 static struct platform_device tmu0_device = {
 263         .name           = "sh_tmu",
 264         .id             = 0,
 265         .dev = {
 266                 .platform_data  = &tmu0_platform_data,
 267         },
 268         .resource       = tmu0_resources,
 269         .num_resources  = ARRAY_SIZE(tmu0_resources),
 270         .archdata = {
 271                 .hwblk_id = HWBLK_TMU,
 272         },
 273 };
 274
 275 static struct sh_timer_config tmu1_platform_data = {
 276         .name = "TMU1",
 277         .channel_offset = 0x10,
 278         .timer_bit = 1,
 279         .clk = "tmu0",
 280         .clocksource_rating = 200,
 281 };
 282
 283 static struct resource tmu1_resources[] = {
 284         [0] = {
 285                 .name   = "TMU1",
 286                 .start  = 0xffd80014,
 287                 .end    = 0xffd8001f,
 288                 .flags  = IORESOURCE_MEM,
 289         },
 290         [1] = {
 291                 .start  = 17,
 292                 .flags  = IORESOURCE_IRQ,
 293         },
 294 };
 295
 296 static struct platform_device tmu1_device = {
 297         .name           = "sh_tmu",
 298         .id             = 1,
 299         .dev = {
 300                 .platform_data  = &tmu1_platform_data,
 301         },
 302         .resource       = tmu1_resources,
 303         .num_resources  = ARRAY_SIZE(tmu1_resources),
 304         .archdata = {
 305                 .hwblk_id = HWBLK_TMU,
 306         },
 307 };
 308
 309 static struct sh_timer_config tmu2_platform_data = {
 310         .name = "TMU2",
 311         .channel_offset = 0x1c,
 312         .timer_bit = 2,
 313         .clk = "tmu0",
 314 };
 315
 316 static struct resource tmu2_resources[] = {
 317         [0] = {
 318                 .name   = "TMU2",
 319                 .start  = 0xffd80020,
 320                 .end    = 0xffd8002b,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = 18,
 325                 .flags  = IORESOURCE_IRQ,
 326         },
 327 };
 328
 329 static struct platform_device tmu2_device = {
 330         .name           = "sh_tmu",
 331         .id             = 2,
 332         .dev = {
 333                 .platform_data  = &tmu2_platform_data,
 334         },
 335         .resource       = tmu2_resources,
 336         .num_resources  = ARRAY_SIZE(tmu2_resources),
 337         .archdata = {
 338                 .hwblk_id = HWBLK_TMU,
 339         },
 340 };
 341
 342 static struct plat_sci_port sci_platform_data[] = {
 343         {
 344                 .mapbase        = 0xffe00000,
 345                 .flags          = UPF_BOOT_AUTOCONF,
 346                 .type           = PORT_SCIF,
 347                 .irqs           = { 80, 80, 80, 80 },
 348                 .clk            = "scif0",
 349         },
 350         {
 351                 .mapbase        = 0xffe10000,
 352                 .flags          = UPF_BOOT_AUTOCONF,
 353                 .type           = PORT_SCIF,
 354                 .irqs           = { 81, 81, 81, 81 },
 355                 .clk            = "scif1",
 356         },
 357         {
 358                 .mapbase        = 0xffe20000,
 359                 .flags          = UPF_BOOT_AUTOCONF,
 360                 .type           = PORT_SCIF,
 361                 .irqs           = { 82, 82, 82, 82 },
 362                 .clk            = "scif2",
 363         },
 364         {
 365                 .flags = 0,
 366         }
 367 };
 368
 369 static struct platform_device sci_device = {
 370         .name           = "sh-sci",
 371         .id             = -1,
 372         .dev            = {
 373                 .platform_data  = sci_platform_data,
 374         },
 375 };
 376
 377 static struct sh_dmae_pdata dma_platform_data = {
 378         .mode = 0,
 379 };
 380
 381 static struct platform_device dma_device = {
 382         .name           = "sh-dma-engine",
 383         .id             = -1,
 384         .dev            = {
 385                 .platform_data  = &dma_platform_data,
 386         },
 387 };
 388
 389 static struct platform_device *sh7722_devices[] __initdata = {
 390         &cmt_device,
 391         &tmu0_device,
 392         &tmu1_device,
 393         &tmu2_device,
 394         &rtc_device,
 395         &usbf_device,
 396         &iic_device,
 397         &sci_device,
 398         &vpu_device,
 399         &veu_device,
 400         &jpu_device,
 401         &dma_device,
 402 };
 403
 404 static int __init sh7722_devices_setup(void)
 405 {
 406         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 407         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 408         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 409
 410         return platform_add_devices(sh7722_devices,
 411                                     ARRAY_SIZE(sh7722_devices));
 412 }
 413 arch_initcall(sh7722_devices_setup);
 414
 415 static struct platform_device *sh7722_early_devices[] __initdata = {
 416         &cmt_device,
 417         &tmu0_device,
 418         &tmu1_device,
 419         &tmu2_device,
 420 };
 421
 422 void __init plat_early_device_setup(void)
 423 {
 424         early_platform_add_devices(sh7722_early_devices,
 425                                    ARRAY_SIZE(sh7722_early_devices));
 426 }
 427
 428 enum {
 429         UNUSED=0,
 430
 431         /* interrupt sources */
 432         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 433         HUDI,
 434         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 435         RTC_ATI, RTC_PRI, RTC_CUI,
 436         DMAC0, DMAC1, DMAC2, DMAC3,
 437         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 438         VPU, TPU,
 439         USB_USBI0, USB_USBI1,
 440         DMAC4, DMAC5, DMAC_DADERR,
 441         KEYSC,
 442         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 443         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 444         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 445         SDHI0, SDHI1, SDHI2, SDHI3,
 446         CMT, TSIF, SIU, TWODG,
 447         TMU0, TMU1, TMU2,
 448         IRDA, JPU, LCDC,
 449
 450         /* interrupt groups */
 451         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 452 };
 453
 454 static struct intc_vect vectors[] __initdata = {
 455         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 456         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 457         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 458         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 459         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 460         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 461         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 462         INTC_VECT(RTC_CUI, 0x7c0),
 463         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 464         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 465         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 466         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 467         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 468         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 469         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 470         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 471         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 472         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 473         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 474         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 475         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 476         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 477         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 478         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 479         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 480         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 481         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 482         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 483         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 484         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 485 };
 486
 487 static struct intc_group groups[] __initdata = {
 488         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 489         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 490         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 491         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 492         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 493         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 494         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 495                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 496         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 497         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 498 };
 499
 500 static struct intc_mask_reg mask_registers[] __initdata = {
 501         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 502           { } },
 503         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 504           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 505         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 506           { 0, 0, 0, VPU, } },
 507         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 508           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 509         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 510           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 511         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 512           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 513         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 514           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 515         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 516           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 517             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 518         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 519           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
 520         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 521           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 522         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 523           { } },
 524         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 525           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 526         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 527           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 528 };
 529
 530 static struct intc_prio_reg prio_registers[] __initdata = {
 531         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 532         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 533         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 534         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 535         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 536         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 537         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 538         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 539         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 540         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 541         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 542         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 543         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 544           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 545 };
 546
 547 static struct intc_sense_reg sense_registers[] __initdata = {
 548         { 0xa414001c, 16, 2, /* ICR1 */
 549           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 550 };
 551
 552 static struct intc_mask_reg ack_registers[] __initdata = {
 553         { 0xa4140024, 0, 8, /* INTREQ00 */
 554           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 555 };
 556
 557 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
 558                              mask_registers, prio_registers, sense_registers,
 559                              ack_registers);
 560
 561 void __init plat_irq_setup(void)
 562 {
 563         register_intc_controller(&intc_desc);
 564 }
 565
 566 void __init plat_mem_setup(void)
 567 {
 568         /* Register the URAM space as Node 1 */
 569         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 570 }