[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / isdn / hisax / s0box.c
blob16d00b555c8cfa986dfa24776acc0a9dcdf92b1f
1 /* $Id: s0box.c,v 2.6.2.4 2004/01/13 23:48:39 keil Exp $
3 * low level stuff for Creatix S0BOX
5 * Author Enrik Berkhan
6 * Copyright by Enrik Berkhan <enrik@starfleet.inka.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
14 #include "hisax.h"
15 #include "isac.h"
16 #include "hscx.h"
17 #include "isdnl1.h"
19 static const char *s0box_revision = "$Revision: 2.6.2.4 $";
21 static inline void
22 writereg(unsigned int padr, signed int addr, u_char off, u_char val) {
23 outb_p(0x1c,padr+2);
24 outb_p(0x14,padr+2);
25 outb_p((addr+off)&0x7f,padr);
26 outb_p(0x16,padr+2);
27 outb_p(val,padr);
28 outb_p(0x17,padr+2);
29 outb_p(0x14,padr+2);
30 outb_p(0x1c,padr+2);
33 static u_char nibtab[] = { 1, 9, 5, 0xd, 3, 0xb, 7, 0xf,
34 0, 0, 0, 0, 0, 0, 0, 0,
35 0, 8, 4, 0xc, 2, 0xa, 6, 0xe } ;
37 static inline u_char
38 readreg(unsigned int padr, signed int addr, u_char off) {
39 register u_char n1, n2;
41 outb_p(0x1c,padr+2);
42 outb_p(0x14,padr+2);
43 outb_p((addr+off)|0x80,padr);
44 outb_p(0x16,padr+2);
45 outb_p(0x17,padr+2);
46 n1 = (inb_p(padr+1) >> 3) & 0x17;
47 outb_p(0x16,padr+2);
48 n2 = (inb_p(padr+1) >> 3) & 0x17;
49 outb_p(0x14,padr+2);
50 outb_p(0x1c,padr+2);
51 return nibtab[n1] | (nibtab[n2] << 4);
54 static inline void
55 read_fifo(unsigned int padr, signed int adr, u_char * data, int size)
57 int i;
58 register u_char n1, n2;
60 outb_p(0x1c, padr+2);
61 outb_p(0x14, padr+2);
62 outb_p(adr|0x80, padr);
63 outb_p(0x16, padr+2);
64 for (i=0; i<size; i++) {
65 outb_p(0x17, padr+2);
66 n1 = (inb_p(padr+1) >> 3) & 0x17;
67 outb_p(0x16,padr+2);
68 n2 = (inb_p(padr+1) >> 3) & 0x17;
69 *(data++)=nibtab[n1] | (nibtab[n2] << 4);
71 outb_p(0x14,padr+2);
72 outb_p(0x1c,padr+2);
73 return;
76 static inline void
77 write_fifo(unsigned int padr, signed int adr, u_char * data, int size)
79 int i;
80 outb_p(0x1c, padr+2);
81 outb_p(0x14, padr+2);
82 outb_p(adr&0x7f, padr);
83 for (i=0; i<size; i++) {
84 outb_p(0x16, padr+2);
85 outb_p(*(data++), padr);
86 outb_p(0x17, padr+2);
88 outb_p(0x14,padr+2);
89 outb_p(0x1c,padr+2);
90 return;
93 /* Interface functions */
95 static u_char
96 ReadISAC(struct IsdnCardState *cs, u_char offset)
98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset));
101 static void
102 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value);
107 static void
108 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
113 static void
114 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size);
119 static u_char
120 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset));
125 static void
126 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value);
132 * fast interrupt HSCX stuff goes here
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
140 #include "hscx_irq.c"
142 static irqreturn_t
143 s0box_interrupt(int intno, void *dev_id)
145 #define MAXCOUNT 5
146 struct IsdnCardState *cs = dev_id;
147 u_char val;
148 u_long flags;
149 int count = 0;
151 spin_lock_irqsave(&cs->lock, flags);
152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA);
153 Start_HSCX:
154 if (val)
155 hscx_int_main(cs, val);
156 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA);
157 Start_ISAC:
158 if (val)
159 isac_interrupt(cs, val);
160 count++;
161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA);
162 if (val && count < MAXCOUNT) {
163 if (cs->debug & L1_DEB_HSCX)
164 debugl1(cs, "HSCX IntStat after IntRoutine");
165 goto Start_HSCX;
167 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA);
168 if (val && count < MAXCOUNT) {
169 if (cs->debug & L1_DEB_ISAC)
170 debugl1(cs, "ISAC IntStat after IntRoutine");
171 goto Start_ISAC;
173 if (count >= MAXCOUNT)
174 printk(KERN_WARNING "S0Box: more than %d loops in s0box_interrupt\n", count);
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF);
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF);
177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF);
178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0);
179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0);
180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0);
181 spin_unlock_irqrestore(&cs->lock, flags);
182 return IRQ_HANDLED;
185 static void
186 release_io_s0box(struct IsdnCardState *cs)
188 release_region(cs->hw.teles3.cfg_reg, 8);
191 static int
192 S0Box_card_msg(struct IsdnCardState *cs, int mt, void *arg)
194 u_long flags;
196 switch (mt) {
197 case CARD_RESET:
198 break;
199 case CARD_RELEASE:
200 release_io_s0box(cs);
201 break;
202 case CARD_INIT:
203 spin_lock_irqsave(&cs->lock, flags);
204 inithscxisac(cs, 3);
205 spin_unlock_irqrestore(&cs->lock, flags);
206 break;
207 case CARD_TEST:
208 break;
210 return(0);
213 int __devinit
214 setup_s0box(struct IsdnCard *card)
216 struct IsdnCardState *cs = card->cs;
217 char tmp[64];
219 strcpy(tmp, s0box_revision);
220 printk(KERN_INFO "HiSax: S0Box IO driver Rev. %s\n", HiSax_getrev(tmp));
221 if (cs->typ != ISDN_CTYPE_S0BOX)
222 return (0);
224 cs->hw.teles3.cfg_reg = card->para[1];
225 cs->hw.teles3.hscx[0] = -0x20;
226 cs->hw.teles3.hscx[1] = 0x0;
227 cs->hw.teles3.isac = 0x20;
228 cs->hw.teles3.isacfifo = cs->hw.teles3.isac + 0x3e;
229 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e;
230 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e;
231 cs->irq = card->para[0];
232 if (!request_region(cs->hw.teles3.cfg_reg,8, "S0Box parallel I/O")) {
233 printk(KERN_WARNING "HiSax: S0Box ports %x-%x already in use\n",
234 cs->hw.teles3.cfg_reg,
235 cs->hw.teles3.cfg_reg + 7);
236 return 0;
238 printk(KERN_INFO "HiSax: S0Box config irq:%d isac:0x%x cfg:0x%x\n",
239 cs->irq,
240 cs->hw.teles3.isac, cs->hw.teles3.cfg_reg);
241 printk(KERN_INFO "HiSax: hscx A:0x%x hscx B:0x%x\n",
242 cs->hw.teles3.hscx[0], cs->hw.teles3.hscx[1]);
243 setup_isac(cs);
244 cs->readisac = &ReadISAC;
245 cs->writeisac = &WriteISAC;
246 cs->readisacfifo = &ReadISACfifo;
247 cs->writeisacfifo = &WriteISACfifo;
248 cs->BC_Read_Reg = &ReadHSCX;
249 cs->BC_Write_Reg = &WriteHSCX;
250 cs->BC_Send_Data = &hscx_fill_fifo;
251 cs->cardmsg = &S0Box_card_msg;
252 cs->irq_func = &s0box_interrupt;
253 ISACVersion(cs, "S0Box:");
254 if (HscxVersion(cs, "S0Box:")) {
255 printk(KERN_WARNING
256 "S0Box: wrong HSCX versions check IO address\n");
257 release_io_s0box(cs);
258 return (0);
260 return (1);