drivers/media/dvb/frontends/zl10036.c

   1 /**
   2  * Driver for Zarlink zl10036 DVB-S silicon tuner
   3  *
   4  * Copyright (C) 2006 Tino Reichardt
   5  * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License Version 2, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  **
  21  * The data sheet for this tuner can be found at:
  22  *    http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf
  23  *
  24  * This one is working: (at my Avermedia DVB-S Pro)
  25  * - zl10036 (40pin, FTA)
  26  *
  27  * A driver for zl10038 should be very similar.
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/dvb/frontend.h>
  32 #include <linux/types.h>
  33
  34 #include "zl10036.h"
  35
  36 static int zl10036_debug;
  37 #define dprintk(level, args...) \
  38         do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \
  39         } while (0)
  40
  41 #define deb_info(args...)  dprintk(0x01, args)
  42 #define deb_i2c(args...)  dprintk(0x02, args)
  43
  44 struct zl10036_state {
  45         struct i2c_adapter *i2c;
  46         const struct zl10036_config *config;
  47         u32 frequency;
  48         u8 br, bf;
  49 };
  50
  51
  52 /* This driver assumes the tuner is driven by a 10.111MHz Cristal */
  53 #define _XTAL 10111
  54
  55 /* Some of the possible dividers:
  56  *   64, (write 0x05 to reg), freq step size   158kHz
  57  *   10, (write 0x0a to reg), freq step size 1.011kHz (used here)
  58  *    5, (write 0x09 to reg), freq step size 2.022kHz
  59  */
  60
  61 #define _RDIV 10
  62 #define _RDIV_REG 0x0a
  63 #define _FR   (_XTAL/_RDIV)
  64
  65 #define STATUS_POR 0x80 /* Power on Reset */
  66 #define STATUS_FL  0x40 /* Frequency & Phase Lock */
  67
  68 /* read/write for zl10036 and zl10038 */
  69
  70 static int zl10036_read_status_reg(struct zl10036_state *state)
  71 {
  72         u8 status;
  73         struct i2c_msg msg[1] = {
  74                 { .addr = state->config->tuner_address, .flags = I2C_M_RD,
  75                   .buf = &status, .len = sizeof(status) },
  76         };
  77
  78         if (i2c_transfer(state->i2c, msg, 1) != 1) {
  79                 printk(KERN_ERR "%s: i2c read failed at addr=%02x\n",
  80                         __func__, state->config->tuner_address);
  81                 return -EIO;
  82         }
  83
  84         deb_i2c("R(status): %02x  [FL=%d]\n", status,
  85                 (status & STATUS_FL) ? 1 : 0);
  86         if (status & STATUS_POR)
  87                 deb_info("%s: Power-On-Reset bit enabled - "
  88                         "need to initialize the tuner\n", __func__);
  89
  90         return status;
  91 }
  92
  93 static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count)
  94 {
  95         struct i2c_msg msg[1] = {
  96                 { .addr = state->config->tuner_address, .flags = 0,
  97                   .buf = buf, .len = count },
  98         };
  99         u8 reg = 0;
 100         int ret;
 101
 102         if (zl10036_debug & 0x02) {
 103                 /* every 8bit-value satisifes this!
 104                  * so only check for debug log */
 105                 if ((buf[0] & 0x80) == 0x00)
 106                         reg = 2;
 107                 else if ((buf[0] & 0xc0) == 0x80)
 108                         reg = 4;
 109                 else if ((buf[0] & 0xf0) == 0xc0)
 110                         reg = 6;
 111                 else if ((buf[0] & 0xf0) == 0xd0)
 112                         reg = 8;
 113                 else if ((buf[0] & 0xf0) == 0xe0)
 114                         reg = 10;
 115                 else if ((buf[0] & 0xf0) == 0xf0)
 116                         reg = 12;
 117
 118                 deb_i2c("W(%d):", reg);
 119                 {
 120                         int i;
 121                         for (i = 0; i < count; i++)
 122                                 printk(KERN_CONT " %02x", buf[i]);
 123                         printk(KERN_CONT "\n");
 124                 }
 125         }
 126
 127         ret = i2c_transfer(state->i2c, msg, 1);
 128         if (ret != 1) {
 129                 printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret);
 130                 return -EIO;
 131         }
 132
 133         return 0;
 134 }
 135
 136 static int zl10036_release(struct dvb_frontend *fe)
 137 {
 138         struct zl10036_state *state = fe->tuner_priv;
 139
 140         fe->tuner_priv = NULL;
 141         kfree(state);
 142
 143         return 0;
 144 }
 145
 146 static int zl10036_sleep(struct dvb_frontend *fe)
 147 {
 148         struct zl10036_state *state = fe->tuner_priv;
 149         u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */
 150         int ret;
 151
 152         deb_info("%s\n", __func__);
 153
 154         if (fe->ops.i2c_gate_ctrl)
 155                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 156
 157         ret = zl10036_write(state, buf, sizeof(buf));
 158
 159         if (fe->ops.i2c_gate_ctrl)
 160                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 161
 162         return ret;
 163 }
 164
 165 /**
 166  * register map of the ZL10036/ZL10038
 167  *
 168  * reg[default] content
 169  *  2[0x00]:   0 | N14 | N13 | N12 | N11 | N10 |  N9 |  N8
 170  *  3[0x00]:  N7 |  N6 |  N5 |  N4 |  N3 |  N2 |  N1 |  N0
 171  *  4[0x80]:   1 |   0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN
 172  *  5[0x00]:  P0 |  C1 |  C0 |  R4 |  R3 |  R2 |  R1 |  R0
 173  *  6[0xc0]:   1 |   1 |   0 |   0 | RSD |   0 |   0 |   0
 174  *  7[0x20]:  P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 |   0
 175  *  8[0xdb]:   1 |   1 |   0 |   1 |   0 |  CC |   1 |   1
 176  *  9[0x30]: VSD |  V2 |  V1 |  V0 |  S3 |  S2 |  S1 |  S0
 177  * 10[0xe1]:   1 |   1 |   1 |   0 |   0 | LS2 | LS1 | LS0
 178  * 11[0xf5]:  WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE
 179  * 12[0xf0]:   1 |   1 |   1 |   1 |   0 |   0 |   0 |   0
 180  * 13[0x28]:  PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR |  TL
 181  */
 182
 183 static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency)
 184 {
 185         u8 buf[2];
 186         u32 div, foffset;
 187
 188         div = (frequency + _FR/2) / _FR;
 189         state->frequency = div * _FR;
 190
 191         foffset = frequency - state->frequency;
 192
 193         buf[0] = (div >> 8) & 0x7f;
 194         buf[1] = (div >> 0) & 0xff;
 195
 196         deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__,
 197                 frequency, state->frequency, foffset, div);
 198
 199         return zl10036_write(state, buf, sizeof(buf));
 200 }
 201
 202 static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw)
 203 {
 204         /* fbw is measured in kHz */
 205         u8 br, bf;
 206         int ret;
 207         u8 buf_bf[] = {
 208                 0xc0, 0x00, /*   6/7: rsd=0 bf=0 */
 209         };
 210         u8 buf_br[] = {
 211                 0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/
 212         };
 213         u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */
 214
 215         /* ensure correct values */
 216         if (fbw > 35000)
 217                 fbw = 35000;
 218         if (fbw <  8000)
 219                 fbw =  8000;
 220
 221 #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */
 222
 223         /* <= 28,82 MHz */
 224         if (fbw <= 28820) {
 225                 br = _BR_MAXIMUM;
 226         } else {
 227                 /**
 228                  *  f(bw)=34,6MHz f(xtal)=10.111MHz
 229                  *  br = (10111/34600) * 63 * 1/K = 14;
 230                  */
 231                 br = ((_XTAL * 21 * 1000) / (fbw * 419));
 232         }
 233
 234         /* ensure correct values */
 235         if (br < 4)
 236                 br = 4;
 237         if (br > _BR_MAXIMUM)
 238                 br = _BR_MAXIMUM;
 239
 240         /*
 241          * k = 1.257
 242          * bf = fbw/_XTAL * br * k - 1 */
 243
 244         bf = (fbw * br * 1257) / (_XTAL * 1000) - 1;
 245
 246         /* ensure correct values */
 247         if (bf > 62)
 248                 bf = 62;
 249
 250         buf_bf[1] = (bf << 1) & 0x7e;
 251         buf_br[1] = (br << 2) & 0x7c;
 252         deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf);
 253
 254         if (br != state->br) {
 255                 ret = zl10036_write(state, buf_br, sizeof(buf_br));
 256                 if (ret < 0)
 257                         return ret;
 258         }
 259
 260         if (bf != state->bf) {
 261                 ret = zl10036_write(state, buf_bf, sizeof(buf_bf));
 262                 if (ret < 0)
 263                         return ret;
 264
 265                 /* time = br/(32* fxtal) */
 266                 /* minimal sleep time to be calculated
 267                  * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */
 268                 msleep(1);
 269
 270                 ret = zl10036_write(state, zl10036_rsd_off,
 271                         sizeof(zl10036_rsd_off));
 272                 if (ret < 0)
 273                         return ret;
 274         }
 275
 276         state->br = br;
 277         state->bf = bf;
 278
 279         return 0;
 280 }
 281
 282 static int zl10036_set_gain_params(struct zl10036_state *state,
 283         int c)
 284 {
 285         u8 buf[2];
 286         u8 rfg, ba, bg;
 287
 288         /* default values */
 289         rfg = 0; /* enable when using an lna */
 290         ba = 1;
 291         bg = 1;
 292
 293         /* reg 4 */
 294         buf[0] = 0x80 | ((rfg << 5) & 0x20)
 295                 | ((ba  << 3) & 0x18) | ((bg  << 1) & 0x06);
 296
 297         if (!state->config->rf_loop_enable)
 298                 buf[0] |= 0x01;
 299
 300         /* P0=0 */
 301         buf[1] = _RDIV_REG | ((c << 5) & 0x60);
 302
 303         deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg);
 304         return zl10036_write(state, buf, sizeof(buf));
 305 }
 306
 307 static int zl10036_set_params(struct dvb_frontend *fe,
 308                 struct dvb_frontend_parameters *params)
 309 {
 310         struct zl10036_state *state = fe->tuner_priv;
 311         int ret = 0;
 312         u32 frequency = params->frequency;
 313         u32 fbw;
 314         int i;
 315         u8 c;
 316
 317         /* ensure correct values
 318          * maybe redundant as core already checks this */
 319         if ((frequency < fe->ops.info.frequency_min)
 320         ||  (frequency > fe->ops.info.frequency_max))
 321                 return -EINVAL;
 322
 323         /**
 324          * alpha = 1.35 for dvb-s
 325          * fBW = (alpha*symbolrate)/(2*0.8)
 326          * 1.35 / (2*0.8) = 27 / 32
 327          */
 328         fbw = (27 * params->u.qpsk.symbol_rate) / 32;
 329
 330         /* scale to kHz */
 331         fbw /= 1000;
 332
 333         /* Add safe margin of 3MHz */
 334         fbw += 3000;
 335
 336         /* setting the charge pump - guessed values */
 337         if (frequency < 950000)
 338                 return -EINVAL;
 339         else if (frequency < 1250000)
 340                 c = 0;
 341         else if (frequency < 1750000)
 342                 c = 1;
 343         else if (frequency < 2175000)
 344                 c = 2;
 345         else
 346                 return -EINVAL;
 347
 348         if (fe->ops.i2c_gate_ctrl)
 349                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 350
 351         ret = zl10036_set_gain_params(state, c);
 352         if (ret < 0)
 353                 goto error;
 354
 355         ret = zl10036_set_frequency(state, params->frequency);
 356         if (ret < 0)
 357                 goto error;
 358
 359         ret = zl10036_set_bandwidth(state, fbw);
 360         if (ret < 0)
 361                 goto error;
 362
 363         /* wait for tuner lock - no idea if this is really needed */
 364         for (i = 0; i < 20; i++) {
 365                 ret = zl10036_read_status_reg(state);
 366                 if (ret < 0)
 367                         goto error;
 368
 369                 /* check Frequency & Phase Lock Bit */
 370                 if (ret & STATUS_FL)
 371                         break;
 372
 373                 msleep(10);
 374         }
 375
 376 error:
 377         if (fe->ops.i2c_gate_ctrl)
 378                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 379
 380         return ret;
 381 }
 382
 383 static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 384 {
 385         struct zl10036_state *state = fe->tuner_priv;
 386
 387         *frequency = state->frequency;
 388
 389         return 0;
 390 }
 391
 392 static int zl10036_init_regs(struct zl10036_state *state)
 393 {
 394         int ret;
 395         int i;
 396
 397         /* could also be one block from reg 2 to 13 and additional 10/11 */
 398         u8 zl10036_init_tab[][2] = {
 399                 { 0x04, 0x00 },         /*   2/3: div=0x400 - arbitrary value */
 400                 { 0x8b, _RDIV_REG },    /*   4/5: rfg=0 ba=1 bg=1 len=? */
 401                                         /*        p0=0 c=0 r=_RDIV_REG */
 402                 { 0xc0, 0x20 },         /*   6/7: rsd=0 bf=0x10 */
 403                 { 0xd3, 0x40 },         /*   8/9: from datasheet */
 404                 { 0xe3, 0x5b },         /* 10/11: lock window level */
 405                 { 0xf0, 0x28 },         /* 12/13: br=0xa clr=0 tl=0*/
 406                 { 0xe3, 0xf9 },         /* 10/11: unlock window level */
 407         };
 408
 409         /* invalid values to trigger writing */
 410         state->br = 0xff;
 411         state->bf = 0xff;
 412
 413         if (!state->config->rf_loop_enable)
 414                 zl10036_init_tab[1][2] |= 0x01;
 415
 416         deb_info("%s\n", __func__);
 417
 418         for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) {
 419                 ret = zl10036_write(state, zl10036_init_tab[i], 2);
 420                 if (ret < 0)
 421                         return ret;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int zl10036_init(struct dvb_frontend *fe)
 428 {
 429         struct zl10036_state *state = fe->tuner_priv;
 430         int ret = 0;
 431
 432         if (fe->ops.i2c_gate_ctrl)
 433                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 434
 435         ret = zl10036_read_status_reg(state);
 436         if (ret < 0)
 437                 return ret;
 438
 439         /* Only init if Power-on-Reset bit is set? */
 440         ret = zl10036_init_regs(state);
 441
 442         if (fe->ops.i2c_gate_ctrl)
 443                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 444
 445         return ret;
 446 }
 447
 448 static struct dvb_tuner_ops zl10036_tuner_ops = {
 449         .info = {
 450                 .name = "Zarlink ZL10036",
 451                 .frequency_min = 950000,
 452                 .frequency_max = 2175000
 453         },
 454         .init = zl10036_init,
 455         .release = zl10036_release,
 456         .sleep = zl10036_sleep,
 457         .set_params = zl10036_set_params,
 458         .get_frequency = zl10036_get_frequency,
 459 };
 460
 461 struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
 462                                     const struct zl10036_config *config,
 463                                     struct i2c_adapter *i2c)
 464 {
 465         struct zl10036_state *state = NULL;
 466         int ret;
 467
 468         if (NULL == config) {
 469                 printk(KERN_ERR "%s: no config specified", __func__);
 470                 goto error;
 471         }
 472
 473         state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
 474         if (NULL == state)
 475                 return NULL;
 476
 477         state->config = config;
 478         state->i2c = i2c;
 479
 480         if (fe->ops.i2c_gate_ctrl)
 481                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
 482
 483         ret = zl10036_read_status_reg(state);
 484         if (ret < 0) {
 485                 printk(KERN_ERR "%s: No zl10036 found\n", __func__);
 486                 goto error;
 487         }
 488
 489         ret = zl10036_init_regs(state);
 490         if (ret < 0) {
 491                 printk(KERN_ERR "%s: tuner initialization failed\n",
 492                         __func__);
 493                 goto error;
 494         }
 495
 496         if (fe->ops.i2c_gate_ctrl)
 497                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
 498
 499         fe->tuner_priv = state;
 500
 501         memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops,
 502                 sizeof(struct dvb_tuner_ops));
 503         printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n",
 504                 __func__, fe->ops.tuner_ops.info.name, config->tuner_address);
 505
 506         return fe;
 507
 508 error:
 509         zl10036_release(fe);
 510         return NULL;
 511 }
 512 EXPORT_SYMBOL(zl10036_attach);
 513
 514 module_param_named(debug, zl10036_debug, int, 0644);
 515 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 516 MODULE_DESCRIPTION("DVB ZL10036 driver");
 517 MODULE_AUTHOR("Tino Reichardt");
 518 MODULE_AUTHOR("Matthias Schwarzott");
 519 MODULE_LICENSE("GPL");