drivers/net/cxgb3/common.h

   1 /*
   2  * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __CHELSIO_COMMON_H
  33 #define __CHELSIO_COMMON_H
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ctype.h>
  38 #include <linux/delay.h>
  39 #include <linux/init.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mdio.h>
  43 #include "version.h"
  44
  45 #define CH_ERR(adap, fmt, ...)   dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  46 #define CH_WARN(adap, fmt, ...)  dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  47 #define CH_ALERT(adap, fmt, ...) \
  48         dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
  49
  50 /*
  51  * More powerful macro that selectively prints messages based on msg_enable.
  52  * For info and debugging messages.
  53  */
  54 #define CH_MSG(adapter, level, category, fmt, ...) do { \
  55         if ((adapter)->msg_enable & NETIF_MSG_##category) \
  56                 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
  57                            ## __VA_ARGS__); \
  58 } while (0)
  59
  60 #ifdef DEBUG
  61 # define CH_DBG(adapter, category, fmt, ...) \
  62         CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
  63 #else
  64 # define CH_DBG(adapter, category, fmt, ...)
  65 #endif
  66
  67 /* Additional NETIF_MSG_* categories */
  68 #define NETIF_MSG_MMIO 0x8000000
  69
  70 struct t3_rx_mode {
  71         struct net_device *dev;
  72         struct dev_mc_list *mclist;
  73         unsigned int idx;
  74 };
  75
  76 static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev,
  77                                 struct dev_mc_list *mclist)
  78 {
  79         p->dev = dev;
  80         p->mclist = mclist;
  81         p->idx = 0;
  82 }
  83
  84 static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm)
  85 {
  86         u8 *addr = NULL;
  87
  88         if (rm->mclist && rm->idx < rm->dev->mc_count) {
  89                 addr = rm->mclist->dmi_addr;
  90                 rm->mclist = rm->mclist->next;
  91                 rm->idx++;
  92         }
  93         return addr;
  94 }
  95
  96 enum {
  97         MAX_NPORTS = 2,         /* max # of ports */
  98         MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
  99         EEPROMSIZE = 8192,      /* Serial EEPROM size */
 100         SERNUM_LEN     = 16,    /* Serial # length */
 101         RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
 102         TCB_SIZE = 128,         /* TCB size */
 103         NMTUS = 16,             /* size of MTU table */
 104         NCCTRL_WIN = 32,        /* # of congestion control windows */
 105         PROTO_SRAM_LINES = 128, /* size of TP sram */
 106 };
 107
 108 #define MAX_RX_COALESCING_LEN 12288U
 109
 110 enum {
 111         PAUSE_RX = 1 << 0,
 112         PAUSE_TX = 1 << 1,
 113         PAUSE_AUTONEG = 1 << 2
 114 };
 115
 116 enum {
 117         SUPPORTED_IRQ      = 1 << 24
 118 };
 119
 120 enum {                          /* adapter interrupt-maintained statistics */
 121         STAT_ULP_CH0_PBL_OOB,
 122         STAT_ULP_CH1_PBL_OOB,
 123         STAT_PCI_CORR_ECC,
 124
 125         IRQ_NUM_STATS           /* keep last */
 126 };
 127
 128 enum {
 129         TP_VERSION_MAJOR        = 1,
 130         TP_VERSION_MINOR        = 1,
 131         TP_VERSION_MICRO        = 0
 132 };
 133
 134 #define S_TP_VERSION_MAJOR              16
 135 #define M_TP_VERSION_MAJOR              0xFF
 136 #define V_TP_VERSION_MAJOR(x)           ((x) << S_TP_VERSION_MAJOR)
 137 #define G_TP_VERSION_MAJOR(x)           \
 138             (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
 139
 140 #define S_TP_VERSION_MINOR              8
 141 #define M_TP_VERSION_MINOR              0xFF
 142 #define V_TP_VERSION_MINOR(x)           ((x) << S_TP_VERSION_MINOR)
 143 #define G_TP_VERSION_MINOR(x)           \
 144             (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
 145
 146 #define S_TP_VERSION_MICRO              0
 147 #define M_TP_VERSION_MICRO              0xFF
 148 #define V_TP_VERSION_MICRO(x)           ((x) << S_TP_VERSION_MICRO)
 149 #define G_TP_VERSION_MICRO(x)           \
 150             (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
 151
 152 enum {
 153         SGE_QSETS = 8,          /* # of SGE Tx/Rx/RspQ sets */
 154         SGE_RXQ_PER_SET = 2,    /* # of Rx queues per set */
 155         SGE_TXQ_PER_SET = 3     /* # of Tx queues per set */
 156 };
 157
 158 enum sge_context_type {         /* SGE egress context types */
 159         SGE_CNTXT_RDMA = 0,
 160         SGE_CNTXT_ETH = 2,
 161         SGE_CNTXT_OFLD = 4,
 162         SGE_CNTXT_CTRL = 5
 163 };
 164
 165 enum {
 166         AN_PKT_SIZE = 32,       /* async notification packet size */
 167         IMMED_PKT_SIZE = 48     /* packet size for immediate data */
 168 };
 169
 170 struct sg_ent {                 /* SGE scatter/gather entry */
 171         __be32 len[2];
 172         __be64 addr[2];
 173 };
 174
 175 #ifndef SGE_NUM_GENBITS
 176 /* Must be 1 or 2 */
 177 # define SGE_NUM_GENBITS 2
 178 #endif
 179
 180 #define TX_DESC_FLITS 16U
 181 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
 182
 183 struct cphy;
 184 struct adapter;
 185
 186 struct mdio_ops {
 187         int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
 188                     u16 reg_addr);
 189         int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
 190                      u16 reg_addr, u16 val);
 191         unsigned mode_support;
 192 };
 193
 194 struct adapter_info {
 195         unsigned char nports0;        /* # of ports on channel 0 */
 196         unsigned char nports1;        /* # of ports on channel 1 */
 197         unsigned char phy_base_addr;    /* MDIO PHY base address */
 198         unsigned int gpio_out;  /* GPIO output settings */
 199         unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
 200         unsigned long caps;     /* adapter capabilities */
 201         const struct mdio_ops *mdio_ops;        /* MDIO operations */
 202         const char *desc;       /* product description */
 203 };
 204
 205 struct mc5_stats {
 206         unsigned long parity_err;
 207         unsigned long active_rgn_full;
 208         unsigned long nfa_srch_err;
 209         unsigned long unknown_cmd;
 210         unsigned long reqq_parity_err;
 211         unsigned long dispq_parity_err;
 212         unsigned long del_act_empty;
 213 };
 214
 215 struct mc7_stats {
 216         unsigned long corr_err;
 217         unsigned long uncorr_err;
 218         unsigned long parity_err;
 219         unsigned long addr_err;
 220 };
 221
 222 struct mac_stats {
 223         u64 tx_octets;          /* total # of octets in good frames */
 224         u64 tx_octets_bad;      /* total # of octets in error frames */
 225         u64 tx_frames;          /* all good frames */
 226         u64 tx_mcast_frames;    /* good multicast frames */
 227         u64 tx_bcast_frames;    /* good broadcast frames */
 228         u64 tx_pause;           /* # of transmitted pause frames */
 229         u64 tx_deferred;        /* frames with deferred transmissions */
 230         u64 tx_late_collisions; /* # of late collisions */
 231         u64 tx_total_collisions;        /* # of total collisions */
 232         u64 tx_excess_collisions;       /* frame errors from excessive collissions */
 233         u64 tx_underrun;        /* # of Tx FIFO underruns */
 234         u64 tx_len_errs;        /* # of Tx length errors */
 235         u64 tx_mac_internal_errs;       /* # of internal MAC errors on Tx */
 236         u64 tx_excess_deferral; /* # of frames with excessive deferral */
 237         u64 tx_fcs_errs;        /* # of frames with bad FCS */
 238
 239         u64 tx_frames_64;       /* # of Tx frames in a particular range */
 240         u64 tx_frames_65_127;
 241         u64 tx_frames_128_255;
 242         u64 tx_frames_256_511;
 243         u64 tx_frames_512_1023;
 244         u64 tx_frames_1024_1518;
 245         u64 tx_frames_1519_max;
 246
 247         u64 rx_octets;          /* total # of octets in good frames */
 248         u64 rx_octets_bad;      /* total # of octets in error frames */
 249         u64 rx_frames;          /* all good frames */
 250         u64 rx_mcast_frames;    /* good multicast frames */
 251         u64 rx_bcast_frames;    /* good broadcast frames */
 252         u64 rx_pause;           /* # of received pause frames */
 253         u64 rx_fcs_errs;        /* # of received frames with bad FCS */
 254         u64 rx_align_errs;      /* alignment errors */
 255         u64 rx_symbol_errs;     /* symbol errors */
 256         u64 rx_data_errs;       /* data errors */
 257         u64 rx_sequence_errs;   /* sequence errors */
 258         u64 rx_runt;            /* # of runt frames */
 259         u64 rx_jabber;          /* # of jabber frames */
 260         u64 rx_short;           /* # of short frames */
 261         u64 rx_too_long;        /* # of oversized frames */
 262         u64 rx_mac_internal_errs;       /* # of internal MAC errors on Rx */
 263
 264         u64 rx_frames_64;       /* # of Rx frames in a particular range */
 265         u64 rx_frames_65_127;
 266         u64 rx_frames_128_255;
 267         u64 rx_frames_256_511;
 268         u64 rx_frames_512_1023;
 269         u64 rx_frames_1024_1518;
 270         u64 rx_frames_1519_max;
 271
 272         u64 rx_cong_drops;      /* # of Rx drops due to SGE congestion */
 273
 274         unsigned long tx_fifo_parity_err;
 275         unsigned long rx_fifo_parity_err;
 276         unsigned long tx_fifo_urun;
 277         unsigned long rx_fifo_ovfl;
 278         unsigned long serdes_signal_loss;
 279         unsigned long xaui_pcs_ctc_err;
 280         unsigned long xaui_pcs_align_change;
 281
 282         unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
 283         unsigned long num_resets;  /* # times reset due to stuck TX */
 284
 285         unsigned long link_faults;  /* # detected link faults */
 286 };
 287
 288 struct tp_mib_stats {
 289         u32 ipInReceive_hi;
 290         u32 ipInReceive_lo;
 291         u32 ipInHdrErrors_hi;
 292         u32 ipInHdrErrors_lo;
 293         u32 ipInAddrErrors_hi;
 294         u32 ipInAddrErrors_lo;
 295         u32 ipInUnknownProtos_hi;
 296         u32 ipInUnknownProtos_lo;
 297         u32 ipInDiscards_hi;
 298         u32 ipInDiscards_lo;
 299         u32 ipInDelivers_hi;
 300         u32 ipInDelivers_lo;
 301         u32 ipOutRequests_hi;
 302         u32 ipOutRequests_lo;
 303         u32 ipOutDiscards_hi;
 304         u32 ipOutDiscards_lo;
 305         u32 ipOutNoRoutes_hi;
 306         u32 ipOutNoRoutes_lo;
 307         u32 ipReasmTimeout;
 308         u32 ipReasmReqds;
 309         u32 ipReasmOKs;
 310         u32 ipReasmFails;
 311
 312         u32 reserved[8];
 313
 314         u32 tcpActiveOpens;
 315         u32 tcpPassiveOpens;
 316         u32 tcpAttemptFails;
 317         u32 tcpEstabResets;
 318         u32 tcpOutRsts;
 319         u32 tcpCurrEstab;
 320         u32 tcpInSegs_hi;
 321         u32 tcpInSegs_lo;
 322         u32 tcpOutSegs_hi;
 323         u32 tcpOutSegs_lo;
 324         u32 tcpRetransSeg_hi;
 325         u32 tcpRetransSeg_lo;
 326         u32 tcpInErrs_hi;
 327         u32 tcpInErrs_lo;
 328         u32 tcpRtoMin;
 329         u32 tcpRtoMax;
 330 };
 331
 332 struct tp_params {
 333         unsigned int nchan;     /* # of channels */
 334         unsigned int pmrx_size; /* total PMRX capacity */
 335         unsigned int pmtx_size; /* total PMTX capacity */
 336         unsigned int cm_size;   /* total CM capacity */
 337         unsigned int chan_rx_size;      /* per channel Rx size */
 338         unsigned int chan_tx_size;      /* per channel Tx size */
 339         unsigned int rx_pg_size;        /* Rx page size */
 340         unsigned int tx_pg_size;        /* Tx page size */
 341         unsigned int rx_num_pgs;        /* # of Rx pages */
 342         unsigned int tx_num_pgs;        /* # of Tx pages */
 343         unsigned int ntimer_qs; /* # of timer queues */
 344 };
 345
 346 struct qset_params {            /* SGE queue set parameters */
 347         unsigned int polling;   /* polling/interrupt service for rspq */
 348         unsigned int lro;       /* large receive offload */
 349         unsigned int coalesce_usecs;    /* irq coalescing timer */
 350         unsigned int rspq_size; /* # of entries in response queue */
 351         unsigned int fl_size;   /* # of entries in regular free list */
 352         unsigned int jumbo_size;        /* # of entries in jumbo free list */
 353         unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
 354         unsigned int cong_thres;        /* FL congestion threshold */
 355         unsigned int vector;            /* Interrupt (line or vector) number */
 356 };
 357
 358 struct sge_params {
 359         unsigned int max_pkt_size;      /* max offload pkt size */
 360         struct qset_params qset[SGE_QSETS];
 361 };
 362
 363 struct mc5_params {
 364         unsigned int mode;      /* selects MC5 width */
 365         unsigned int nservers;  /* size of server region */
 366         unsigned int nfilters;  /* size of filter region */
 367         unsigned int nroutes;   /* size of routing region */
 368 };
 369
 370 /* Default MC5 region sizes */
 371 enum {
 372         DEFAULT_NSERVERS = 512,
 373         DEFAULT_NFILTERS = 128
 374 };
 375
 376 /* MC5 modes, these must be non-0 */
 377 enum {
 378         MC5_MODE_144_BIT = 1,
 379         MC5_MODE_72_BIT = 2
 380 };
 381
 382 /* MC5 min active region size */
 383 enum { MC5_MIN_TIDS = 16 };
 384
 385 struct vpd_params {
 386         unsigned int cclk;
 387         unsigned int mclk;
 388         unsigned int uclk;
 389         unsigned int mdc;
 390         unsigned int mem_timing;
 391         u8 sn[SERNUM_LEN + 1];
 392         u8 eth_base[6];
 393         u8 port_type[MAX_NPORTS];
 394         unsigned short xauicfg[2];
 395 };
 396
 397 struct pci_params {
 398         unsigned int vpd_cap_addr;
 399         unsigned int pcie_cap_addr;
 400         unsigned short speed;
 401         unsigned char width;
 402         unsigned char variant;
 403 };
 404
 405 enum {
 406         PCI_VARIANT_PCI,
 407         PCI_VARIANT_PCIX_MODE1_PARITY,
 408         PCI_VARIANT_PCIX_MODE1_ECC,
 409         PCI_VARIANT_PCIX_266_MODE2,
 410         PCI_VARIANT_PCIE
 411 };
 412
 413 struct adapter_params {
 414         struct sge_params sge;
 415         struct mc5_params mc5;
 416         struct tp_params tp;
 417         struct vpd_params vpd;
 418         struct pci_params pci;
 419
 420         const struct adapter_info *info;
 421
 422         unsigned short mtus[NMTUS];
 423         unsigned short a_wnd[NCCTRL_WIN];
 424         unsigned short b_wnd[NCCTRL_WIN];
 425
 426         unsigned int nports;    /* # of ethernet ports */
 427         unsigned int chan_map;  /* bitmap of in-use Tx channels */
 428         unsigned int stats_update_period;       /* MAC stats accumulation period */
 429         unsigned int linkpoll_period;   /* link poll period in 0.1s */
 430         unsigned int rev;       /* chip revision */
 431         unsigned int offload;
 432 };
 433
 434 enum {                                      /* chip revisions */
 435         T3_REV_A  = 0,
 436         T3_REV_B  = 2,
 437         T3_REV_B2 = 3,
 438         T3_REV_C  = 4,
 439 };
 440
 441 struct trace_params {
 442         u32 sip;
 443         u32 sip_mask;
 444         u32 dip;
 445         u32 dip_mask;
 446         u16 sport;
 447         u16 sport_mask;
 448         u16 dport;
 449         u16 dport_mask;
 450         u32 vlan:12;
 451         u32 vlan_mask:12;
 452         u32 intf:4;
 453         u32 intf_mask:4;
 454         u8 proto;
 455         u8 proto_mask;
 456 };
 457
 458 struct link_config {
 459         unsigned int supported; /* link capabilities */
 460         unsigned int advertising;       /* advertised capabilities */
 461         unsigned short requested_speed; /* speed user has requested */
 462         unsigned short speed;   /* actual link speed */
 463         unsigned char requested_duplex; /* duplex user has requested */
 464         unsigned char duplex;   /* actual link duplex */
 465         unsigned char requested_fc;     /* flow control user has requested */
 466         unsigned char fc;       /* actual link flow control */
 467         unsigned char autoneg;  /* autonegotiating? */
 468         unsigned int link_ok;   /* link up? */
 469 };
 470
 471 #define SPEED_INVALID   0xffff
 472 #define DUPLEX_INVALID  0xff
 473
 474 struct mc5 {
 475         struct adapter *adapter;
 476         unsigned int tcam_size;
 477         unsigned char part_type;
 478         unsigned char parity_enabled;
 479         unsigned char mode;
 480         struct mc5_stats stats;
 481 };
 482
 483 static inline unsigned int t3_mc5_size(const struct mc5 *p)
 484 {
 485         return p->tcam_size;
 486 }
 487
 488 struct mc7 {
 489         struct adapter *adapter;        /* backpointer to adapter */
 490         unsigned int size;      /* memory size in bytes */
 491         unsigned int width;     /* MC7 interface width */
 492         unsigned int offset;    /* register address offset for MC7 instance */
 493         const char *name;       /* name of MC7 instance */
 494         struct mc7_stats stats; /* MC7 statistics */
 495 };
 496
 497 static inline unsigned int t3_mc7_size(const struct mc7 *p)
 498 {
 499         return p->size;
 500 }
 501
 502 struct cmac {
 503         struct adapter *adapter;
 504         unsigned int offset;
 505         unsigned int nucast;    /* # of address filters for unicast MACs */
 506         unsigned int tx_tcnt;
 507         unsigned int tx_xcnt;
 508         u64 tx_mcnt;
 509         unsigned int rx_xcnt;
 510         unsigned int rx_ocnt;
 511         u64 rx_mcnt;
 512         unsigned int toggle_cnt;
 513         unsigned int txen;
 514         u64 rx_pause;
 515         struct mac_stats stats;
 516 };
 517
 518 enum {
 519         MAC_DIRECTION_RX = 1,
 520         MAC_DIRECTION_TX = 2,
 521         MAC_RXFIFO_SIZE = 32768
 522 };
 523
 524 /* PHY loopback direction */
 525 enum {
 526         PHY_LOOPBACK_TX = 1,
 527         PHY_LOOPBACK_RX = 2
 528 };
 529
 530 /* PHY interrupt types */
 531 enum {
 532         cphy_cause_link_change = 1,
 533         cphy_cause_fifo_error = 2,
 534         cphy_cause_module_change = 4,
 535 };
 536
 537 /* PHY module types */
 538 enum {
 539         phy_modtype_none,
 540         phy_modtype_sr,
 541         phy_modtype_lr,
 542         phy_modtype_lrm,
 543         phy_modtype_twinax,
 544         phy_modtype_twinax_long,
 545         phy_modtype_unknown
 546 };
 547
 548 /* PHY operations */
 549 struct cphy_ops {
 550         int (*reset)(struct cphy *phy, int wait);
 551
 552         int (*intr_enable)(struct cphy *phy);
 553         int (*intr_disable)(struct cphy *phy);
 554         int (*intr_clear)(struct cphy *phy);
 555         int (*intr_handler)(struct cphy *phy);
 556
 557         int (*autoneg_enable)(struct cphy *phy);
 558         int (*autoneg_restart)(struct cphy *phy);
 559
 560         int (*advertise)(struct cphy *phy, unsigned int advertise_map);
 561         int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
 562         int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
 563         int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
 564                                int *duplex, int *fc);
 565         int (*power_down)(struct cphy *phy, int enable);
 566
 567         u32 mmds;
 568 };
 569 enum {
 570         EDC_OPT_AEL2005 = 0,
 571         EDC_OPT_AEL2005_SIZE = 1084,
 572         EDC_TWX_AEL2005 = 1,
 573         EDC_TWX_AEL2005_SIZE = 1464,
 574         EDC_TWX_AEL2020 = 2,
 575         EDC_TWX_AEL2020_SIZE = 1628,
 576         EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */
 577 };
 578
 579 /* A PHY instance */
 580 struct cphy {
 581         u8 modtype;                     /* PHY module type */
 582         short priv;                     /* scratch pad */
 583         unsigned int caps;              /* PHY capabilities */
 584         struct adapter *adapter;        /* associated adapter */
 585         const char *desc;               /* PHY description */
 586         unsigned long fifo_errors;      /* FIFO over/under-flows */
 587         const struct cphy_ops *ops;     /* PHY operations */
 588         struct mdio_if_info mdio;
 589         u16 phy_cache[EDC_MAX_SIZE];    /* EDC cache */
 590 };
 591
 592 /* Convenience MDIO read/write wrappers */
 593 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
 594                                unsigned int *valp)
 595 {
 596         int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
 597         *valp = (rc >= 0) ? rc : -1;
 598         return (rc >= 0) ? 0 : rc;
 599 }
 600
 601 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
 602                                 unsigned int val)
 603 {
 604         return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
 605                                     reg, val);
 606 }
 607
 608 /* Convenience initializer */
 609 static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
 610                              int phy_addr, struct cphy_ops *phy_ops,
 611                              const struct mdio_ops *mdio_ops,
 612                               unsigned int caps, const char *desc)
 613 {
 614         phy->caps = caps;
 615         phy->adapter = adapter;
 616         phy->desc = desc;
 617         phy->ops = phy_ops;
 618         if (mdio_ops) {
 619                 phy->mdio.prtad = phy_addr;
 620                 phy->mdio.mmds = phy_ops->mmds;
 621                 phy->mdio.mode_support = mdio_ops->mode_support;
 622                 phy->mdio.mdio_read = mdio_ops->read;
 623                 phy->mdio.mdio_write = mdio_ops->write;
 624         }
 625 }
 626
 627 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
 628 #define MAC_STATS_ACCUM_SECS 180
 629
 630 #define XGM_REG(reg_addr, idx) \
 631         ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
 632
 633 struct addr_val_pair {
 634         unsigned int reg_addr;
 635         unsigned int val;
 636 };
 637
 638 #include "adapter.h"
 639
 640 #ifndef PCI_VENDOR_ID_CHELSIO
 641 # define PCI_VENDOR_ID_CHELSIO 0x1425
 642 #endif
 643
 644 #define for_each_port(adapter, iter) \
 645         for (iter = 0; iter < (adapter)->params.nports; ++iter)
 646
 647 #define adapter_info(adap) ((adap)->params.info)
 648
 649 static inline int uses_xaui(const struct adapter *adap)
 650 {
 651         return adapter_info(adap)->caps & SUPPORTED_AUI;
 652 }
 653
 654 static inline int is_10G(const struct adapter *adap)
 655 {
 656         return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
 657 }
 658
 659 static inline int is_offload(const struct adapter *adap)
 660 {
 661         return adap->params.offload;
 662 }
 663
 664 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
 665 {
 666         return adap->params.vpd.cclk / 1000;
 667 }
 668
 669 static inline unsigned int is_pcie(const struct adapter *adap)
 670 {
 671         return adap->params.pci.variant == PCI_VARIANT_PCIE;
 672 }
 673
 674 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
 675                       u32 val);
 676 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
 677                    int n, unsigned int offset);
 678 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 679                         int polarity, int attempts, int delay, u32 *valp);
 680 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
 681                                   int polarity, int attempts, int delay)
 682 {
 683         return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
 684                                    delay, NULL);
 685 }
 686 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
 687                         unsigned int set);
 688 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
 689 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
 690 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
 691 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
 692 int t3_phy_lasi_intr_enable(struct cphy *phy);
 693 int t3_phy_lasi_intr_disable(struct cphy *phy);
 694 int t3_phy_lasi_intr_clear(struct cphy *phy);
 695 int t3_phy_lasi_intr_handler(struct cphy *phy);
 696
 697 void t3_intr_enable(struct adapter *adapter);
 698 void t3_intr_disable(struct adapter *adapter);
 699 void t3_intr_clear(struct adapter *adapter);
 700 void t3_xgm_intr_enable(struct adapter *adapter, int idx);
 701 void t3_xgm_intr_disable(struct adapter *adapter, int idx);
 702 void t3_port_intr_enable(struct adapter *adapter, int idx);
 703 void t3_port_intr_disable(struct adapter *adapter, int idx);
 704 void t3_port_intr_clear(struct adapter *adapter, int idx);
 705 int t3_slow_intr_handler(struct adapter *adapter);
 706 int t3_phy_intr_handler(struct adapter *adapter);
 707
 708 void t3_link_changed(struct adapter *adapter, int port_id);
 709 void t3_link_fault(struct adapter *adapter, int port_id);
 710 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
 711 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
 712 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
 713 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
 714 int t3_seeprom_wp(struct adapter *adapter, int enable);
 715 int t3_get_tp_version(struct adapter *adapter, u32 *vers);
 716 int t3_check_tpsram_version(struct adapter *adapter);
 717 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
 718                     unsigned int size);
 719 int t3_set_proto_sram(struct adapter *adap, const u8 *data);
 720 int t3_read_flash(struct adapter *adapter, unsigned int addr,
 721                   unsigned int nwords, u32 *data, int byte_oriented);
 722 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
 723 int t3_get_fw_version(struct adapter *adapter, u32 *vers);
 724 int t3_check_fw_version(struct adapter *adapter);
 725 int t3_init_hw(struct adapter *adapter, u32 fw_params);
 726 void mac_prep(struct cmac *mac, struct adapter *adapter, int index);
 727 void early_hw_init(struct adapter *adapter, const struct adapter_info *ai);
 728 int t3_reset_adapter(struct adapter *adapter);
 729 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
 730                     int reset);
 731 int t3_replay_prep_adapter(struct adapter *adapter);
 732 void t3_led_ready(struct adapter *adapter);
 733 void t3_fatal_err(struct adapter *adapter);
 734 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
 735 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
 736                    const u8 * cpus, const u16 *rspq);
 737 int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map);
 738 int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
 739 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
 740                         unsigned int n, unsigned int *valp);
 741 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
 742                    u64 *buf);
 743
 744 int t3_mac_reset(struct cmac *mac);
 745 void t3b_pcs_reset(struct cmac *mac);
 746 void t3_mac_disable_exact_filters(struct cmac *mac);
 747 void t3_mac_enable_exact_filters(struct cmac *mac);
 748 int t3_mac_enable(struct cmac *mac, int which);
 749 int t3_mac_disable(struct cmac *mac, int which);
 750 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
 751 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
 752 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
 753 int t3_mac_set_num_ucast(struct cmac *mac, int n);
 754 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
 755 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
 756 int t3b2_mac_watchdog_task(struct cmac *mac);
 757
 758 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
 759 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
 760                 unsigned int nroutes);
 761 void t3_mc5_intr_handler(struct mc5 *mc5);
 762 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
 763                       u32 *buf);
 764
 765 int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh);
 766 void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size);
 767 void t3_tp_set_offload_mode(struct adapter *adap, int enable);
 768 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
 769 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
 770                   unsigned short alpha[NCCTRL_WIN],
 771                   unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
 772 void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]);
 773 void t3_get_cong_cntl_tab(struct adapter *adap,
 774                           unsigned short incr[NMTUS][NCCTRL_WIN]);
 775 void t3_config_trace_filter(struct adapter *adapter,
 776                             const struct trace_params *tp, int filter_index,
 777                             int invert, int enable);
 778 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
 779
 780 void t3_sge_prep(struct adapter *adap, struct sge_params *p);
 781 void t3_sge_init(struct adapter *adap, struct sge_params *p);
 782 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
 783                        enum sge_context_type type, int respq, u64 base_addr,
 784                        unsigned int size, unsigned int token, int gen,
 785                        unsigned int cidx);
 786 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
 787                         int gts_enable, u64 base_addr, unsigned int size,
 788                         unsigned int esize, unsigned int cong_thres, int gen,
 789                         unsigned int cidx);
 790 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
 791                          int irq_vec_idx, u64 base_addr, unsigned int size,
 792                          unsigned int fl_thres, int gen, unsigned int cidx);
 793 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
 794                         unsigned int size, int rspq, int ovfl_mode,
 795                         unsigned int credits, unsigned int credit_thres);
 796 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
 797 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
 798 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
 799 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
 800 int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]);
 801 int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]);
 802 int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]);
 803 int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]);
 804 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
 805                       unsigned int credits);
 806
 807 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
 808                         int phy_addr, const struct mdio_ops *mdio_ops);
 809 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
 810                         int phy_addr, const struct mdio_ops *mdio_ops);
 811 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
 812                         int phy_addr, const struct mdio_ops *mdio_ops);
 813 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
 814                         int phy_addr, const struct mdio_ops *mdio_ops);
 815 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
 816                         int phy_addr, const struct mdio_ops *mdio_ops);
 817 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
 818                        const struct mdio_ops *mdio_ops);
 819 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
 820                             int phy_addr, const struct mdio_ops *mdio_ops);
 821 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
 822                             int phy_addr, const struct mdio_ops *mdio_ops);
 823 #endif                          /* __CHELSIO_COMMON_H */