?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / e1000e / 82571.c
blobd1e0563a67dffdb8ad988659bf90b221b2635cc6
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
44 */
45
46 #include <linux/netdevice.h>
47 #include <linux/delay.h>
48 #include <linux/pci.h>
49
50 #include "e1000.h"
51
52 #define ID_LED_RESERVED_F746 0xF746
53 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
54 (ID_LED_OFF1_ON2 << 8) | \
55 (ID_LED_DEF1_DEF2 << 4) | \
56 (ID_LED_DEF1_DEF2))
57
58 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
59
60 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
61
62 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
63 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
64 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
65 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
66 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
67 u16 words, u16 *data);
68 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
69 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
71 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
72 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
73 static s32 e1000_led_on_82574(struct e1000_hw *hw);
74 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
75
76 /**
77 * e1000_init_phy_params_82571 - Init PHY func ptrs.
78 * @hw: pointer to the HW structure
79 *
80 * This is a function pointer entry point called by the api module.
81 **/
82 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
83 {
84 struct e1000_phy_info *phy = &hw->phy;
85 s32 ret_val;
86
87 if (hw->phy.media_type != e1000_media_type_copper) {
88 phy->type = e1000_phy_none;
89 return 0;
90 }
91
92 phy->addr = 1;
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 phy->reset_delay_us = 100;
95
96 switch (hw->mac.type) {
97 case e1000_82571:
98 case e1000_82572:
99 phy->type = e1000_phy_igp_2;
100 break;
101 case e1000_82573:
102 phy->type = e1000_phy_m88;
103 break;
104 case e1000_82574:
105 case e1000_82583:
106 phy->type = e1000_phy_bm;
107 break;
108 default:
109 return -E1000_ERR_PHY;
110 break;
111 }
112
113 /* This can only be done after all function pointers are setup. */
114 ret_val = e1000_get_phy_id_82571(hw);
115
116 /* Verify phy id */
117 switch (hw->mac.type) {
118 case e1000_82571:
119 case e1000_82572:
120 if (phy->id != IGP01E1000_I_PHY_ID)
121 return -E1000_ERR_PHY;
122 break;
123 case e1000_82573:
124 if (phy->id != M88E1111_I_PHY_ID)
125 return -E1000_ERR_PHY;
126 break;
127 case e1000_82574:
128 case e1000_82583:
129 if (phy->id != BME1000_E_PHY_ID_R2)
130 return -E1000_ERR_PHY;
131 break;
132 default:
133 return -E1000_ERR_PHY;
134 break;
135 }
136
137 return 0;
138 }
139
140 /**
141 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
142 * @hw: pointer to the HW structure
143 *
144 * This is a function pointer entry point called by the api module.
145 **/
146 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
147 {
148 struct e1000_nvm_info *nvm = &hw->nvm;
149 u32 eecd = er32(EECD);
150 u16 size;
151
152 nvm->opcode_bits = 8;
153 nvm->delay_usec = 1;
154 switch (nvm->override) {
155 case e1000_nvm_override_spi_large:
156 nvm->page_size = 32;
157 nvm->address_bits = 16;
158 break;
159 case e1000_nvm_override_spi_small:
160 nvm->page_size = 8;
161 nvm->address_bits = 8;
162 break;
163 default:
164 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
165 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
166 break;
167 }
168
169 switch (hw->mac.type) {
170 case e1000_82573:
171 case e1000_82574:
172 case e1000_82583:
173 if (((eecd >> 15) & 0x3) == 0x3) {
174 nvm->type = e1000_nvm_flash_hw;
175 nvm->word_size = 2048;
176 /*
177 * Autonomous Flash update bit must be cleared due
178 * to Flash update issue.
179 */
180 eecd &= ~E1000_EECD_AUPDEN;
181 ew32(EECD, eecd);
182 break;
183 }
184 /* Fall Through */
185 default:
186 nvm->type = e1000_nvm_eeprom_spi;
187 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
188 E1000_EECD_SIZE_EX_SHIFT);
189 /*
190 * Added to a constant, "size" becomes the left-shift value
191 * for setting word_size.
192 */
193 size += NVM_WORD_SIZE_BASE_SHIFT;
194
195 /* EEPROM access above 16k is unsupported */
196 if (size > 14)
197 size = 14;
198 nvm->word_size = 1 << size;
199 break;
200 }
201
202 return 0;
203 }
204
205 /**
206 * e1000_init_mac_params_82571 - Init MAC func ptrs.
207 * @hw: pointer to the HW structure
208 *
209 * This is a function pointer entry point called by the api module.
210 **/
211 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
212 {
213 struct e1000_hw *hw = &adapter->hw;
214 struct e1000_mac_info *mac = &hw->mac;
215 struct e1000_mac_operations *func = &mac->ops;
216 u32 swsm = 0;
217 u32 swsm2 = 0;
218 bool force_clear_smbi = false;
219
220 /* Set media type */
221 switch (adapter->pdev->device) {
222 case E1000_DEV_ID_82571EB_FIBER:
223 case E1000_DEV_ID_82572EI_FIBER:
224 case E1000_DEV_ID_82571EB_QUAD_FIBER:
225 hw->phy.media_type = e1000_media_type_fiber;
226 break;
227 case E1000_DEV_ID_82571EB_SERDES:
228 case E1000_DEV_ID_82572EI_SERDES:
229 case E1000_DEV_ID_82571EB_SERDES_DUAL:
230 case E1000_DEV_ID_82571EB_SERDES_QUAD:
231 hw->phy.media_type = e1000_media_type_internal_serdes;
232 break;
233 default:
234 hw->phy.media_type = e1000_media_type_copper;
235 break;
236 }
237
238 /* Set mta register count */
239 mac->mta_reg_count = 128;
240 /* Set rar entry count */
241 mac->rar_entry_count = E1000_RAR_ENTRIES;
242 /* Set if manageability features are enabled. */
243 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
244
245 /* check for link */
246 switch (hw->phy.media_type) {
247 case e1000_media_type_copper:
248 func->setup_physical_interface = e1000_setup_copper_link_82571;
249 func->check_for_link = e1000e_check_for_copper_link;
250 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
251 break;
252 case e1000_media_type_fiber:
253 func->setup_physical_interface =
254 e1000_setup_fiber_serdes_link_82571;
255 func->check_for_link = e1000e_check_for_fiber_link;
256 func->get_link_up_info =
257 e1000e_get_speed_and_duplex_fiber_serdes;
258 break;
259 case e1000_media_type_internal_serdes:
260 func->setup_physical_interface =
261 e1000_setup_fiber_serdes_link_82571;
262 func->check_for_link = e1000_check_for_serdes_link_82571;
263 func->get_link_up_info =
264 e1000e_get_speed_and_duplex_fiber_serdes;
265 break;
266 default:
267 return -E1000_ERR_CONFIG;
268 break;
269 }
270
271 switch (hw->mac.type) {
272 case e1000_82574:
273 case e1000_82583:
274 func->check_mng_mode = e1000_check_mng_mode_82574;
275 func->led_on = e1000_led_on_82574;
276 break;
277 default:
278 func->check_mng_mode = e1000e_check_mng_mode_generic;
279 func->led_on = e1000e_led_on_generic;
280 break;
281 }
282
283 /*
284 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
285 * first NVM or PHY acess. This should be done for single-port
286 * devices, and for one port only on dual-port devices so that
287 * for those devices we can still use the SMBI lock to synchronize
288 * inter-port accesses to the PHY & NVM.
289 */
290 switch (hw->mac.type) {
291 case e1000_82571:
292 case e1000_82572:
293 swsm2 = er32(SWSM2);
294
295 if (!(swsm2 & E1000_SWSM2_LOCK)) {
296 /* Only do this for the first interface on this card */
297 ew32(SWSM2,
298 swsm2 | E1000_SWSM2_LOCK);
299 force_clear_smbi = true;
300 } else
301 force_clear_smbi = false;
302 break;
303 default:
304 force_clear_smbi = true;
305 break;
306 }
307
308 if (force_clear_smbi) {
309 /* Make sure SWSM.SMBI is clear */
310 swsm = er32(SWSM);
311 if (swsm & E1000_SWSM_SMBI) {
312 /* This bit should not be set on a first interface, and
313 * indicates that the bootagent or EFI code has
314 * improperly left this bit enabled
315 */
316 hw_dbg(hw, "Please update your 82571 Bootagent\n");
317 }
318 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
319 }
320
321 /*
322 * Initialze device specific counter of SMBI acquisition
323 * timeouts.
324 */
325 hw->dev_spec.e82571.smb_counter = 0;
326
327 return 0;
328 }
329
330 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
331 {
332 struct e1000_hw *hw = &adapter->hw;
333 static int global_quad_port_a; /* global port a indication */
334 struct pci_dev *pdev = adapter->pdev;
335 u16 eeprom_data = 0;
336 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
337 s32 rc;
338
339 rc = e1000_init_mac_params_82571(adapter);
340 if (rc)
341 return rc;
342
343 rc = e1000_init_nvm_params_82571(hw);
344 if (rc)
345 return rc;
346
347 rc = e1000_init_phy_params_82571(hw);
348 if (rc)
349 return rc;
350
351 /* tag quad port adapters first, it's used below */
352 switch (pdev->device) {
353 case E1000_DEV_ID_82571EB_QUAD_COPPER:
354 case E1000_DEV_ID_82571EB_QUAD_FIBER:
355 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
356 case E1000_DEV_ID_82571PT_QUAD_COPPER:
357 adapter->flags |= FLAG_IS_QUAD_PORT;
358 /* mark the first port */
359 if (global_quad_port_a == 0)
360 adapter->flags |= FLAG_IS_QUAD_PORT_A;
361 /* Reset for multiple quad port adapters */
362 global_quad_port_a++;
363 if (global_quad_port_a == 4)
364 global_quad_port_a = 0;
365 break;
366 default:
367 break;
368 }
369
370 switch (adapter->hw.mac.type) {
371 case e1000_82571:
372 /* these dual ports don't have WoL on port B at all */
373 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
374 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
375 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
376 (is_port_b))
377 adapter->flags &= ~FLAG_HAS_WOL;
378 /* quad ports only support WoL on port A */
379 if (adapter->flags & FLAG_IS_QUAD_PORT &&
380 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
381 adapter->flags &= ~FLAG_HAS_WOL;
382 /* Does not support WoL on any port */
383 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
384 adapter->flags &= ~FLAG_HAS_WOL;
385 break;
386
387 case e1000_82573:
388 if (pdev->device == E1000_DEV_ID_82573L) {
389 if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
390 &eeprom_data) < 0)
391 break;
392 if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
393 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
394 adapter->max_hw_frame_size = DEFAULT_JUMBO;
395 }
396 }
397 break;
398 default:
399 break;
400 }
401
402 return 0;
403 }
404
405 /**
406 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
407 * @hw: pointer to the HW structure
408 *
409 * Reads the PHY registers and stores the PHY ID and possibly the PHY
410 * revision in the hardware structure.
411 **/
412 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
413 {
414 struct e1000_phy_info *phy = &hw->phy;
415 s32 ret_val;
416 u16 phy_id = 0;
417
418 switch (hw->mac.type) {
419 case e1000_82571:
420 case e1000_82572:
421 /*
422 * The 82571 firmware may still be configuring the PHY.
423 * In this case, we cannot access the PHY until the
424 * configuration is done. So we explicitly set the
425 * PHY ID.
426 */
427 phy->id = IGP01E1000_I_PHY_ID;
428 break;
429 case e1000_82573:
430 return e1000e_get_phy_id(hw);
431 break;
432 case e1000_82574:
433 case e1000_82583:
434 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
435 if (ret_val)
436 return ret_val;
437
438 phy->id = (u32)(phy_id << 16);
439 udelay(20);
440 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
441 if (ret_val)
442 return ret_val;
443
444 phy->id |= (u32)(phy_id);
445 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
446 break;
447 default:
448 return -E1000_ERR_PHY;
449 break;
450 }
451
452 return 0;
453 }
454
455 /**
456 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
457 * @hw: pointer to the HW structure
458 *
459 * Acquire the HW semaphore to access the PHY or NVM
460 **/
461 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
462 {
463 u32 swsm;
464 s32 sw_timeout = hw->nvm.word_size + 1;
465 s32 fw_timeout = hw->nvm.word_size + 1;
466 s32 i = 0;
467
468 /*
469 * If we have timedout 3 times on trying to acquire
470 * the inter-port SMBI semaphore, there is old code
471 * operating on the other port, and it is not
472 * releasing SMBI. Modify the number of times that
473 * we try for the semaphore to interwork with this
474 * older code.
475 */
476 if (hw->dev_spec.e82571.smb_counter > 2)
477 sw_timeout = 1;
478
479 /* Get the SW semaphore */
480 while (i < sw_timeout) {
481 swsm = er32(SWSM);
482 if (!(swsm & E1000_SWSM_SMBI))
483 break;
484
485 udelay(50);
486 i++;
487 }
488
489 if (i == sw_timeout) {
490 hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n");
491 hw->dev_spec.e82571.smb_counter++;
492 }
493 /* Get the FW semaphore. */
494 for (i = 0; i < fw_timeout; i++) {
495 swsm = er32(SWSM);
496 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
497
498 /* Semaphore acquired if bit latched */
499 if (er32(SWSM) & E1000_SWSM_SWESMBI)
500 break;
501
502 udelay(50);
503 }
504
505 if (i == fw_timeout) {
506 /* Release semaphores */
507 e1000_put_hw_semaphore_82571(hw);
508 hw_dbg(hw, "Driver can't access the NVM\n");
509 return -E1000_ERR_NVM;
510 }
511
512 return 0;
513 }
514
515 /**
516 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
517 * @hw: pointer to the HW structure
518 *
519 * Release hardware semaphore used to access the PHY or NVM
520 **/
521 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
522 {
523 u32 swsm;
524
525 swsm = er32(SWSM);
526 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
527 ew32(SWSM, swsm);
528 }
529
530 /**
531 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
532 * @hw: pointer to the HW structure
533 *
534 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
535 * Then for non-82573 hardware, set the EEPROM access request bit and wait
536 * for EEPROM access grant bit. If the access grant bit is not set, release
537 * hardware semaphore.
538 **/
539 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
540 {
541 s32 ret_val;
542
543 ret_val = e1000_get_hw_semaphore_82571(hw);
544 if (ret_val)
545 return ret_val;
546
547 switch (hw->mac.type) {
548 case e1000_82573:
549 case e1000_82574:
550 case e1000_82583:
551 break;
552 default:
553 ret_val = e1000e_acquire_nvm(hw);
554 break;
555 }
556
557 if (ret_val)
558 e1000_put_hw_semaphore_82571(hw);
559
560 return ret_val;
561 }
562
563 /**
564 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
565 * @hw: pointer to the HW structure
566 *
567 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
568 **/
569 static void e1000_release_nvm_82571(struct e1000_hw *hw)
570 {
571 e1000e_release_nvm(hw);
572 e1000_put_hw_semaphore_82571(hw);
573 }
574
575 /**
576 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
577 * @hw: pointer to the HW structure
578 * @offset: offset within the EEPROM to be written to
579 * @words: number of words to write
580 * @data: 16 bit word(s) to be written to the EEPROM
581 *
582 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
583 *
584 * If e1000e_update_nvm_checksum is not called after this function, the
585 * EEPROM will most likely contain an invalid checksum.
586 **/
587 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
588 u16 *data)
589 {
590 s32 ret_val;
591
592 switch (hw->mac.type) {
593 case e1000_82573:
594 case e1000_82574:
595 case e1000_82583:
596 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
597 break;
598 case e1000_82571:
599 case e1000_82572:
600 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
601 break;
602 default:
603 ret_val = -E1000_ERR_NVM;
604 break;
605 }
606
607 return ret_val;
608 }
609
610 /**
611 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
612 * @hw: pointer to the HW structure
613 *
614 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
615 * up to the checksum. Then calculates the EEPROM checksum and writes the
616 * value to the EEPROM.
617 **/
618 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
619 {
620 u32 eecd;
621 s32 ret_val;
622 u16 i;
623
624 ret_val = e1000e_update_nvm_checksum_generic(hw);
625 if (ret_val)
626 return ret_val;
627
628 /*
629 * If our nvm is an EEPROM, then we're done
630 * otherwise, commit the checksum to the flash NVM.
631 */
632 if (hw->nvm.type != e1000_nvm_flash_hw)
633 return ret_val;
634
635 /* Check for pending operations. */
636 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
637 msleep(1);
638 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
639 break;
640 }
641
642 if (i == E1000_FLASH_UPDATES)
643 return -E1000_ERR_NVM;
644
645 /* Reset the firmware if using STM opcode. */
646 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
647 /*
648 * The enabling of and the actual reset must be done
649 * in two write cycles.
650 */
651 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
652 e1e_flush();
653 ew32(HICR, E1000_HICR_FW_RESET);
654 }
655
656 /* Commit the write to flash */
657 eecd = er32(EECD) | E1000_EECD_FLUPD;
658 ew32(EECD, eecd);
659
660 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
661 msleep(1);
662 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
663 break;
664 }
665
666 if (i == E1000_FLASH_UPDATES)
667 return -E1000_ERR_NVM;
668
669 return 0;
670 }
671
672 /**
673 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
674 * @hw: pointer to the HW structure
675 *
676 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
677 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
678 **/
679 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
680 {
681 if (hw->nvm.type == e1000_nvm_flash_hw)
682 e1000_fix_nvm_checksum_82571(hw);
683
684 return e1000e_validate_nvm_checksum_generic(hw);
685 }
686
687 /**
688 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
689 * @hw: pointer to the HW structure
690 * @offset: offset within the EEPROM to be written to
691 * @words: number of words to write
692 * @data: 16 bit word(s) to be written to the EEPROM
693 *
694 * After checking for invalid values, poll the EEPROM to ensure the previous
695 * command has completed before trying to write the next word. After write
696 * poll for completion.
697 *
698 * If e1000e_update_nvm_checksum is not called after this function, the
699 * EEPROM will most likely contain an invalid checksum.
700 **/
701 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
702 u16 words, u16 *data)
703 {
704 struct e1000_nvm_info *nvm = &hw->nvm;
705 u32 i;
706 u32 eewr = 0;
707 s32 ret_val = 0;
708
709 /*
710 * A check for invalid values: offset too large, too many words,
711 * and not enough words.
712 */
713 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
714 (words == 0)) {
715 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
716 return -E1000_ERR_NVM;
717 }
718
719 for (i = 0; i < words; i++) {
720 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
721 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
722 E1000_NVM_RW_REG_START;
723
724 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
725 if (ret_val)
726 break;
727
728 ew32(EEWR, eewr);
729
730 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
731 if (ret_val)
732 break;
733 }
734
735 return ret_val;
736 }
737
738 /**
739 * e1000_get_cfg_done_82571 - Poll for configuration done
740 * @hw: pointer to the HW structure
741 *
742 * Reads the management control register for the config done bit to be set.
743 **/
744 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
745 {
746 s32 timeout = PHY_CFG_TIMEOUT;
747
748 while (timeout) {
749 if (er32(EEMNGCTL) &
750 E1000_NVM_CFG_DONE_PORT_0)
751 break;
752 msleep(1);
753 timeout--;
754 }
755 if (!timeout) {
756 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
757 return -E1000_ERR_RESET;
758 }
759
760 return 0;
761 }
762
763 /**
764 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
765 * @hw: pointer to the HW structure
766 * @active: TRUE to enable LPLU, FALSE to disable
767 *
768 * Sets the LPLU D0 state according to the active flag. When activating LPLU
769 * this function also disables smart speed and vice versa. LPLU will not be
770 * activated unless the device autonegotiation advertisement meets standards
771 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
772 * pointer entry point only called by PHY setup routines.
773 **/
774 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
775 {
776 struct e1000_phy_info *phy = &hw->phy;
777 s32 ret_val;
778 u16 data;
779
780 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
781 if (ret_val)
782 return ret_val;
783
784 if (active) {
785 data |= IGP02E1000_PM_D0_LPLU;
786 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
787 if (ret_val)
788 return ret_val;
789
790 /* When LPLU is enabled, we should disable SmartSpeed */
791 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
792 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
793 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
794 if (ret_val)
795 return ret_val;
796 } else {
797 data &= ~IGP02E1000_PM_D0_LPLU;
798 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
799 /*
800 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
801 * during Dx states where the power conservation is most
802 * important. During driver activity we should enable
803 * SmartSpeed, so performance is maintained.
804 */
805 if (phy->smart_speed == e1000_smart_speed_on) {
806 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
807 &data);
808 if (ret_val)
809 return ret_val;
810
811 data |= IGP01E1000_PSCFR_SMART_SPEED;
812 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
813 data);
814 if (ret_val)
815 return ret_val;
816 } else if (phy->smart_speed == e1000_smart_speed_off) {
817 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
818 &data);
819 if (ret_val)
820 return ret_val;
821
822 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
823 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
824 data);
825 if (ret_val)
826 return ret_val;
827 }
828 }
829
830 return 0;
831 }
832
833 /**
834 * e1000_reset_hw_82571 - Reset hardware
835 * @hw: pointer to the HW structure
836 *
837 * This resets the hardware into a known state. This is a
838 * function pointer entry point called by the api module.
839 **/
840 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
841 {
842 u32 ctrl;
843 u32 extcnf_ctrl;
844 u32 ctrl_ext;
845 u32 icr;
846 s32 ret_val;
847 u16 i = 0;
848
849 /*
850 * Prevent the PCI-E bus from sticking if there is no TLP connection
851 * on the last TLP read/write transaction when MAC is reset.
852 */
853 ret_val = e1000e_disable_pcie_master(hw);
854 if (ret_val)
855 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
856
857 hw_dbg(hw, "Masking off all interrupts\n");
858 ew32(IMC, 0xffffffff);
859
860 ew32(RCTL, 0);
861 ew32(TCTL, E1000_TCTL_PSP);
862 e1e_flush();
863
864 msleep(10);
865
866 /*
867 * Must acquire the MDIO ownership before MAC reset.
868 * Ownership defaults to firmware after a reset.
869 */
870 switch (hw->mac.type) {
871 case e1000_82573:
872 case e1000_82574:
873 case e1000_82583:
874 extcnf_ctrl = er32(EXTCNF_CTRL);
875 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
876
877 do {
878 ew32(EXTCNF_CTRL, extcnf_ctrl);
879 extcnf_ctrl = er32(EXTCNF_CTRL);
880
881 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
882 break;
883
884 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
885
886 msleep(2);
887 i++;
888 } while (i < MDIO_OWNERSHIP_TIMEOUT);
889 break;
890 default:
891 break;
892 }
893
894 ctrl = er32(CTRL);
895
896 hw_dbg(hw, "Issuing a global reset to MAC\n");
897 ew32(CTRL, ctrl | E1000_CTRL_RST);
898
899 if (hw->nvm.type == e1000_nvm_flash_hw) {
900 udelay(10);
901 ctrl_ext = er32(CTRL_EXT);
902 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
903 ew32(CTRL_EXT, ctrl_ext);
904 e1e_flush();
905 }
906
907 ret_val = e1000e_get_auto_rd_done(hw);
908 if (ret_val)
909 /* We don't want to continue accessing MAC registers. */
910 return ret_val;
911
912 /*
913 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
914 * Need to wait for Phy configuration completion before accessing
915 * NVM and Phy.
916 */
917
918 switch (hw->mac.type) {
919 case e1000_82573:
920 case e1000_82574:
921 case e1000_82583:
922 msleep(25);
923 break;
924 default:
925 break;
926 }
927
928 /* Clear any pending interrupt events. */
929 ew32(IMC, 0xffffffff);
930 icr = er32(ICR);
931
932 if (hw->mac.type == e1000_82571 &&
933 hw->dev_spec.e82571.alt_mac_addr_is_present)
934 e1000e_set_laa_state_82571(hw, true);
935
936 /* Reinitialize the 82571 serdes link state machine */
937 if (hw->phy.media_type == e1000_media_type_internal_serdes)
938 hw->mac.serdes_link_state = e1000_serdes_link_down;
939
940 return 0;
941 }
942
943 /**
944 * e1000_init_hw_82571 - Initialize hardware
945 * @hw: pointer to the HW structure
946 *
947 * This inits the hardware readying it for operation.
948 **/
949 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
950 {
951 struct e1000_mac_info *mac = &hw->mac;
952 u32 reg_data;
953 s32 ret_val;
954 u16 i;
955 u16 rar_count = mac->rar_entry_count;
956
957 e1000_initialize_hw_bits_82571(hw);
958
959 /* Initialize identification LED */
960 ret_val = e1000e_id_led_init(hw);
961 if (ret_val) {
962 hw_dbg(hw, "Error initializing identification LED\n");
963 return ret_val;
964 }
965
966 /* Disabling VLAN filtering */
967 hw_dbg(hw, "Initializing the IEEE VLAN\n");
968 e1000e_clear_vfta(hw);
969
970 /* Setup the receive address. */
971 /*
972 * If, however, a locally administered address was assigned to the
973 * 82571, we must reserve a RAR for it to work around an issue where
974 * resetting one port will reload the MAC on the other port.
975 */
976 if (e1000e_get_laa_state_82571(hw))
977 rar_count--;
978 e1000e_init_rx_addrs(hw, rar_count);
979
980 /* Zero out the Multicast HASH table */
981 hw_dbg(hw, "Zeroing the MTA\n");
982 for (i = 0; i < mac->mta_reg_count; i++)
983 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
984
985 /* Setup link and flow control */
986 ret_val = e1000_setup_link_82571(hw);
987
988 /* Set the transmit descriptor write-back policy */
989 reg_data = er32(TXDCTL(0));
990 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
991 E1000_TXDCTL_FULL_TX_DESC_WB |
992 E1000_TXDCTL_COUNT_DESC;
993 ew32(TXDCTL(0), reg_data);
994
995 /* ...for both queues. */
996 switch (mac->type) {
997 case e1000_82573:
998 case e1000_82574:
999 case e1000_82583:
1000 e1000e_enable_tx_pkt_filtering(hw);
1001 reg_data = er32(GCR);
1002 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1003 ew32(GCR, reg_data);
1004 break;
1005 default:
1006 reg_data = er32(TXDCTL(1));
1007 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1008 E1000_TXDCTL_FULL_TX_DESC_WB |
1009 E1000_TXDCTL_COUNT_DESC;
1010 ew32(TXDCTL(1), reg_data);
1011 break;
1012 }
1013
1014 /*
1015 * Clear all of the statistics registers (clear on read). It is
1016 * important that we do this after we have tried to establish link
1017 * because the symbol error count will increment wildly if there
1018 * is no link.
1019 */
1020 e1000_clear_hw_cntrs_82571(hw);
1021
1022 return ret_val;
1023 }
1024
1025 /**
1026 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1027 * @hw: pointer to the HW structure
1028 *
1029 * Initializes required hardware-dependent bits needed for normal operation.
1030 **/
1031 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1032 {
1033 u32 reg;
1034
1035 /* Transmit Descriptor Control 0 */
1036 reg = er32(TXDCTL(0));
1037 reg |= (1 << 22);
1038 ew32(TXDCTL(0), reg);
1039
1040 /* Transmit Descriptor Control 1 */
1041 reg = er32(TXDCTL(1));
1042 reg |= (1 << 22);
1043 ew32(TXDCTL(1), reg);
1044
1045 /* Transmit Arbitration Control 0 */
1046 reg = er32(TARC(0));
1047 reg &= ~(0xF << 27); /* 30:27 */
1048 switch (hw->mac.type) {
1049 case e1000_82571:
1050 case e1000_82572:
1051 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1052 break;
1053 default:
1054 break;
1055 }
1056 ew32(TARC(0), reg);
1057
1058 /* Transmit Arbitration Control 1 */
1059 reg = er32(TARC(1));
1060 switch (hw->mac.type) {
1061 case e1000_82571:
1062 case e1000_82572:
1063 reg &= ~((1 << 29) | (1 << 30));
1064 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1065 if (er32(TCTL) & E1000_TCTL_MULR)
1066 reg &= ~(1 << 28);
1067 else
1068 reg |= (1 << 28);
1069 ew32(TARC(1), reg);
1070 break;
1071 default:
1072 break;
1073 }
1074
1075 /* Device Control */
1076 switch (hw->mac.type) {
1077 case e1000_82573:
1078 case e1000_82574:
1079 case e1000_82583:
1080 reg = er32(CTRL);
1081 reg &= ~(1 << 29);
1082 ew32(CTRL, reg);
1083 break;
1084 default:
1085 break;
1086 }
1087
1088 /* Extended Device Control */
1089 switch (hw->mac.type) {
1090 case e1000_82573:
1091 case e1000_82574:
1092 case e1000_82583:
1093 reg = er32(CTRL_EXT);
1094 reg &= ~(1 << 23);
1095 reg |= (1 << 22);
1096 ew32(CTRL_EXT, reg);
1097 break;
1098 default:
1099 break;
1100 }
1101
1102 if (hw->mac.type == e1000_82571) {
1103 reg = er32(PBA_ECC);
1104 reg |= E1000_PBA_ECC_CORR_EN;
1105 ew32(PBA_ECC, reg);
1106 }
1107 /*
1108 * Workaround for hardware errata.
1109 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1110 */
1111
1112 if ((hw->mac.type == e1000_82571) ||
1113 (hw->mac.type == e1000_82572)) {
1114 reg = er32(CTRL_EXT);
1115 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1116 ew32(CTRL_EXT, reg);
1117 }
1118
1119
1120 /* PCI-Ex Control Registers */
1121 switch (hw->mac.type) {
1122 case e1000_82574:
1123 case e1000_82583:
1124 reg = er32(GCR);
1125 reg |= (1 << 22);
1126 ew32(GCR, reg);
1127
1128 reg = er32(GCR2);
1129 reg |= 1;
1130 ew32(GCR2, reg);
1131 break;
1132 default:
1133 break;
1134 }
1135
1136 return;
1137 }
1138
1139 /**
1140 * e1000e_clear_vfta - Clear VLAN filter table
1141 * @hw: pointer to the HW structure
1142 *
1143 * Clears the register array which contains the VLAN filter table by
1144 * setting all the values to 0.
1145 **/
1146 void e1000e_clear_vfta(struct e1000_hw *hw)
1147 {
1148 u32 offset;
1149 u32 vfta_value = 0;
1150 u32 vfta_offset = 0;
1151 u32 vfta_bit_in_reg = 0;
1152
1153 switch (hw->mac.type) {
1154 case e1000_82573:
1155 case e1000_82574:
1156 case e1000_82583:
1157 if (hw->mng_cookie.vlan_id != 0) {
1158 /*
1159 * The VFTA is a 4096b bit-field, each identifying
1160 * a single VLAN ID. The following operations
1161 * determine which 32b entry (i.e. offset) into the
1162 * array we want to set the VLAN ID (i.e. bit) of
1163 * the manageability unit.
1164 */
1165 vfta_offset = (hw->mng_cookie.vlan_id >>
1166 E1000_VFTA_ENTRY_SHIFT) &
1167 E1000_VFTA_ENTRY_MASK;
1168 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1169 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1170 }
1171 break;
1172 default:
1173 break;
1174 }
1175 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1176 /*
1177 * If the offset we want to clear is the same offset of the
1178 * manageability VLAN ID, then clear all bits except that of
1179 * the manageability unit.
1180 */
1181 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1182 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1183 e1e_flush();
1184 }
1185 }
1186
1187 /**
1188 * e1000_check_mng_mode_82574 - Check manageability is enabled
1189 * @hw: pointer to the HW structure
1190 *
1191 * Reads the NVM Initialization Control Word 2 and returns true
1192 * (>0) if any manageability is enabled, else false (0).
1193 **/
1194 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1195 {
1196 u16 data;
1197
1198 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1199 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1200 }
1201
1202 /**
1203 * e1000_led_on_82574 - Turn LED on
1204 * @hw: pointer to the HW structure
1205 *
1206 * Turn LED on.
1207 **/
1208 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1209 {
1210 u32 ctrl;
1211 u32 i;
1212
1213 ctrl = hw->mac.ledctl_mode2;
1214 if (!(E1000_STATUS_LU & er32(STATUS))) {
1215 /*
1216 * If no link, then turn LED on by setting the invert bit
1217 * for each LED that's "on" (0x0E) in ledctl_mode2.
1218 */
1219 for (i = 0; i < 4; i++)
1220 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1221 E1000_LEDCTL_MODE_LED_ON)
1222 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1223 }
1224 ew32(LEDCTL, ctrl);
1225
1226 return 0;
1227 }
1228
1229 /**
1230 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1231 * @hw: pointer to the HW structure
1232 * @mc_addr_list: array of multicast addresses to program
1233 * @mc_addr_count: number of multicast addresses to program
1234 * @rar_used_count: the first RAR register free to program
1235 * @rar_count: total number of supported Receive Address Registers
1236 *
1237 * Updates the Receive Address Registers and Multicast Table Array.
1238 * The caller must have a packed mc_addr_list of multicast addresses.
1239 * The parameter rar_count will usually be hw->mac.rar_entry_count
1240 * unless there are workarounds that change this.
1241 **/
1242 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1243 u8 *mc_addr_list,
1244 u32 mc_addr_count,
1245 u32 rar_used_count,
1246 u32 rar_count)
1247 {
1248 if (e1000e_get_laa_state_82571(hw))
1249 rar_count--;
1250
1251 e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1252 rar_used_count, rar_count);
1253 }
1254
1255 /**
1256 * e1000_setup_link_82571 - Setup flow control and link settings
1257 * @hw: pointer to the HW structure
1258 *
1259 * Determines which flow control settings to use, then configures flow
1260 * control. Calls the appropriate media-specific link configuration
1261 * function. Assuming the adapter has a valid link partner, a valid link
1262 * should be established. Assumes the hardware has previously been reset
1263 * and the transmitter and receiver are not enabled.
1264 **/
1265 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1266 {
1267 /*
1268 * 82573 does not have a word in the NVM to determine
1269 * the default flow control setting, so we explicitly
1270 * set it to full.
1271 */
1272 switch (hw->mac.type) {
1273 case e1000_82573:
1274 case e1000_82574:
1275 case e1000_82583:
1276 if (hw->fc.requested_mode == e1000_fc_default)
1277 hw->fc.requested_mode = e1000_fc_full;
1278 break;
1279 default:
1280 break;
1281 }
1282
1283 return e1000e_setup_link(hw);
1284 }
1285
1286 /**
1287 * e1000_setup_copper_link_82571 - Configure copper link settings
1288 * @hw: pointer to the HW structure
1289 *
1290 * Configures the link for auto-neg or forced speed and duplex. Then we check
1291 * for link, once link is established calls to configure collision distance
1292 * and flow control are called.
1293 **/
1294 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1295 {
1296 u32 ctrl;
1297 u32 led_ctrl;
1298 s32 ret_val;
1299
1300 ctrl = er32(CTRL);
1301 ctrl |= E1000_CTRL_SLU;
1302 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1303 ew32(CTRL, ctrl);
1304
1305 switch (hw->phy.type) {
1306 case e1000_phy_m88:
1307 case e1000_phy_bm:
1308 ret_val = e1000e_copper_link_setup_m88(hw);
1309 break;
1310 case e1000_phy_igp_2:
1311 ret_val = e1000e_copper_link_setup_igp(hw);
1312 /* Setup activity LED */
1313 led_ctrl = er32(LEDCTL);
1314 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1315 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1316 ew32(LEDCTL, led_ctrl);
1317 break;
1318 default:
1319 return -E1000_ERR_PHY;
1320 break;
1321 }
1322
1323 if (ret_val)
1324 return ret_val;
1325
1326 ret_val = e1000e_setup_copper_link(hw);
1327
1328 return ret_val;
1329 }
1330
1331 /**
1332 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1333 * @hw: pointer to the HW structure
1334 *
1335 * Configures collision distance and flow control for fiber and serdes links.
1336 * Upon successful setup, poll for link.
1337 **/
1338 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1339 {
1340 switch (hw->mac.type) {
1341 case e1000_82571:
1342 case e1000_82572:
1343 /*
1344 * If SerDes loopback mode is entered, there is no form
1345 * of reset to take the adapter out of that mode. So we
1346 * have to explicitly take the adapter out of loopback
1347 * mode. This prevents drivers from twiddling their thumbs
1348 * if another tool failed to take it out of loopback mode.
1349 */
1350 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1351 break;
1352 default:
1353 break;
1354 }
1355
1356 return e1000e_setup_fiber_serdes_link(hw);
1357 }
1358
1359 /**
1360 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1361 * @hw: pointer to the HW structure
1362 *
1363 * Checks for link up on the hardware. If link is not up and we have
1364 * a signal, then we need to force link up.
1365 **/
1366 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1367 {
1368 struct e1000_mac_info *mac = &hw->mac;
1369 u32 rxcw;
1370 u32 ctrl;
1371 u32 status;
1372 s32 ret_val = 0;
1373
1374 ctrl = er32(CTRL);
1375 status = er32(STATUS);
1376 rxcw = er32(RXCW);
1377
1378 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1379
1380 /* Receiver is synchronized with no invalid bits. */
1381 switch (mac->serdes_link_state) {
1382 case e1000_serdes_link_autoneg_complete:
1383 if (!(status & E1000_STATUS_LU)) {
1384 /*
1385 * We have lost link, retry autoneg before
1386 * reporting link failure
1387 */
1388 mac->serdes_link_state =
1389 e1000_serdes_link_autoneg_progress;
1390 hw_dbg(hw, "AN_UP -> AN_PROG\n");
1391 }
1392 break;
1393
1394 case e1000_serdes_link_forced_up:
1395 /*
1396 * If we are receiving /C/ ordered sets, re-enable
1397 * auto-negotiation in the TXCW register and disable
1398 * forced link in the Device Control register in an
1399 * attempt to auto-negotiate with our link partner.
1400 */
1401 if (rxcw & E1000_RXCW_C) {
1402 /* Enable autoneg, and unforce link up */
1403 ew32(TXCW, mac->txcw);
1404 ew32(CTRL,
1405 (ctrl & ~E1000_CTRL_SLU));
1406 mac->serdes_link_state =
1407 e1000_serdes_link_autoneg_progress;
1408 hw_dbg(hw, "FORCED_UP -> AN_PROG\n");
1409 }
1410 break;
1411
1412 case e1000_serdes_link_autoneg_progress:
1413 /*
1414 * If the LU bit is set in the STATUS register,
1415 * autoneg has completed sucessfully. If not,
1416 * try foring the link because the far end may be
1417 * available but not capable of autonegotiation.
1418 */
1419 if (status & E1000_STATUS_LU) {
1420 mac->serdes_link_state =
1421 e1000_serdes_link_autoneg_complete;
1422 hw_dbg(hw, "AN_PROG -> AN_UP\n");
1423 } else {
1424 /*
1425 * Disable autoneg, force link up and
1426 * full duplex, and change state to forced
1427 */
1428 ew32(TXCW,
1429 (mac->txcw & ~E1000_TXCW_ANE));
1430 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1431 ew32(CTRL, ctrl);
1432
1433 /* Configure Flow Control after link up. */
1434 ret_val =
1435 e1000e_config_fc_after_link_up(hw);
1436 if (ret_val) {
1437 hw_dbg(hw, "Error config flow control\n");
1438 break;
1439 }
1440 mac->serdes_link_state =
1441 e1000_serdes_link_forced_up;
1442 hw_dbg(hw, "AN_PROG -> FORCED_UP\n");
1443 }
1444 mac->serdes_has_link = true;
1445 break;
1446
1447 case e1000_serdes_link_down:
1448 default:
1449 /* The link was down but the receiver has now gained
1450 * valid sync, so lets see if we can bring the link
1451 * up. */
1452 ew32(TXCW, mac->txcw);
1453 ew32(CTRL,
1454 (ctrl & ~E1000_CTRL_SLU));
1455 mac->serdes_link_state =
1456 e1000_serdes_link_autoneg_progress;
1457 hw_dbg(hw, "DOWN -> AN_PROG\n");
1458 break;
1459 }
1460 } else {
1461 if (!(rxcw & E1000_RXCW_SYNCH)) {
1462 mac->serdes_has_link = false;
1463 mac->serdes_link_state = e1000_serdes_link_down;
1464 hw_dbg(hw, "ANYSTATE -> DOWN\n");
1465 } else {
1466 /*
1467 * We have sync, and can tolerate one
1468 * invalid (IV) codeword before declaring
1469 * link down, so reread to look again
1470 */
1471 udelay(10);
1472 rxcw = er32(RXCW);
1473 if (rxcw & E1000_RXCW_IV) {
1474 mac->serdes_link_state = e1000_serdes_link_down;
1475 mac->serdes_has_link = false;
1476 hw_dbg(hw, "ANYSTATE -> DOWN\n");
1477 }
1478 }
1479 }
1480
1481 return ret_val;
1482 }
1483
1484 /**
1485 * e1000_valid_led_default_82571 - Verify a valid default LED config
1486 * @hw: pointer to the HW structure
1487 * @data: pointer to the NVM (EEPROM)
1488 *
1489 * Read the EEPROM for the current default LED configuration. If the
1490 * LED configuration is not valid, set to a valid LED configuration.
1491 **/
1492 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1493 {
1494 s32 ret_val;
1495
1496 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1497 if (ret_val) {
1498 hw_dbg(hw, "NVM Read Error\n");
1499 return ret_val;
1500 }
1501
1502 switch (hw->mac.type) {
1503 case e1000_82573:
1504 case e1000_82574:
1505 case e1000_82583:
1506 if (*data == ID_LED_RESERVED_F746)
1507 *data = ID_LED_DEFAULT_82573;
1508 break;
1509 default:
1510 if (*data == ID_LED_RESERVED_0000 ||
1511 *data == ID_LED_RESERVED_FFFF)
1512 *data = ID_LED_DEFAULT;
1513 break;
1514 }
1515
1516 return 0;
1517 }
1518
1519 /**
1520 * e1000e_get_laa_state_82571 - Get locally administered address state
1521 * @hw: pointer to the HW structure
1522 *
1523 * Retrieve and return the current locally administered address state.
1524 **/
1525 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1526 {
1527 if (hw->mac.type != e1000_82571)
1528 return 0;
1529
1530 return hw->dev_spec.e82571.laa_is_present;
1531 }
1532
1533 /**
1534 * e1000e_set_laa_state_82571 - Set locally administered address state
1535 * @hw: pointer to the HW structure
1536 * @state: enable/disable locally administered address
1537 *
1538 * Enable/Disable the current locally administers address state.
1539 **/
1540 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1541 {
1542 if (hw->mac.type != e1000_82571)
1543 return;
1544
1545 hw->dev_spec.e82571.laa_is_present = state;
1546
1547 /* If workaround is activated... */
1548 if (state)
1549 /*
1550 * Hold a copy of the LAA in RAR[14] This is done so that
1551 * between the time RAR[0] gets clobbered and the time it
1552 * gets fixed, the actual LAA is in one of the RARs and no
1553 * incoming packets directed to this port are dropped.
1554 * Eventually the LAA will be in RAR[0] and RAR[14].
1555 */
1556 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1557 }
1558
1559 /**
1560 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1561 * @hw: pointer to the HW structure
1562 *
1563 * Verifies that the EEPROM has completed the update. After updating the
1564 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1565 * the checksum fix is not implemented, we need to set the bit and update
1566 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1567 * we need to return bad checksum.
1568 **/
1569 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1570 {
1571 struct e1000_nvm_info *nvm = &hw->nvm;
1572 s32 ret_val;
1573 u16 data;
1574
1575 if (nvm->type != e1000_nvm_flash_hw)
1576 return 0;
1577
1578 /*
1579 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1580 * 10h-12h. Checksum may need to be fixed.
1581 */
1582 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1583 if (ret_val)
1584 return ret_val;
1585
1586 if (!(data & 0x10)) {
1587 /*
1588 * Read 0x23 and check bit 15. This bit is a 1
1589 * when the checksum has already been fixed. If
1590 * the checksum is still wrong and this bit is a
1591 * 1, we need to return bad checksum. Otherwise,
1592 * we need to set this bit to a 1 and update the
1593 * checksum.
1594 */
1595 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1596 if (ret_val)
1597 return ret_val;
1598
1599 if (!(data & 0x8000)) {
1600 data |= 0x8000;
1601 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1602 if (ret_val)
1603 return ret_val;
1604 ret_val = e1000e_update_nvm_checksum(hw);
1605 }
1606 }
1607
1608 return 0;
1609 }
1610
1611 /**
1612 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1613 * @hw: pointer to the HW structure
1614 *
1615 * Clears the hardware counters by reading the counter registers.
1616 **/
1617 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1618 {
1619 u32 temp;
1620
1621 e1000e_clear_hw_cntrs_base(hw);
1622
1623 temp = er32(PRC64);
1624 temp = er32(PRC127);
1625 temp = er32(PRC255);
1626 temp = er32(PRC511);
1627 temp = er32(PRC1023);
1628 temp = er32(PRC1522);
1629 temp = er32(PTC64);
1630 temp = er32(PTC127);
1631 temp = er32(PTC255);
1632 temp = er32(PTC511);
1633 temp = er32(PTC1023);
1634 temp = er32(PTC1522);
1635
1636 temp = er32(ALGNERRC);
1637 temp = er32(RXERRC);
1638 temp = er32(TNCRS);
1639 temp = er32(CEXTERR);
1640 temp = er32(TSCTC);
1641 temp = er32(TSCTFC);
1642
1643 temp = er32(MGTPRC);
1644 temp = er32(MGTPDC);
1645 temp = er32(MGTPTC);
1646
1647 temp = er32(IAC);
1648 temp = er32(ICRXOC);
1649
1650 temp = er32(ICRXPTC);
1651 temp = er32(ICRXATC);
1652 temp = er32(ICTXPTC);
1653 temp = er32(ICTXATC);
1654 temp = er32(ICTXQEC);
1655 temp = er32(ICTXQMTC);
1656 temp = er32(ICRXDMTC);
1657 }
1658
1659 static struct e1000_mac_operations e82571_mac_ops = {
1660 /* .check_mng_mode: mac type dependent */
1661 /* .check_for_link: media type dependent */
1662 .id_led_init = e1000e_id_led_init,
1663 .cleanup_led = e1000e_cleanup_led_generic,
1664 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1665 .get_bus_info = e1000e_get_bus_info_pcie,
1666 /* .get_link_up_info: media type dependent */
1667 /* .led_on: mac type dependent */
1668 .led_off = e1000e_led_off_generic,
1669 .update_mc_addr_list = e1000_update_mc_addr_list_82571,
1670 .reset_hw = e1000_reset_hw_82571,
1671 .init_hw = e1000_init_hw_82571,
1672 .setup_link = e1000_setup_link_82571,
1673 /* .setup_physical_interface: media type dependent */
1674 .setup_led = e1000e_setup_led_generic,
1675 };
1676
1677 static struct e1000_phy_operations e82_phy_ops_igp = {
1678 .acquire_phy = e1000_get_hw_semaphore_82571,
1679 .check_reset_block = e1000e_check_reset_block_generic,
1680 .commit_phy = NULL,
1681 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1682 .get_cfg_done = e1000_get_cfg_done_82571,
1683 .get_cable_length = e1000e_get_cable_length_igp_2,
1684 .get_phy_info = e1000e_get_phy_info_igp,
1685 .read_phy_reg = e1000e_read_phy_reg_igp,
1686 .release_phy = e1000_put_hw_semaphore_82571,
1687 .reset_phy = e1000e_phy_hw_reset_generic,
1688 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1689 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1690 .write_phy_reg = e1000e_write_phy_reg_igp,
1691 .cfg_on_link_up = NULL,
1692 };
1693
1694 static struct e1000_phy_operations e82_phy_ops_m88 = {
1695 .acquire_phy = e1000_get_hw_semaphore_82571,
1696 .check_reset_block = e1000e_check_reset_block_generic,
1697 .commit_phy = e1000e_phy_sw_reset,
1698 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1699 .get_cfg_done = e1000e_get_cfg_done,
1700 .get_cable_length = e1000e_get_cable_length_m88,
1701 .get_phy_info = e1000e_get_phy_info_m88,
1702 .read_phy_reg = e1000e_read_phy_reg_m88,
1703 .release_phy = e1000_put_hw_semaphore_82571,
1704 .reset_phy = e1000e_phy_hw_reset_generic,
1705 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1706 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1707 .write_phy_reg = e1000e_write_phy_reg_m88,
1708 .cfg_on_link_up = NULL,
1709 };
1710
1711 static struct e1000_phy_operations e82_phy_ops_bm = {
1712 .acquire_phy = e1000_get_hw_semaphore_82571,
1713 .check_reset_block = e1000e_check_reset_block_generic,
1714 .commit_phy = e1000e_phy_sw_reset,
1715 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1716 .get_cfg_done = e1000e_get_cfg_done,
1717 .get_cable_length = e1000e_get_cable_length_m88,
1718 .get_phy_info = e1000e_get_phy_info_m88,
1719 .read_phy_reg = e1000e_read_phy_reg_bm2,
1720 .release_phy = e1000_put_hw_semaphore_82571,
1721 .reset_phy = e1000e_phy_hw_reset_generic,
1722 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1723 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1724 .write_phy_reg = e1000e_write_phy_reg_bm2,
1725 .cfg_on_link_up = NULL,
1726 };
1727
1728 static struct e1000_nvm_operations e82571_nvm_ops = {
1729 .acquire_nvm = e1000_acquire_nvm_82571,
1730 .read_nvm = e1000e_read_nvm_eerd,
1731 .release_nvm = e1000_release_nvm_82571,
1732 .update_nvm = e1000_update_nvm_checksum_82571,
1733 .valid_led_default = e1000_valid_led_default_82571,
1734 .validate_nvm = e1000_validate_nvm_checksum_82571,
1735 .write_nvm = e1000_write_nvm_82571,
1736 };
1737
1738 struct e1000_info e1000_82571_info = {
1739 .mac = e1000_82571,
1740 .flags = FLAG_HAS_HW_VLAN_FILTER
1741 | FLAG_HAS_JUMBO_FRAMES
1742 | FLAG_HAS_WOL
1743 | FLAG_APME_IN_CTRL3
1744 | FLAG_RX_CSUM_ENABLED
1745 | FLAG_HAS_CTRLEXT_ON_LOAD
1746 | FLAG_HAS_SMART_POWER_DOWN
1747 | FLAG_RESET_OVERWRITES_LAA /* errata */
1748 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1749 | FLAG_APME_CHECK_PORT_B,
1750 .pba = 38,
1751 .max_hw_frame_size = DEFAULT_JUMBO,
1752 .get_variants = e1000_get_variants_82571,
1753 .mac_ops = &e82571_mac_ops,
1754 .phy_ops = &e82_phy_ops_igp,
1755 .nvm_ops = &e82571_nvm_ops,
1756 };
1757
1758 struct e1000_info e1000_82572_info = {
1759 .mac = e1000_82572,
1760 .flags = FLAG_HAS_HW_VLAN_FILTER
1761 | FLAG_HAS_JUMBO_FRAMES
1762 | FLAG_HAS_WOL
1763 | FLAG_APME_IN_CTRL3
1764 | FLAG_RX_CSUM_ENABLED
1765 | FLAG_HAS_CTRLEXT_ON_LOAD
1766 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1767 .pba = 38,
1768 .max_hw_frame_size = DEFAULT_JUMBO,
1769 .get_variants = e1000_get_variants_82571,
1770 .mac_ops = &e82571_mac_ops,
1771 .phy_ops = &e82_phy_ops_igp,
1772 .nvm_ops = &e82571_nvm_ops,
1773 };
1774
1775 struct e1000_info e1000_82573_info = {
1776 .mac = e1000_82573,
1777 .flags = FLAG_HAS_HW_VLAN_FILTER
1778 | FLAG_HAS_JUMBO_FRAMES
1779 | FLAG_HAS_WOL
1780 | FLAG_APME_IN_CTRL3
1781 | FLAG_RX_CSUM_ENABLED
1782 | FLAG_HAS_SMART_POWER_DOWN
1783 | FLAG_HAS_AMT
1784 | FLAG_HAS_ERT
1785 | FLAG_HAS_SWSM_ON_LOAD,
1786 .pba = 20,
1787 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1788 .get_variants = e1000_get_variants_82571,
1789 .mac_ops = &e82571_mac_ops,
1790 .phy_ops = &e82_phy_ops_m88,
1791 .nvm_ops = &e82571_nvm_ops,
1792 };
1793
1794 struct e1000_info e1000_82574_info = {
1795 .mac = e1000_82574,
1796 .flags = FLAG_HAS_HW_VLAN_FILTER
1797 | FLAG_HAS_MSIX
1798 | FLAG_HAS_JUMBO_FRAMES
1799 | FLAG_HAS_WOL
1800 | FLAG_APME_IN_CTRL3
1801 | FLAG_RX_CSUM_ENABLED
1802 | FLAG_HAS_SMART_POWER_DOWN
1803 | FLAG_HAS_AMT
1804 | FLAG_HAS_CTRLEXT_ON_LOAD,
1805 .pba = 20,
1806 .max_hw_frame_size = DEFAULT_JUMBO,
1807 .get_variants = e1000_get_variants_82571,
1808 .mac_ops = &e82571_mac_ops,
1809 .phy_ops = &e82_phy_ops_bm,
1810 .nvm_ops = &e82571_nvm_ops,
1811 };
1812
1813 struct e1000_info e1000_82583_info = {
1814 .mac = e1000_82583,
1815 .flags = FLAG_HAS_HW_VLAN_FILTER
1816 | FLAG_HAS_WOL
1817 | FLAG_APME_IN_CTRL3
1818 | FLAG_RX_CSUM_ENABLED
1819 | FLAG_HAS_SMART_POWER_DOWN
1820 | FLAG_HAS_AMT
1821 | FLAG_HAS_CTRLEXT_ON_LOAD,
1822 .pba = 20,
1823 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1824 .get_variants = e1000_get_variants_82571,
1825 .mac_ops = &e82571_mac_ops,
1826 .phy_ops = &e82_phy_ops_bm,
1827 .nvm_ops = &e82571_nvm_ops,
1828 };
1829
Verdex Pro support