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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / ixgbe / ixgbe_82599.c
blob34b04924c8a1f6412f7231306833c3ceebafbe63
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
51 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed,
53 bool *autoneg);
54 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
59
60 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
61 {
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
65 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
66 } else {
67 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
68 }
69 }
70
71 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
72 {
73 s32 ret_val = 0;
74 u16 list_offset, data_offset, data_value;
75
76 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
77 ixgbe_init_mac_link_ops_82599(hw);
78
79 hw->phy.ops.reset = NULL;
80
81 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
82 &data_offset);
83
84 if (ret_val != 0)
85 goto setup_sfp_out;
86
87 /* PHY config will finish before releasing the semaphore */
88 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
89 if (ret_val != 0) {
90 ret_val = IXGBE_ERR_SWFW_SYNC;
91 goto setup_sfp_out;
92 }
93
94 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
95 while (data_value != 0xffff) {
96 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
97 IXGBE_WRITE_FLUSH(hw);
98 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
99 }
100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
102 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
103
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw->eeprom.semaphore_delay);
108 }
109
110 setup_sfp_out:
111 return ret_val;
112 }
113
114 /**
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
117 *
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
120 **/
121 static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
122 {
123 struct ixgbe_adapter *adapter = hw->back;
124 u16 msix_count;
125 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
126 &msix_count);
127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
128
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
130 msix_count++;
131
132 return msix_count;
133 }
134
135 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
136 {
137 struct ixgbe_mac_info *mac = &hw->mac;
138
139 ixgbe_init_mac_link_ops_82599(hw);
140
141 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
142 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
143 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
144 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
145 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
147
148 return 0;
149 }
150
151 /**
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
154 *
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
158 *
159 **/
160 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
161 {
162 struct ixgbe_mac_info *mac = &hw->mac;
163 struct ixgbe_phy_info *phy = &hw->phy;
164 s32 ret_val = 0;
165
166 /* Identify the PHY or SFP module */
167 ret_val = phy->ops.identify(hw);
168
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw);
171
172 /* If copper media, overwrite with copper function pointers */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
175 mac->ops.get_link_capabilities =
176 &ixgbe_get_copper_link_capabilities_82599;
177 }
178
179 /* Set necessary function pointers based on phy type */
180 switch (hw->phy.type) {
181 case ixgbe_phy_tn:
182 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
183 phy->ops.get_firmware_version =
184 &ixgbe_get_phy_firmware_version_tnx;
185 break;
186 default:
187 break;
188 }
189
190 return ret_val;
191 }
192
193 /**
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
198 *
199 * Determines the link capabilities by reading the AUTOC register.
200 **/
201 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
202 ixgbe_link_speed *speed,
203 bool *negotiation)
204 {
205 s32 status = 0;
206 u32 autoc = 0;
207
208 /*
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
212 */
213 if (hw->mac.orig_link_settings_stored)
214 autoc = hw->mac.orig_autoc;
215 else
216 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
217
218 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_1GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
226 *negotiation = false;
227 break;
228
229 case IXGBE_AUTOC_LMS_1G_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = true;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_SERIAL:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_KX4_KX_KR:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
241 *speed = IXGBE_LINK_SPEED_UNKNOWN;
242 if (autoc & IXGBE_AUTOC_KR_SUPP)
243 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
244 if (autoc & IXGBE_AUTOC_KX4_SUPP)
245 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
246 if (autoc & IXGBE_AUTOC_KX_SUPP)
247 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = true;
249 break;
250
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
252 *speed = IXGBE_LINK_SPEED_100_FULL;
253 if (autoc & IXGBE_AUTOC_KR_SUPP)
254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
257 if (autoc & IXGBE_AUTOC_KX_SUPP)
258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
263 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
264 *negotiation = false;
265 break;
266
267 default:
268 status = IXGBE_ERR_LINK_SETUP;
269 goto out;
270 break;
271 }
272
273 if (hw->phy.multispeed_fiber) {
274 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
275 IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 }
278
279 out:
280 return status;
281 }
282
283 /**
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *autoneg)
294 {
295 s32 status = IXGBE_ERR_LINK_SETUP;
296 u16 speed_ability;
297
298 *speed = 0;
299 *autoneg = true;
300
301 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
302 &speed_ability);
303
304 if (status == 0) {
305 if (speed_ability & MDIO_SPEED_10G)
306 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
307 if (speed_ability & MDIO_PMA_SPEED_1000)
308 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
309 }
310
311 return status;
312 }
313
314 /**
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
317 *
318 * Returns the media type (fiber, copper, backplane)
319 **/
320 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
321 {
322 enum ixgbe_media_type media_type;
323
324 /* Detect if there is a copper PHY attached. */
325 if (hw->phy.type == ixgbe_phy_cu_unknown ||
326 hw->phy.type == ixgbe_phy_tn) {
327 media_type = ixgbe_media_type_copper;
328 goto out;
329 }
330
331 switch (hw->device_id) {
332 case IXGBE_DEV_ID_82599_KX4:
333 case IXGBE_DEV_ID_82599_KX4_MEZZ:
334 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
335 case IXGBE_DEV_ID_82599_XAUI_LOM:
336 /* Default device ID is mezzanine card KX/KX4 */
337 media_type = ixgbe_media_type_backplane;
338 break;
339 case IXGBE_DEV_ID_82599_SFP:
340 media_type = ixgbe_media_type_fiber;
341 break;
342 case IXGBE_DEV_ID_82599_CX4:
343 media_type = ixgbe_media_type_cx4;
344 break;
345 default:
346 media_type = ixgbe_media_type_unknown;
347 break;
348 }
349 out:
350 return media_type;
351 }
352
353 /**
354 * ixgbe_start_mac_link_82599 - Setup MAC link settings
355 * @hw: pointer to hardware structure
356 * @autoneg_wait_to_complete: true when waiting for completion is needed
357 *
358 * Configures link settings based on values in the ixgbe_hw struct.
359 * Restarts the link. Performs autonegotiation if needed.
360 **/
361 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
362 bool autoneg_wait_to_complete)
363 {
364 u32 autoc_reg;
365 u32 links_reg;
366 u32 i;
367 s32 status = 0;
368
369 /* Restart link */
370 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
371 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
372 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
373
374 /* Only poll for autoneg to complete if specified to do so */
375 if (autoneg_wait_to_complete) {
376 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
377 IXGBE_AUTOC_LMS_KX4_KX_KR ||
378 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
379 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
380 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
381 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
382 links_reg = 0; /* Just in case Autoneg time = 0 */
383 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
384 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
385 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
386 break;
387 msleep(100);
388 }
389 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
390 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
391 hw_dbg(hw, "Autoneg did not complete.\n");
392 }
393 }
394 }
395
396 /* Add delay to filter out noises during initial link setup */
397 msleep(50);
398
399 return status;
400 }
401
402 /**
403 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
404 * @hw: pointer to hardware structure
405 * @speed: new link speed
406 * @autoneg: true if autonegotiation enabled
407 * @autoneg_wait_to_complete: true when waiting for completion is needed
408 *
409 * Set the link speed in the AUTOC register and restarts link.
410 **/
411 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
412 ixgbe_link_speed speed,
413 bool autoneg,
414 bool autoneg_wait_to_complete)
415 {
416 s32 status = 0;
417 ixgbe_link_speed phy_link_speed;
418 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
419 u32 speedcnt = 0;
420 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
421 bool link_up = false;
422 bool negotiation;
423 int i;
424
425 /* Mask off requested but non-supported speeds */
426 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
427 speed &= phy_link_speed;
428
429 /*
430 * When the driver changes the link speeds that it can support,
431 * it sets autotry_restart to true to indicate that we need to
432 * initiate a new autotry session with the link partner. To do
433 * so, we set the speed then disable and re-enable the tx laser, to
434 * alert the link partner that it also needs to restart autotry on its
435 * end. This is consistent with true clause 37 autoneg, which also
436 * involves a loss of signal.
437 */
438
439 /*
440 * Try each speed one by one, highest priority first. We do this in
441 * software because 10gb fiber doesn't support speed autonegotiation.
442 */
443 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
444 speedcnt++;
445 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
446
447 /* If we already have link at this speed, just jump out */
448 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
449
450 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
451 goto out;
452
453 /* Set the module link speed */
454 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
455 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
456
457 /* Allow module to change analog characteristics (1G->10G) */
458 msleep(40);
459
460 status = ixgbe_setup_mac_link_82599(hw,
461 IXGBE_LINK_SPEED_10GB_FULL,
462 autoneg,
463 autoneg_wait_to_complete);
464 if (status != 0)
465 return status;
466
467 /* Flap the tx laser if it has not already been done */
468 if (hw->mac.autotry_restart) {
469 /* Disable tx laser; allow 100us to go dark per spec */
470 esdp_reg |= IXGBE_ESDP_SDP3;
471 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
472 udelay(100);
473
474 /* Enable tx laser; allow 2ms to light up per spec */
475 esdp_reg &= ~IXGBE_ESDP_SDP3;
476 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
477 msleep(2);
478
479 hw->mac.autotry_restart = false;
480 }
481
482 /* The controller may take up to 500ms at 10g to acquire link */
483 for (i = 0; i < 5; i++) {
484 /* Wait for the link partner to also set speed */
485 msleep(100);
486
487 /* If we have link, just jump out */
488 hw->mac.ops.check_link(hw, &phy_link_speed,
489 &link_up, false);
490 if (link_up)
491 goto out;
492 }
493 }
494
495 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
496 speedcnt++;
497 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
498 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
499
500 /* If we already have link at this speed, just jump out */
501 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
502
503 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
504 goto out;
505
506 /* Set the module link speed */
507 esdp_reg &= ~IXGBE_ESDP_SDP5;
508 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
510
511 /* Allow module to change analog characteristics (10G->1G) */
512 msleep(40);
513
514 status = ixgbe_setup_mac_link_82599(hw,
515 IXGBE_LINK_SPEED_1GB_FULL,
516 autoneg,
517 autoneg_wait_to_complete);
518 if (status != 0)
519 return status;
520
521 /* Flap the tx laser if it has not already been done */
522 if (hw->mac.autotry_restart) {
523 /* Disable tx laser; allow 100us to go dark per spec */
524 esdp_reg |= IXGBE_ESDP_SDP3;
525 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
526 udelay(100);
527
528 /* Enable tx laser; allow 2ms to light up per spec */
529 esdp_reg &= ~IXGBE_ESDP_SDP3;
530 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
531 msleep(2);
532
533 hw->mac.autotry_restart = false;
534 }
535
536 /* Wait for the link partner to also set speed */
537 msleep(100);
538
539 /* If we have link, just jump out */
540 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
541 if (link_up)
542 goto out;
543 }
544
545 /*
546 * We didn't get link. Configure back to the highest speed we tried,
547 * (if there was more than one). We call ourselves back with just the
548 * single highest speed that the user requested.
549 */
550 if (speedcnt > 1)
551 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
552 highest_link_speed,
553 autoneg,
554 autoneg_wait_to_complete);
555
556 out:
557 /* Set autoneg_advertised value based on input link speed */
558 hw->phy.autoneg_advertised = 0;
559
560 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
561 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
562
563 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
564 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
565
566 return status;
567 }
568
569 /**
570 * ixgbe_check_mac_link_82599 - Determine link and speed status
571 * @hw: pointer to hardware structure
572 * @speed: pointer to link speed
573 * @link_up: true when link is up
574 * @link_up_wait_to_complete: bool used to wait for link up or not
575 *
576 * Reads the links register to determine if link is up and the current speed
577 **/
578 static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
579 ixgbe_link_speed *speed,
580 bool *link_up,
581 bool link_up_wait_to_complete)
582 {
583 u32 links_reg;
584 u32 i;
585
586 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
587 if (link_up_wait_to_complete) {
588 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
589 if (links_reg & IXGBE_LINKS_UP) {
590 *link_up = true;
591 break;
592 } else {
593 *link_up = false;
594 }
595 msleep(100);
596 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
597 }
598 } else {
599 if (links_reg & IXGBE_LINKS_UP)
600 *link_up = true;
601 else
602 *link_up = false;
603 }
604
605 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
606 IXGBE_LINKS_SPEED_10G_82599)
607 *speed = IXGBE_LINK_SPEED_10GB_FULL;
608 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
609 IXGBE_LINKS_SPEED_1G_82599)
610 *speed = IXGBE_LINK_SPEED_1GB_FULL;
611 else
612 *speed = IXGBE_LINK_SPEED_100_FULL;
613
614 /* if link is down, zero out the current_mode */
615 if (*link_up == false) {
616 hw->fc.current_mode = ixgbe_fc_none;
617 hw->fc.fc_was_autonegged = false;
618 }
619
620 return 0;
621 }
622
623 /**
624 * ixgbe_setup_mac_link_82599 - Set MAC link speed
625 * @hw: pointer to hardware structure
626 * @speed: new link speed
627 * @autoneg: true if autonegotiation enabled
628 * @autoneg_wait_to_complete: true when waiting for completion is needed
629 *
630 * Set the link speed in the AUTOC register and restarts link.
631 **/
632 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
633 ixgbe_link_speed speed, bool autoneg,
634 bool autoneg_wait_to_complete)
635 {
636 s32 status = 0;
637 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
638 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
639 u32 start_autoc = autoc;
640 u32 orig_autoc = 0;
641 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
642 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
643 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
644 u32 links_reg;
645 u32 i;
646 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
647
648 /* Check to see if speed passed in is supported. */
649 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
650 speed &= link_capabilities;
651
652 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
653 status = IXGBE_ERR_LINK_SETUP;
654 goto out;
655 }
656
657 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
658 if (hw->mac.orig_link_settings_stored)
659 orig_autoc = hw->mac.orig_autoc;
660 else
661 orig_autoc = autoc;
662
663
664 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
665 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
666 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
667 /* Set KX4/KX/KR support according to speed requested */
668 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
669 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
670 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
671 autoc |= IXGBE_AUTOC_KX4_SUPP;
672 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
673 autoc |= IXGBE_AUTOC_KR_SUPP;
674 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
675 autoc |= IXGBE_AUTOC_KX_SUPP;
676 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
677 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
678 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
679 /* Switch from 1G SFI to 10G SFI if requested */
680 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
681 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
682 autoc &= ~IXGBE_AUTOC_LMS_MASK;
683 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
684 }
685 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
686 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
687 /* Switch from 10G SFI to 1G SFI if requested */
688 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
689 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
690 autoc &= ~IXGBE_AUTOC_LMS_MASK;
691 if (autoneg)
692 autoc |= IXGBE_AUTOC_LMS_1G_AN;
693 else
694 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
695 }
696 }
697
698 if (autoc != start_autoc) {
699 /* Restart link */
700 autoc |= IXGBE_AUTOC_AN_RESTART;
701 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
702
703 /* Only poll for autoneg to complete if specified to do so */
704 if (autoneg_wait_to_complete) {
705 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
706 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
707 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
708 links_reg = 0; /*Just in case Autoneg time=0*/
709 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
710 links_reg =
711 IXGBE_READ_REG(hw, IXGBE_LINKS);
712 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
713 break;
714 msleep(100);
715 }
716 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
717 status =
718 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
719 hw_dbg(hw, "Autoneg did not "
720 "complete.\n");
721 }
722 }
723 }
724
725 /* Add delay to filter out noises during initial link setup */
726 msleep(50);
727 }
728
729 out:
730 return status;
731 }
732
733 /**
734 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
735 * @hw: pointer to hardware structure
736 * @speed: new link speed
737 * @autoneg: true if autonegotiation enabled
738 * @autoneg_wait_to_complete: true if waiting is needed to complete
739 *
740 * Restarts link on PHY and MAC based on settings passed in.
741 **/
742 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
743 ixgbe_link_speed speed,
744 bool autoneg,
745 bool autoneg_wait_to_complete)
746 {
747 s32 status;
748
749 /* Setup the PHY according to input speed */
750 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
751 autoneg_wait_to_complete);
752 /* Set up MAC */
753 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
754
755 return status;
756 }
757
758 /**
759 * ixgbe_reset_hw_82599 - Perform hardware reset
760 * @hw: pointer to hardware structure
761 *
762 * Resets the hardware by resetting the transmit and receive units, masks
763 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
764 * reset.
765 **/
766 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
767 {
768 s32 status = 0;
769 u32 ctrl, ctrl_ext;
770 u32 i;
771 u32 autoc;
772 u32 autoc2;
773
774 /* Call adapter stop to disable tx/rx and clear interrupts */
775 hw->mac.ops.stop_adapter(hw);
776
777 /* PHY ops must be identified and initialized prior to reset */
778
779 /* Init PHY and function pointers, perform SFP setup */
780 status = hw->phy.ops.init(hw);
781
782 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
783 goto reset_hw_out;
784
785 /* Setup SFP module if there is one present. */
786 if (hw->phy.sfp_setup_needed) {
787 status = hw->mac.ops.setup_sfp(hw);
788 hw->phy.sfp_setup_needed = false;
789 }
790
791 /* Reset PHY */
792 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
793 hw->phy.ops.reset(hw);
794
795 /*
796 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
797 * access and verify no pending requests before reset
798 */
799 status = ixgbe_disable_pcie_master(hw);
800 if (status != 0) {
801 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
802 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
803 }
804
805 /*
806 * Issue global reset to the MAC. This needs to be a SW reset.
807 * If link reset is used, it might reset the MAC when mng is using it
808 */
809 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
810 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
811 IXGBE_WRITE_FLUSH(hw);
812
813 /* Poll for reset bit to self-clear indicating reset is complete */
814 for (i = 0; i < 10; i++) {
815 udelay(1);
816 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
817 if (!(ctrl & IXGBE_CTRL_RST))
818 break;
819 }
820 if (ctrl & IXGBE_CTRL_RST) {
821 status = IXGBE_ERR_RESET_FAILED;
822 hw_dbg(hw, "Reset polling failed to complete.\n");
823 }
824 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
825 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
826 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
827 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
828
829 msleep(50);
830
831
832
833 /*
834 * Store the original AUTOC/AUTOC2 values if they have not been
835 * stored off yet. Otherwise restore the stored original
836 * values since the reset operation sets back to defaults.
837 */
838 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
839 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
840 if (hw->mac.orig_link_settings_stored == false) {
841 hw->mac.orig_autoc = autoc;
842 hw->mac.orig_autoc2 = autoc2;
843 hw->mac.orig_link_settings_stored = true;
844 } else {
845 if (autoc != hw->mac.orig_autoc)
846 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
847 IXGBE_AUTOC_AN_RESTART));
848
849 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
850 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
851 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
852 autoc2 |= (hw->mac.orig_autoc2 &
853 IXGBE_AUTOC2_UPPER_MASK);
854 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
855 }
856 }
857
858 /*
859 * Store MAC address from RAR0, clear receive address registers, and
860 * clear the multicast table. Also reset num_rar_entries to 128,
861 * since we modify this value when programming the SAN MAC address.
862 */
863 hw->mac.num_rar_entries = 128;
864 hw->mac.ops.init_rx_addrs(hw);
865
866 /* Store the permanent mac address */
867 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
868
869 /* Store the permanent SAN mac address */
870 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
871
872 /* Add the SAN MAC address to the RAR only if it's a valid address */
873 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
874 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
875 hw->mac.san_addr, 0, IXGBE_RAH_AV);
876
877 /* Reserve the last RAR for the SAN MAC address */
878 hw->mac.num_rar_entries--;
879 }
880
881 reset_hw_out:
882 return status;
883 }
884
885 /**
886 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
887 * @hw: pointer to hardware struct
888 * @rar: receive address register index to disassociate
889 * @vmdq: VMDq pool index to remove from the rar
890 **/
891 static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
892 {
893 u32 mpsar_lo, mpsar_hi;
894 u32 rar_entries = hw->mac.num_rar_entries;
895
896 if (rar < rar_entries) {
897 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
898 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
899
900 if (!mpsar_lo && !mpsar_hi)
901 goto done;
902
903 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
904 if (mpsar_lo) {
905 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
906 mpsar_lo = 0;
907 }
908 if (mpsar_hi) {
909 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
910 mpsar_hi = 0;
911 }
912 } else if (vmdq < 32) {
913 mpsar_lo &= ~(1 << vmdq);
914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
915 } else {
916 mpsar_hi &= ~(1 << (vmdq - 32));
917 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
918 }
919
920 /* was that the last pool using this rar? */
921 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
922 hw->mac.ops.clear_rar(hw, rar);
923 } else {
924 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
925 }
926
927 done:
928 return 0;
929 }
930
931 /**
932 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
933 * @hw: pointer to hardware struct
934 * @rar: receive address register index to associate with a VMDq index
935 * @vmdq: VMDq pool index
936 **/
937 static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
938 {
939 u32 mpsar;
940 u32 rar_entries = hw->mac.num_rar_entries;
941
942 if (rar < rar_entries) {
943 if (vmdq < 32) {
944 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
945 mpsar |= 1 << vmdq;
946 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
947 } else {
948 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
949 mpsar |= 1 << (vmdq - 32);
950 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
951 }
952 } else {
953 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
954 }
955 return 0;
956 }
957
958 /**
959 * ixgbe_set_vfta_82599 - Set VLAN filter table
960 * @hw: pointer to hardware structure
961 * @vlan: VLAN id to write to VLAN filter
962 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
963 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
964 *
965 * Turn on/off specified VLAN in the VLAN filter table.
966 **/
967 static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
968 bool vlan_on)
969 {
970 u32 regindex;
971 u32 bitindex;
972 u32 bits;
973 u32 first_empty_slot;
974
975 if (vlan > 4095)
976 return IXGBE_ERR_PARAM;
977
978 /*
979 * this is a 2 part operation - first the VFTA, then the
980 * VLVF and VLVFB if vind is set
981 */
982
983 /* Part 1
984 * The VFTA is a bitstring made up of 128 32-bit registers
985 * that enable the particular VLAN id, much like the MTA:
986 * bits[11-5]: which register
987 * bits[4-0]: which bit in the register
988 */
989 regindex = (vlan >> 5) & 0x7F;
990 bitindex = vlan & 0x1F;
991 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
992 if (vlan_on)
993 bits |= (1 << bitindex);
994 else
995 bits &= ~(1 << bitindex);
996 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
997
998
999 /* Part 2
1000 * If the vind is set
1001 * Either vlan_on
1002 * make sure the vlan is in VLVF
1003 * set the vind bit in the matching VLVFB
1004 * Or !vlan_on
1005 * clear the pool bit and possibly the vind
1006 */
1007 if (vind) {
1008 /* find the vlanid or the first empty slot */
1009 first_empty_slot = 0;
1010
1011 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1012 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1013 if (!bits && !first_empty_slot)
1014 first_empty_slot = regindex;
1015 else if ((bits & 0x0FFF) == vlan)
1016 break;
1017 }
1018
1019 if (regindex >= IXGBE_VLVF_ENTRIES) {
1020 if (first_empty_slot)
1021 regindex = first_empty_slot;
1022 else {
1023 hw_dbg(hw, "No space in VLVF.\n");
1024 goto out;
1025 }
1026 }
1027
1028 if (vlan_on) {
1029 /* set the pool bit */
1030 if (vind < 32) {
1031 bits = IXGBE_READ_REG(hw,
1032 IXGBE_VLVFB(regindex * 2));
1033 bits |= (1 << vind);
1034 IXGBE_WRITE_REG(hw,
1035 IXGBE_VLVFB(regindex * 2), bits);
1036 } else {
1037 bits = IXGBE_READ_REG(hw,
1038 IXGBE_VLVFB((regindex * 2) + 1));
1039 bits |= (1 << vind);
1040 IXGBE_WRITE_REG(hw,
1041 IXGBE_VLVFB((regindex * 2) + 1), bits);
1042 }
1043 } else {
1044 /* clear the pool bit */
1045 if (vind < 32) {
1046 bits = IXGBE_READ_REG(hw,
1047 IXGBE_VLVFB(regindex * 2));
1048 bits &= ~(1 << vind);
1049 IXGBE_WRITE_REG(hw,
1050 IXGBE_VLVFB(regindex * 2), bits);
1051 bits |= IXGBE_READ_REG(hw,
1052 IXGBE_VLVFB((regindex * 2) + 1));
1053 } else {
1054 bits = IXGBE_READ_REG(hw,
1055 IXGBE_VLVFB((regindex * 2) + 1));
1056 bits &= ~(1 << vind);
1057 IXGBE_WRITE_REG(hw,
1058 IXGBE_VLVFB((regindex * 2) + 1), bits);
1059 bits |= IXGBE_READ_REG(hw,
1060 IXGBE_VLVFB(regindex * 2));
1061 }
1062 }
1063
1064 if (bits)
1065 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1066 (IXGBE_VLVF_VIEN | vlan));
1067 else
1068 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1069 }
1070
1071 out:
1072 return 0;
1073 }
1074
1075 /**
1076 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1077 * @hw: pointer to hardware structure
1078 *
1079 * Clears the VLAN filer table, and the VMDq index associated with the filter
1080 **/
1081 static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1082 {
1083 u32 offset;
1084
1085 for (offset = 0; offset < hw->mac.vft_size; offset++)
1086 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1087
1088 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1089 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1090 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1091 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1092 }
1093
1094 return 0;
1095 }
1096
1097 /**
1098 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1099 * @hw: pointer to hardware structure
1100 **/
1101 static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1102 {
1103 int i;
1104 hw_dbg(hw, " Clearing UTA\n");
1105
1106 for (i = 0; i < 128; i++)
1107 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1108
1109 return 0;
1110 }
1111
1112 /**
1113 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1114 * @hw: pointer to hardware structure
1115 **/
1116 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1117 {
1118 int i;
1119 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1120 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1121
1122 /*
1123 * Before starting reinitialization process,
1124 * FDIRCMD.CMD must be zero.
1125 */
1126 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1127 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1128 IXGBE_FDIRCMD_CMD_MASK))
1129 break;
1130 udelay(10);
1131 }
1132 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1133 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1134 "aborting table re-initialization. \n");
1135 return IXGBE_ERR_FDIR_REINIT_FAILED;
1136 }
1137
1138 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1139 IXGBE_WRITE_FLUSH(hw);
1140 /*
1141 * 82599 adapters flow director init flow cannot be restarted,
1142 * Workaround 82599 silicon errata by performing the following steps
1143 * before re-writing the FDIRCTRL control register with the same value.
1144 * - write 1 to bit 8 of FDIRCMD register &
1145 * - write 0 to bit 8 of FDIRCMD register
1146 */
1147 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1148 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1149 IXGBE_FDIRCMD_CLEARHT));
1150 IXGBE_WRITE_FLUSH(hw);
1151 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1152 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1153 ~IXGBE_FDIRCMD_CLEARHT));
1154 IXGBE_WRITE_FLUSH(hw);
1155 /*
1156 * Clear FDIR Hash register to clear any leftover hashes
1157 * waiting to be programmed.
1158 */
1159 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1160 IXGBE_WRITE_FLUSH(hw);
1161
1162 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1163 IXGBE_WRITE_FLUSH(hw);
1164
1165 /* Poll init-done after we write FDIRCTRL register */
1166 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1167 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1168 IXGBE_FDIRCTRL_INIT_DONE)
1169 break;
1170 udelay(10);
1171 }
1172 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1173 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1174 return IXGBE_ERR_FDIR_REINIT_FAILED;
1175 }
1176
1177 /* Clear FDIR statistics registers (read to clear) */
1178 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1179 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1180 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1182 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1183
1184 return 0;
1185 }
1186
1187 /**
1188 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1189 * @hw: pointer to hardware structure
1190 * @pballoc: which mode to allocate filters with
1191 **/
1192 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1193 {
1194 u32 fdirctrl = 0;
1195 u32 pbsize;
1196 int i;
1197
1198 /*
1199 * Before enabling Flow Director, the Rx Packet Buffer size
1200 * must be reduced. The new value is the current size minus
1201 * flow director memory usage size.
1202 */
1203 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1204 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1205 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1206
1207 /*
1208 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1209 * intialized to zero for non DCB mode otherwise actual total RX PB
1210 * would be bigger than programmed and filter space would run into
1211 * the PB 0 region.
1212 */
1213 for (i = 1; i < 8; i++)
1214 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1215
1216 /* Send interrupt when 64 filters are left */
1217 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1218
1219 /* Set the maximum length per hash bucket to 0xA filters */
1220 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1221
1222 switch (pballoc) {
1223 case IXGBE_FDIR_PBALLOC_64K:
1224 /* 8k - 1 signature filters */
1225 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1226 break;
1227 case IXGBE_FDIR_PBALLOC_128K:
1228 /* 16k - 1 signature filters */
1229 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1230 break;
1231 case IXGBE_FDIR_PBALLOC_256K:
1232 /* 32k - 1 signature filters */
1233 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1234 break;
1235 default:
1236 /* bad value */
1237 return IXGBE_ERR_CONFIG;
1238 };
1239
1240 /* Move the flexible bytes to use the ethertype - shift 6 words */
1241 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1242
1243 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1244
1245 /* Prime the keys for hashing */
1246 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1247 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1249 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1250
1251 /*
1252 * Poll init-done after we write the register. Estimated times:
1253 * 10G: PBALLOC = 11b, timing is 60us
1254 * 1G: PBALLOC = 11b, timing is 600us
1255 * 100M: PBALLOC = 11b, timing is 6ms
1256 *
1257 * Multiple these timings by 4 if under full Rx load
1258 *
1259 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1260 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1261 * this might not finish in our poll time, but we can live with that
1262 * for now.
1263 */
1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1265 IXGBE_WRITE_FLUSH(hw);
1266 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1267 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1268 IXGBE_FDIRCTRL_INIT_DONE)
1269 break;
1270 msleep(1);
1271 }
1272 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1273 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1274
1275 return 0;
1276 }
1277
1278 /**
1279 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1280 * @hw: pointer to hardware structure
1281 * @pballoc: which mode to allocate filters with
1282 **/
1283 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1284 {
1285 u32 fdirctrl = 0;
1286 u32 pbsize;
1287 int i;
1288
1289 /*
1290 * Before enabling Flow Director, the Rx Packet Buffer size
1291 * must be reduced. The new value is the current size minus
1292 * flow director memory usage size.
1293 */
1294 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1295 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1296 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1297
1298 /*
1299 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1300 * intialized to zero for non DCB mode otherwise actual total RX PB
1301 * would be bigger than programmed and filter space would run into
1302 * the PB 0 region.
1303 */
1304 for (i = 1; i < 8; i++)
1305 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1306
1307 /* Send interrupt when 64 filters are left */
1308 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1309
1310 switch (pballoc) {
1311 case IXGBE_FDIR_PBALLOC_64K:
1312 /* 2k - 1 perfect filters */
1313 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1314 break;
1315 case IXGBE_FDIR_PBALLOC_128K:
1316 /* 4k - 1 perfect filters */
1317 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1318 break;
1319 case IXGBE_FDIR_PBALLOC_256K:
1320 /* 8k - 1 perfect filters */
1321 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1322 break;
1323 default:
1324 /* bad value */
1325 return IXGBE_ERR_CONFIG;
1326 };
1327
1328 /* Turn perfect match filtering on */
1329 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1330 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1331
1332 /* Move the flexible bytes to use the ethertype - shift 6 words */
1333 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1334
1335 /* Prime the keys for hashing */
1336 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1337 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1338 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1339 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1340
1341 /*
1342 * Poll init-done after we write the register. Estimated times:
1343 * 10G: PBALLOC = 11b, timing is 60us
1344 * 1G: PBALLOC = 11b, timing is 600us
1345 * 100M: PBALLOC = 11b, timing is 6ms
1346 *
1347 * Multiple these timings by 4 if under full Rx load
1348 *
1349 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1350 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1351 * this might not finish in our poll time, but we can live with that
1352 * for now.
1353 */
1354
1355 /* Set the maximum length per hash bucket to 0xA filters */
1356 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1357
1358 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1359 IXGBE_WRITE_FLUSH(hw);
1360 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1361 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1362 IXGBE_FDIRCTRL_INIT_DONE)
1363 break;
1364 msleep(1);
1365 }
1366 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1367 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1368
1369 return 0;
1370 }
1371
1372
1373 /**
1374 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1375 * @stream: input bitstream to compute the hash on
1376 * @key: 32-bit hash key
1377 **/
1378 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1379 u32 key)
1380 {
1381 /*
1382 * The algorithm is as follows:
1383 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1384 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1385 * and A[n] x B[n] is bitwise AND between same length strings
1386 *
1387 * K[n] is 16 bits, defined as:
1388 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1389 * for n modulo 32 < 15, K[n] =
1390 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1391 *
1392 * S[n] is 16 bits, defined as:
1393 * for n >= 15, S[n] = S[n:n - 15]
1394 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1395 *
1396 * To simplify for programming, the algorithm is implemented
1397 * in software this way:
1398 *
1399 * Key[31:0], Stream[335:0]
1400 *
1401 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1402 * int_key[350:0] = tmp_key[351:1]
1403 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1404 *
1405 * hash[15:0] = 0;
1406 * for (i = 0; i < 351; i++) {
1407 * if (int_key[i])
1408 * hash ^= int_stream[(i + 15):i];
1409 * }
1410 */
1411
1412 union {
1413 u64 fill[6];
1414 u32 key[11];
1415 u8 key_stream[44];
1416 } tmp_key;
1417
1418 u8 *stream = (u8 *)atr_input;
1419 u8 int_key[44]; /* upper-most bit unused */
1420 u8 hash_str[46]; /* upper-most 2 bits unused */
1421 u16 hash_result = 0;
1422 int i, j, k, h;
1423
1424 /*
1425 * Initialize the fill member to prevent warnings
1426 * on some compilers
1427 */
1428 tmp_key.fill[0] = 0;
1429
1430 /* First load the temporary key stream */
1431 for (i = 0; i < 6; i++) {
1432 u64 fillkey = ((u64)key << 32) | key;
1433 tmp_key.fill[i] = fillkey;
1434 }
1435
1436 /*
1437 * Set the interim key for the hashing. Bit 352 is unused, so we must
1438 * shift and compensate when building the key.
1439 */
1440
1441 int_key[0] = tmp_key.key_stream[0] >> 1;
1442 for (i = 1, j = 0; i < 44; i++) {
1443 unsigned int this_key = tmp_key.key_stream[j] << 7;
1444 j++;
1445 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1446 }
1447
1448 /*
1449 * Set the interim bit string for the hashing. Bits 368 and 367 are
1450 * unused, so shift and compensate when building the string.
1451 */
1452 hash_str[0] = (stream[40] & 0x7f) >> 1;
1453 for (i = 1, j = 40; i < 46; i++) {
1454 unsigned int this_str = stream[j] << 7;
1455 j++;
1456 if (j > 41)
1457 j = 0;
1458 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1459 }
1460
1461 /*
1462 * Now compute the hash. i is the index into hash_str, j is into our
1463 * key stream, k is counting the number of bits, and h interates within
1464 * each byte.
1465 */
1466 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1467 for (h = 0; h < 8 && k < 351; h++, k++) {
1468 if (int_key[j] & (1 << h)) {
1469 /*
1470 * Key bit is set, XOR in the current 16-bit
1471 * string. Example of processing:
1472 * h = 0,
1473 * tmp = (hash_str[i - 2] & 0 << 16) |
1474 * (hash_str[i - 1] & 0xff << 8) |
1475 * (hash_str[i] & 0xff >> 0)
1476 * So tmp = hash_str[15 + k:k], since the
1477 * i + 2 clause rolls off the 16-bit value
1478 * h = 7,
1479 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1480 * (hash_str[i - 1] & 0xff << 1) |
1481 * (hash_str[i] & 0x80 >> 7)
1482 */
1483 int tmp = (hash_str[i] >> h);
1484 tmp |= (hash_str[i - 1] << (8 - h));
1485 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1486 << (16 - h);
1487 hash_result ^= (u16)tmp;
1488 }
1489 }
1490 }
1491
1492 return hash_result;
1493 }
1494
1495 /**
1496 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1497 * @input: input stream to modify
1498 * @vlan: the VLAN id to load
1499 **/
1500 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1501 {
1502 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1503 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1504
1505 return 0;
1506 }
1507
1508 /**
1509 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1510 * @input: input stream to modify
1511 * @src_addr: the IP address to load
1512 **/
1513 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1514 {
1515 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1516 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1517 (src_addr >> 16) & 0xff;
1518 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1519 (src_addr >> 8) & 0xff;
1520 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1521
1522 return 0;
1523 }
1524
1525 /**
1526 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1527 * @input: input stream to modify
1528 * @dst_addr: the IP address to load
1529 **/
1530 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1531 {
1532 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1533 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1534 (dst_addr >> 16) & 0xff;
1535 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1536 (dst_addr >> 8) & 0xff;
1537 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1538
1539 return 0;
1540 }
1541
1542 /**
1543 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1544 * @input: input stream to modify
1545 * @src_addr_1: the first 4 bytes of the IP address to load
1546 * @src_addr_2: the second 4 bytes of the IP address to load
1547 * @src_addr_3: the third 4 bytes of the IP address to load
1548 * @src_addr_4: the fourth 4 bytes of the IP address to load
1549 **/
1550 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1551 u32 src_addr_1, u32 src_addr_2,
1552 u32 src_addr_3, u32 src_addr_4)
1553 {
1554 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1555 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1556 (src_addr_4 >> 8) & 0xff;
1557 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1558 (src_addr_4 >> 16) & 0xff;
1559 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1560
1561 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1562 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1563 (src_addr_3 >> 8) & 0xff;
1564 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1565 (src_addr_3 >> 16) & 0xff;
1566 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1567
1568 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1569 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1570 (src_addr_2 >> 8) & 0xff;
1571 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1572 (src_addr_2 >> 16) & 0xff;
1573 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1574
1575 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1576 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1577 (src_addr_1 >> 8) & 0xff;
1578 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1579 (src_addr_1 >> 16) & 0xff;
1580 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1581
1582 return 0;
1583 }
1584
1585 /**
1586 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1587 * @input: input stream to modify
1588 * @dst_addr_1: the first 4 bytes of the IP address to load
1589 * @dst_addr_2: the second 4 bytes of the IP address to load
1590 * @dst_addr_3: the third 4 bytes of the IP address to load
1591 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1592 **/
1593 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1594 u32 dst_addr_1, u32 dst_addr_2,
1595 u32 dst_addr_3, u32 dst_addr_4)
1596 {
1597 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1598 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1599 (dst_addr_4 >> 8) & 0xff;
1600 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1601 (dst_addr_4 >> 16) & 0xff;
1602 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1603
1604 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1605 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1606 (dst_addr_3 >> 8) & 0xff;
1607 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1608 (dst_addr_3 >> 16) & 0xff;
1609 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1610
1611 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1612 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1613 (dst_addr_2 >> 8) & 0xff;
1614 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1615 (dst_addr_2 >> 16) & 0xff;
1616 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1617
1618 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1619 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1620 (dst_addr_1 >> 8) & 0xff;
1621 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1622 (dst_addr_1 >> 16) & 0xff;
1623 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1624
1625 return 0;
1626 }
1627
1628 /**
1629 * ixgbe_atr_set_src_port_82599 - Sets the source port
1630 * @input: input stream to modify
1631 * @src_port: the source port to load
1632 **/
1633 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1634 {
1635 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1636 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1637
1638 return 0;
1639 }
1640
1641 /**
1642 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1643 * @input: input stream to modify
1644 * @dst_port: the destination port to load
1645 **/
1646 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1647 {
1648 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1649 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1650
1651 return 0;
1652 }
1653
1654 /**
1655 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1656 * @input: input stream to modify
1657 * @flex_bytes: the flexible bytes to load
1658 **/
1659 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1660 {
1661 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1662 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1663
1664 return 0;
1665 }
1666
1667 /**
1668 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1669 * @input: input stream to modify
1670 * @vm_pool: the Virtual Machine pool to load
1671 **/
1672 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1673 u8 vm_pool)
1674 {
1675 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1676
1677 return 0;
1678 }
1679
1680 /**
1681 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1682 * @input: input stream to modify
1683 * @l4type: the layer 4 type value to load
1684 **/
1685 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1686 {
1687 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1688
1689 return 0;
1690 }
1691
1692 /**
1693 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1694 * @input: input stream to search
1695 * @vlan: the VLAN id to load
1696 **/
1697 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1698 u16 *vlan)
1699 {
1700 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1701 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1702
1703 return 0;
1704 }
1705
1706 /**
1707 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1708 * @input: input stream to search
1709 * @src_addr: the IP address to load
1710 **/
1711 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1712 u32 *src_addr)
1713 {
1714 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1715 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1716 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1717 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1718
1719 return 0;
1720 }
1721
1722 /**
1723 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1724 * @input: input stream to search
1725 * @dst_addr: the IP address to load
1726 **/
1727 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1728 u32 *dst_addr)
1729 {
1730 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1731 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1732 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1733 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1734
1735 return 0;
1736 }
1737
1738 /**
1739 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1740 * @input: input stream to search
1741 * @src_addr_1: the first 4 bytes of the IP address to load
1742 * @src_addr_2: the second 4 bytes of the IP address to load
1743 * @src_addr_3: the third 4 bytes of the IP address to load
1744 * @src_addr_4: the fourth 4 bytes of the IP address to load
1745 **/
1746 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1747 u32 *src_addr_1, u32 *src_addr_2,
1748 u32 *src_addr_3, u32 *src_addr_4)
1749 {
1750 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1751 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1752 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1753 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1754
1755 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1756 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1757 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1758 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1759
1760 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1761 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1762 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1763 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1764
1765 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1766 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1767 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1768 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1769
1770 return 0;
1771 }
1772
1773 /**
1774 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1775 * @input: input stream to search
1776 * @dst_addr_1: the first 4 bytes of the IP address to load
1777 * @dst_addr_2: the second 4 bytes of the IP address to load
1778 * @dst_addr_3: the third 4 bytes of the IP address to load
1779 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1780 **/
1781 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1782 u32 *dst_addr_1, u32 *dst_addr_2,
1783 u32 *dst_addr_3, u32 *dst_addr_4)
1784 {
1785 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1786 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1787 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1788 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1789
1790 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1791 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1792 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1793 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1794
1795 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1796 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1797 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1798 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1799
1800 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1801 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1802 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1803 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1804
1805 return 0;
1806 }
1807
1808 /**
1809 * ixgbe_atr_get_src_port_82599 - Gets the source port
1810 * @input: input stream to modify
1811 * @src_port: the source port to load
1812 *
1813 * Even though the input is given in big-endian, the FDIRPORT registers
1814 * expect the ports to be programmed in little-endian. Hence the need to swap
1815 * endianness when retrieving the data. This can be confusing since the
1816 * internal hash engine expects it to be big-endian.
1817 **/
1818 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1819 u16 *src_port)
1820 {
1821 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1822 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1823
1824 return 0;
1825 }
1826
1827 /**
1828 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1829 * @input: input stream to modify
1830 * @dst_port: the destination port to load
1831 *
1832 * Even though the input is given in big-endian, the FDIRPORT registers
1833 * expect the ports to be programmed in little-endian. Hence the need to swap
1834 * endianness when retrieving the data. This can be confusing since the
1835 * internal hash engine expects it to be big-endian.
1836 **/
1837 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1838 u16 *dst_port)
1839 {
1840 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1841 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1842
1843 return 0;
1844 }
1845
1846 /**
1847 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1848 * @input: input stream to modify
1849 * @flex_bytes: the flexible bytes to load
1850 **/
1851 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1852 u16 *flex_byte)
1853 {
1854 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1855 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1856
1857 return 0;
1858 }
1859
1860 /**
1861 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1862 * @input: input stream to modify
1863 * @vm_pool: the Virtual Machine pool to load
1864 **/
1865 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1866 u8 *vm_pool)
1867 {
1868 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1869
1870 return 0;
1871 }
1872
1873 /**
1874 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1875 * @input: input stream to modify
1876 * @l4type: the layer 4 type value to load
1877 **/
1878 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1879 u8 *l4type)
1880 {
1881 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1882
1883 return 0;
1884 }
1885
1886 /**
1887 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1888 * @hw: pointer to hardware structure
1889 * @stream: input bitstream
1890 * @queue: queue index to direct traffic to
1891 **/
1892 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1893 struct ixgbe_atr_input *input,
1894 u8 queue)
1895 {
1896 u64 fdirhashcmd;
1897 u64 fdircmd;
1898 u32 fdirhash;
1899 u16 bucket_hash, sig_hash;
1900 u8 l4type;
1901
1902 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1903 IXGBE_ATR_BUCKET_HASH_KEY);
1904
1905 /* bucket_hash is only 15 bits */
1906 bucket_hash &= IXGBE_ATR_HASH_MASK;
1907
1908 sig_hash = ixgbe_atr_compute_hash_82599(input,
1909 IXGBE_ATR_SIGNATURE_HASH_KEY);
1910
1911 /* Get the l4type in order to program FDIRCMD properly */
1912 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1913 ixgbe_atr_get_l4type_82599(input, &l4type);
1914
1915 /*
1916 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1917 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1918 */
1919 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1920
1921 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1922 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1923
1924 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1925 case IXGBE_ATR_L4TYPE_TCP:
1926 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1927 break;
1928 case IXGBE_ATR_L4TYPE_UDP:
1929 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1930 break;
1931 case IXGBE_ATR_L4TYPE_SCTP:
1932 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1933 break;
1934 default:
1935 hw_dbg(hw, "Error on l4type input\n");
1936 return IXGBE_ERR_CONFIG;
1937 }
1938
1939 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1940 fdircmd |= IXGBE_FDIRCMD_IPV6;
1941
1942 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1943 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1944
1945 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1946
1947 return 0;
1948 }
1949
1950 /**
1951 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1952 * @hw: pointer to hardware structure
1953 * @input: input bitstream
1954 * @queue: queue index to direct traffic to
1955 *
1956 * Note that the caller to this function must lock before calling, since the
1957 * hardware writes must be protected from one another.
1958 **/
1959 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1960 struct ixgbe_atr_input *input,
1961 u16 soft_id,
1962 u8 queue)
1963 {
1964 u32 fdircmd = 0;
1965 u32 fdirhash;
1966 u32 src_ipv4, dst_ipv4;
1967 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1968 u16 src_port, dst_port, vlan_id, flex_bytes;
1969 u16 bucket_hash;
1970 u8 l4type;
1971
1972 /* Get our input values */
1973 ixgbe_atr_get_l4type_82599(input, &l4type);
1974
1975 /*
1976 * Check l4type formatting, and bail out before we touch the hardware
1977 * if there's a configuration issue
1978 */
1979 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1980 case IXGBE_ATR_L4TYPE_TCP:
1981 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1982 break;
1983 case IXGBE_ATR_L4TYPE_UDP:
1984 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1985 break;
1986 case IXGBE_ATR_L4TYPE_SCTP:
1987 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1988 break;
1989 default:
1990 hw_dbg(hw, "Error on l4type input\n");
1991 return IXGBE_ERR_CONFIG;
1992 }
1993
1994 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1995 IXGBE_ATR_BUCKET_HASH_KEY);
1996
1997 /* bucket_hash is only 15 bits */
1998 bucket_hash &= IXGBE_ATR_HASH_MASK;
1999
2000 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2001 ixgbe_atr_get_src_port_82599(input, &src_port);
2002 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2003 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2004
2005 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2006
2007 /* Now figure out if we're IPv4 or IPv6 */
2008 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2009 /* IPv6 */
2010 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2011 &src_ipv6_3, &src_ipv6_4);
2012
2013 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2014 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2016 /* The last 4 bytes is the same register as IPv4 */
2017 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2018
2019 fdircmd |= IXGBE_FDIRCMD_IPV6;
2020 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2021 } else {
2022 /* IPv4 */
2023 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2024 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2025
2026 }
2027
2028 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2029 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2030
2031 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2032 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2033 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2034 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2035
2036 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2037 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2038 fdircmd |= IXGBE_FDIRCMD_LAST;
2039 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2040 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2041
2042 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2043 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2044
2045 return 0;
2046 }
2047 /**
2048 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2049 * @hw: pointer to hardware structure
2050 * @reg: analog register to read
2051 * @val: read value
2052 *
2053 * Performs read operation to Omer analog register specified.
2054 **/
2055 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2056 {
2057 u32 core_ctl;
2058
2059 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2060 (reg << 8));
2061 IXGBE_WRITE_FLUSH(hw);
2062 udelay(10);
2063 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2064 *val = (u8)core_ctl;
2065
2066 return 0;
2067 }
2068
2069 /**
2070 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2071 * @hw: pointer to hardware structure
2072 * @reg: atlas register to write
2073 * @val: value to write
2074 *
2075 * Performs write operation to Omer analog register specified.
2076 **/
2077 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2078 {
2079 u32 core_ctl;
2080
2081 core_ctl = (reg << 8) | val;
2082 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2083 IXGBE_WRITE_FLUSH(hw);
2084 udelay(10);
2085
2086 return 0;
2087 }
2088
2089 /**
2090 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2091 * @hw: pointer to hardware structure
2092 *
2093 * Starts the hardware using the generic start_hw function.
2094 * Then performs device-specific:
2095 * Clears the rate limiter registers.
2096 **/
2097 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2098 {
2099 u32 q_num;
2100 s32 ret_val;
2101
2102 ret_val = ixgbe_start_hw_generic(hw);
2103
2104 /* Clear the rate limiters */
2105 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2106 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2107 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2108 }
2109 IXGBE_WRITE_FLUSH(hw);
2110
2111 /* We need to run link autotry after the driver loads */
2112 hw->mac.autotry_restart = true;
2113
2114 if (ret_val == 0)
2115 ret_val = ixgbe_verify_fw_version_82599(hw);
2116
2117 return ret_val;
2118 }
2119
2120 /**
2121 * ixgbe_identify_phy_82599 - Get physical layer module
2122 * @hw: pointer to hardware structure
2123 *
2124 * Determines the physical layer module found on the current adapter.
2125 **/
2126 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2127 {
2128 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2129 status = ixgbe_identify_phy_generic(hw);
2130 if (status != 0)
2131 status = ixgbe_identify_sfp_module_generic(hw);
2132 return status;
2133 }
2134
2135 /**
2136 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2137 * @hw: pointer to hardware structure
2138 *
2139 * Determines physical layer capabilities of the current configuration.
2140 **/
2141 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2142 {
2143 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2144 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2145 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2146 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2147 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2148 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2149 u16 ext_ability = 0;
2150 u8 comp_codes_10g = 0;
2151
2152 hw->phy.ops.identify(hw);
2153
2154 if (hw->phy.type == ixgbe_phy_tn ||
2155 hw->phy.type == ixgbe_phy_cu_unknown) {
2156 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2157 &ext_ability);
2158 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2159 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2160 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2161 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2162 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2163 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2164 goto out;
2165 }
2166
2167 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2168 case IXGBE_AUTOC_LMS_1G_AN:
2169 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2170 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2171 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2172 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2173 goto out;
2174 } else
2175 /* SFI mode so read SFP module */
2176 goto sfp_check;
2177 break;
2178 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2179 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2180 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2181 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2182 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2183 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2185 goto out;
2186 break;
2187 case IXGBE_AUTOC_LMS_10G_SERIAL:
2188 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2189 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2190 goto out;
2191 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2192 goto sfp_check;
2193 break;
2194 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2195 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2196 if (autoc & IXGBE_AUTOC_KX_SUPP)
2197 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2198 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2199 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2200 if (autoc & IXGBE_AUTOC_KR_SUPP)
2201 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2202 goto out;
2203 break;
2204 default:
2205 goto out;
2206 break;
2207 }
2208
2209 sfp_check:
2210 /* SFP check must be done last since DA modules are sometimes used to
2211 * test KR mode - we need to id KR mode correctly before SFP module.
2212 * Call identify_sfp because the pluggable module may have changed */
2213 hw->phy.ops.identify_sfp(hw);
2214 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2215 goto out;
2216
2217 switch (hw->phy.type) {
2218 case ixgbe_phy_tw_tyco:
2219 case ixgbe_phy_tw_unknown:
2220 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2221 break;
2222 case ixgbe_phy_sfp_avago:
2223 case ixgbe_phy_sfp_ftl:
2224 case ixgbe_phy_sfp_intel:
2225 case ixgbe_phy_sfp_unknown:
2226 hw->phy.ops.read_i2c_eeprom(hw,
2227 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2228 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2229 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2230 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2231 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2232 break;
2233 default:
2234 break;
2235 }
2236
2237 out:
2238 return physical_layer;
2239 }
2240
2241 /**
2242 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2243 * @hw: pointer to hardware structure
2244 * @regval: register value to write to RXCTRL
2245 *
2246 * Enables the Rx DMA unit for 82599
2247 **/
2248 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2249 {
2250 #define IXGBE_MAX_SECRX_POLL 30
2251 int i;
2252 int secrxreg;
2253
2254 /*
2255 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2256 * If traffic is incoming before we enable the Rx unit, it could hang
2257 * the Rx DMA unit. Therefore, make sure the security engine is
2258 * completely disabled prior to enabling the Rx unit.
2259 */
2260 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2261 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2262 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2263 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2264 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2265 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2266 break;
2267 else
2268 udelay(10);
2269 }
2270
2271 /* For informational purposes only */
2272 if (i >= IXGBE_MAX_SECRX_POLL)
2273 hw_dbg(hw, "Rx unit being enabled before security "
2274 "path fully disabled. Continuing with init.\n");
2275
2276 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2277 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2278 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2279 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2280 IXGBE_WRITE_FLUSH(hw);
2281
2282 return 0;
2283 }
2284
2285 /**
2286 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2287 * @hw: pointer to hardware structure
2288 * @device_caps: the EEPROM word with the extra device capabilities
2289 *
2290 * This function will read the EEPROM location for the device capabilities,
2291 * and return the word through device_caps.
2292 **/
2293 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2294 {
2295 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2296
2297 return 0;
2298 }
2299
2300 /**
2301 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2302 * @hw: pointer to hardware structure
2303 * @san_mac_offset: SAN MAC address offset
2304 *
2305 * This function will read the EEPROM location for the SAN MAC address
2306 * pointer, and returns the value at that location. This is used in both
2307 * get and set mac_addr routines.
2308 **/
2309 static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2310 u16 *san_mac_offset)
2311 {
2312 /*
2313 * First read the EEPROM pointer to see if the MAC addresses are
2314 * available.
2315 */
2316 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2317
2318 return 0;
2319 }
2320
2321 /**
2322 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2323 * @hw: pointer to hardware structure
2324 * @san_mac_addr: SAN MAC address
2325 *
2326 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2327 * per-port, so set_lan_id() must be called before reading the addresses.
2328 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2329 * upon for non-SFP connections, so we must call it here.
2330 **/
2331 static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2332 {
2333 u16 san_mac_data, san_mac_offset;
2334 u8 i;
2335
2336 /*
2337 * First read the EEPROM pointer to see if the MAC addresses are
2338 * available. If they're not, no point in calling set_lan_id() here.
2339 */
2340 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2341
2342 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2343 /*
2344 * No addresses available in this EEPROM. It's not an
2345 * error though, so just wipe the local address and return.
2346 */
2347 for (i = 0; i < 6; i++)
2348 san_mac_addr[i] = 0xFF;
2349
2350 goto san_mac_addr_out;
2351 }
2352
2353 /* make sure we know which port we need to program */
2354 hw->mac.ops.set_lan_id(hw);
2355 /* apply the port offset to the address offset */
2356 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2357 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2358 for (i = 0; i < 3; i++) {
2359 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2360 san_mac_addr[i * 2] = (u8)(san_mac_data);
2361 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2362 san_mac_offset++;
2363 }
2364
2365 san_mac_addr_out:
2366 return 0;
2367 }
2368
2369 /**
2370 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2371 * @hw: pointer to hardware structure
2372 *
2373 * Verifies that installed the firmware version is 0.6 or higher
2374 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2375 *
2376 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2377 * if the FW version is not supported.
2378 **/
2379 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2380 {
2381 s32 status = IXGBE_ERR_EEPROM_VERSION;
2382 u16 fw_offset, fw_ptp_cfg_offset;
2383 u16 fw_version = 0;
2384
2385 /* firmware check is only necessary for SFI devices */
2386 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2387 status = 0;
2388 goto fw_version_out;
2389 }
2390
2391 /* get the offset to the Firmware Module block */
2392 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2393
2394 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2395 goto fw_version_out;
2396
2397 /* get the offset to the Pass Through Patch Configuration block */
2398 hw->eeprom.ops.read(hw, (fw_offset +
2399 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2400 &fw_ptp_cfg_offset);
2401
2402 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2403 goto fw_version_out;
2404
2405 /* get the firmware version */
2406 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2407 IXGBE_FW_PATCH_VERSION_4),
2408 &fw_version);
2409
2410 if (fw_version > 0x5)
2411 status = 0;
2412
2413 fw_version_out:
2414 return status;
2415 }
2416
2417 static struct ixgbe_mac_operations mac_ops_82599 = {
2418 .init_hw = &ixgbe_init_hw_generic,
2419 .reset_hw = &ixgbe_reset_hw_82599,
2420 .start_hw = &ixgbe_start_hw_82599,
2421 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2422 .get_media_type = &ixgbe_get_media_type_82599,
2423 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2424 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2425 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2426 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
2427 .get_device_caps = &ixgbe_get_device_caps_82599,
2428 .stop_adapter = &ixgbe_stop_adapter_generic,
2429 .get_bus_info = &ixgbe_get_bus_info_generic,
2430 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2431 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2432 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2433 .setup_link = &ixgbe_setup_mac_link_82599,
2434 .check_link = &ixgbe_check_mac_link_82599,
2435 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2436 .led_on = &ixgbe_led_on_generic,
2437 .led_off = &ixgbe_led_off_generic,
2438 .blink_led_start = &ixgbe_blink_led_start_generic,
2439 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2440 .set_rar = &ixgbe_set_rar_generic,
2441 .clear_rar = &ixgbe_clear_rar_generic,
2442 .set_vmdq = &ixgbe_set_vmdq_82599,
2443 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2444 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2445 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2446 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2447 .enable_mc = &ixgbe_enable_mc_generic,
2448 .disable_mc = &ixgbe_disable_mc_generic,
2449 .clear_vfta = &ixgbe_clear_vfta_82599,
2450 .set_vfta = &ixgbe_set_vfta_82599,
2451 .fc_enable = &ixgbe_fc_enable_generic,
2452 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2453 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2454 };
2455
2456 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2457 .init_params = &ixgbe_init_eeprom_params_generic,
2458 .read = &ixgbe_read_eeprom_generic,
2459 .write = &ixgbe_write_eeprom_generic,
2460 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2461 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2462 };
2463
2464 static struct ixgbe_phy_operations phy_ops_82599 = {
2465 .identify = &ixgbe_identify_phy_82599,
2466 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2467 .init = &ixgbe_init_phy_ops_82599,
2468 .reset = &ixgbe_reset_phy_generic,
2469 .read_reg = &ixgbe_read_phy_reg_generic,
2470 .write_reg = &ixgbe_write_phy_reg_generic,
2471 .setup_link = &ixgbe_setup_phy_link_generic,
2472 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2473 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2474 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2475 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2476 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2477 };
2478
2479 struct ixgbe_info ixgbe_82599_info = {
2480 .mac = ixgbe_mac_82599EB,
2481 .get_invariants = &ixgbe_get_invariants_82599,
2482 .mac_ops = &mac_ops_82599,
2483 .eeprom_ops = &eeprom_ops_82599,
2484 .phy_ops = &phy_ops_82599,
2485 };
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