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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / pcmcia / nmclan_cs.c
blob5ed6339c52bcbb6e021e08b334b6e614eacf75f8
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19 References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
50
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
63 4. There is a bad slow-down problem in this driver.
64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68 -------------------------------------------------------------------------------
69 History
70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112 ---------------------------------------------------------------------------- */
113
114 #define DRV_NAME "nmclan_cs"
115 #define DRV_VERSION "0.16"
116
117
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
121
122 #define MULTI_TX 0
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
126
127 /* ----------------------------------------------------------------------------
128 Include Files
129 ---------------------------------------------------------------------------- */
130
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/init.h>
134 #include <linux/ptrace.h>
135 #include <linux/slab.h>
136 #include <linux/string.h>
137 #include <linux/timer.h>
138 #include <linux/interrupt.h>
139 #include <linux/in.h>
140 #include <linux/delay.h>
141 #include <linux/ethtool.h>
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145 #include <linux/if_arp.h>
146 #include <linux/ioport.h>
147 #include <linux/bitops.h>
148
149 #include <pcmcia/cs_types.h>
150 #include <pcmcia/cs.h>
151 #include <pcmcia/cisreg.h>
152 #include <pcmcia/cistpl.h>
153 #include <pcmcia/ds.h>
154
155 #include <asm/uaccess.h>
156 #include <asm/io.h>
157 #include <asm/system.h>
158
159 /* ----------------------------------------------------------------------------
160 Defines
161 ---------------------------------------------------------------------------- */
162
163 #define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165 #define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168 /* Loop Control Defines */
169 #define MACE_MAX_IR_ITERATIONS 10
170 #define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180 /*
181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182 which manages the interface between the MACE and the PCMCIA bus. It
183 also includes buffer management for the 32K x 8 SRAM to control up to
184 four transmit and 12 receive frames at a time.
185 */
186 #define AM2150_MAX_TX_FRAMES 4
187 #define AM2150_MAX_RX_FRAMES 12
188
189 /* Am2150 Ethernet Card I/O Mapping */
190 #define AM2150_RCV 0x00
191 #define AM2150_XMT 0x04
192 #define AM2150_XMT_SKIP 0x09
193 #define AM2150_RCV_NEXT 0x0A
194 #define AM2150_RCV_FRAME_COUNT 0x0B
195 #define AM2150_MACE_BANK 0x0C
196 #define AM2150_MACE_BASE 0x10
197
198 /* MACE Registers */
199 #define MACE_RCVFIFO 0
200 #define MACE_XMTFIFO 1
201 #define MACE_XMTFC 2
202 #define MACE_XMTFS 3
203 #define MACE_XMTRC 4
204 #define MACE_RCVFC 5
205 #define MACE_RCVFS 6
206 #define MACE_FIFOFC 7
207 #define MACE_IR 8
208 #define MACE_IMR 9
209 #define MACE_PR 10
210 #define MACE_BIUCC 11
211 #define MACE_FIFOCC 12
212 #define MACE_MACCC 13
213 #define MACE_PLSCC 14
214 #define MACE_PHYCC 15
215 #define MACE_CHIPIDL 16
216 #define MACE_CHIPIDH 17
217 #define MACE_IAC 18
218 /* Reserved */
219 #define MACE_LADRF 20
220 #define MACE_PADR 21
221 /* Reserved */
222 /* Reserved */
223 #define MACE_MPC 24
224 /* Reserved */
225 #define MACE_RNTPC 26
226 #define MACE_RCVCC 27
227 /* Reserved */
228 #define MACE_UTR 29
229 #define MACE_RTR1 30
230 #define MACE_RTR2 31
231
232 /* MACE Bit Masks */
233 #define MACE_XMTRC_EXDEF 0x80
234 #define MACE_XMTRC_XMTRC 0x0F
235
236 #define MACE_XMTFS_XMTSV 0x80
237 #define MACE_XMTFS_UFLO 0x40
238 #define MACE_XMTFS_LCOL 0x20
239 #define MACE_XMTFS_MORE 0x10
240 #define MACE_XMTFS_ONE 0x08
241 #define MACE_XMTFS_DEFER 0x04
242 #define MACE_XMTFS_LCAR 0x02
243 #define MACE_XMTFS_RTRY 0x01
244
245 #define MACE_RCVFS_RCVSTS 0xF000
246 #define MACE_RCVFS_OFLO 0x8000
247 #define MACE_RCVFS_CLSN 0x4000
248 #define MACE_RCVFS_FRAM 0x2000
249 #define MACE_RCVFS_FCS 0x1000
250
251 #define MACE_FIFOFC_RCVFC 0xF0
252 #define MACE_FIFOFC_XMTFC 0x0F
253
254 #define MACE_IR_JAB 0x80
255 #define MACE_IR_BABL 0x40
256 #define MACE_IR_CERR 0x20
257 #define MACE_IR_RCVCCO 0x10
258 #define MACE_IR_RNTPCO 0x08
259 #define MACE_IR_MPCO 0x04
260 #define MACE_IR_RCVINT 0x02
261 #define MACE_IR_XMTINT 0x01
262
263 #define MACE_MACCC_PROM 0x80
264 #define MACE_MACCC_DXMT2PD 0x40
265 #define MACE_MACCC_EMBA 0x20
266 #define MACE_MACCC_RESERVED 0x10
267 #define MACE_MACCC_DRCVPA 0x08
268 #define MACE_MACCC_DRCVBC 0x04
269 #define MACE_MACCC_ENXMT 0x02
270 #define MACE_MACCC_ENRCV 0x01
271
272 #define MACE_PHYCC_LNKFL 0x80
273 #define MACE_PHYCC_DLNKTST 0x40
274 #define MACE_PHYCC_REVPOL 0x20
275 #define MACE_PHYCC_DAPC 0x10
276 #define MACE_PHYCC_LRT 0x08
277 #define MACE_PHYCC_ASEL 0x04
278 #define MACE_PHYCC_RWAKE 0x02
279 #define MACE_PHYCC_AWAKE 0x01
280
281 #define MACE_IAC_ADDRCHG 0x80
282 #define MACE_IAC_PHYADDR 0x04
283 #define MACE_IAC_LOGADDR 0x02
284
285 #define MACE_UTR_RTRE 0x80
286 #define MACE_UTR_RTRD 0x40
287 #define MACE_UTR_RPA 0x20
288 #define MACE_UTR_FCOLL 0x10
289 #define MACE_UTR_RCVFCSE 0x08
290 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
291 #define MACE_UTR_LOOP_NO_MENDEC 0x04
292 #define MACE_UTR_LOOP_EXTERNAL 0x02
293 #define MACE_UTR_LOOP_NONE 0x00
294 #define MACE_UTR_RESERVED 0x01
295
296 /* Switch MACE register bank (only 0 and 1 are valid) */
297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299 #define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310 #undef MACE_IMR_DEFAULT
311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313 #define TX_TIMEOUT ((400*HZ)/1000)
314
315 /* ----------------------------------------------------------------------------
316 Type Definitions
317 ---------------------------------------------------------------------------- */
318
319 typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362 } mace_statistics;
363
364 typedef struct _mace_private {
365 struct pcmcia_device *p_dev;
366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378 } mace_private;
379
380 /* ----------------------------------------------------------------------------
381 Private Global Variables
382 ---------------------------------------------------------------------------- */
383
384 #ifdef PCMCIA_DEBUG
385 static char rcsid[] =
386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
387 static char *version =
388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
389 #endif
390
391 static const char *if_names[]={
392 "Auto", "10baseT", "BNC",
393 };
394
395 /* ----------------------------------------------------------------------------
396 Parameters
397 These are the parameters that can be set during loading with
398 'insmod'.
399 ---------------------------------------------------------------------------- */
400
401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
402 MODULE_LICENSE("GPL");
403
404 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
405
406 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
407 INT_MODULE_PARM(if_port, 0);
408
409 #ifdef PCMCIA_DEBUG
410 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
411 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
412 #else
413 #define DEBUG(n, args...)
414 #endif
415
416 /* ----------------------------------------------------------------------------
417 Function Prototypes
418 ---------------------------------------------------------------------------- */
419
420 static int nmclan_config(struct pcmcia_device *link);
421 static void nmclan_release(struct pcmcia_device *link);
422
423 static void nmclan_reset(struct net_device *dev);
424 static int mace_config(struct net_device *dev, struct ifmap *map);
425 static int mace_open(struct net_device *dev);
426 static int mace_close(struct net_device *dev);
427 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
428 struct net_device *dev);
429 static void mace_tx_timeout(struct net_device *dev);
430 static irqreturn_t mace_interrupt(int irq, void *dev_id);
431 static struct net_device_stats *mace_get_stats(struct net_device *dev);
432 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
433 static void restore_multicast_list(struct net_device *dev);
434 static void set_multicast_list(struct net_device *dev);
435 static const struct ethtool_ops netdev_ethtool_ops;
436
437
438 static void nmclan_detach(struct pcmcia_device *p_dev);
439
440 static const struct net_device_ops mace_netdev_ops = {
441 .ndo_open = mace_open,
442 .ndo_stop = mace_close,
443 .ndo_start_xmit = mace_start_xmit,
444 .ndo_tx_timeout = mace_tx_timeout,
445 .ndo_set_config = mace_config,
446 .ndo_get_stats = mace_get_stats,
447 .ndo_set_multicast_list = set_multicast_list,
448 .ndo_change_mtu = eth_change_mtu,
449 .ndo_set_mac_address = eth_mac_addr,
450 .ndo_validate_addr = eth_validate_addr,
451 };
452
453 /* ----------------------------------------------------------------------------
454 nmclan_attach
455 Creates an "instance" of the driver, allocating local data
456 structures for one device. The device is registered with Card
457 Services.
458 ---------------------------------------------------------------------------- */
459
460 static int nmclan_probe(struct pcmcia_device *link)
461 {
462 mace_private *lp;
463 struct net_device *dev;
464
465 DEBUG(0, "nmclan_attach()\n");
466 DEBUG(1, "%s\n", rcsid);
467
468 /* Create new ethernet device */
469 dev = alloc_etherdev(sizeof(mace_private));
470 if (!dev)
471 return -ENOMEM;
472 lp = netdev_priv(dev);
473 lp->p_dev = link;
474 link->priv = dev;
475
476 spin_lock_init(&lp->bank_lock);
477 link->io.NumPorts1 = 32;
478 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
479 link->io.IOAddrLines = 5;
480 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
481 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
482 link->irq.Handler = &mace_interrupt;
483 link->irq.Instance = dev;
484 link->conf.Attributes = CONF_ENABLE_IRQ;
485 link->conf.IntType = INT_MEMORY_AND_IO;
486 link->conf.ConfigIndex = 1;
487 link->conf.Present = PRESENT_OPTION;
488
489 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
490
491 dev->netdev_ops = &mace_netdev_ops;
492 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
493 dev->watchdog_timeo = TX_TIMEOUT;
494
495 return nmclan_config(link);
496 } /* nmclan_attach */
497
498 /* ----------------------------------------------------------------------------
499 nmclan_detach
500 This deletes a driver "instance". The device is de-registered
501 with Card Services. If it has been released, all local data
502 structures are freed. Otherwise, the structures will be freed
503 when the device is released.
504 ---------------------------------------------------------------------------- */
505
506 static void nmclan_detach(struct pcmcia_device *link)
507 {
508 struct net_device *dev = link->priv;
509
510 DEBUG(0, "nmclan_detach(0x%p)\n", link);
511
512 if (link->dev_node)
513 unregister_netdev(dev);
514
515 nmclan_release(link);
516
517 free_netdev(dev);
518 } /* nmclan_detach */
519
520 /* ----------------------------------------------------------------------------
521 mace_read
522 Reads a MACE register. This is bank independent; however, the
523 caller must ensure that this call is not interruptable. We are
524 assuming that during normal operation, the MACE is always in
525 bank 0.
526 ---------------------------------------------------------------------------- */
527 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
528 {
529 int data = 0xFF;
530 unsigned long flags;
531
532 switch (reg >> 4) {
533 case 0: /* register 0-15 */
534 data = inb(ioaddr + AM2150_MACE_BASE + reg);
535 break;
536 case 1: /* register 16-31 */
537 spin_lock_irqsave(&lp->bank_lock, flags);
538 MACEBANK(1);
539 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
540 MACEBANK(0);
541 spin_unlock_irqrestore(&lp->bank_lock, flags);
542 break;
543 }
544 return (data & 0xFF);
545 } /* mace_read */
546
547 /* ----------------------------------------------------------------------------
548 mace_write
549 Writes to a MACE register. This is bank independent; however,
550 the caller must ensure that this call is not interruptable. We
551 are assuming that during normal operation, the MACE is always in
552 bank 0.
553 ---------------------------------------------------------------------------- */
554 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
555 int data)
556 {
557 unsigned long flags;
558
559 switch (reg >> 4) {
560 case 0: /* register 0-15 */
561 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
562 break;
563 case 1: /* register 16-31 */
564 spin_lock_irqsave(&lp->bank_lock, flags);
565 MACEBANK(1);
566 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
567 MACEBANK(0);
568 spin_unlock_irqrestore(&lp->bank_lock, flags);
569 break;
570 }
571 } /* mace_write */
572
573 /* ----------------------------------------------------------------------------
574 mace_init
575 Resets the MACE chip.
576 ---------------------------------------------------------------------------- */
577 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
578 {
579 int i;
580 int ct = 0;
581
582 /* MACE Software reset */
583 mace_write(lp, ioaddr, MACE_BIUCC, 1);
584 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
585 /* Wait for reset bit to be cleared automatically after <= 200ns */;
586 if(++ct > 500)
587 {
588 printk(KERN_ERR "mace: reset failed, card removed ?\n");
589 return -1;
590 }
591 udelay(1);
592 }
593 mace_write(lp, ioaddr, MACE_BIUCC, 0);
594
595 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
596 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
597
598 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
599 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
600
601 /*
602 * Bit 2-1 PORTSEL[1-0] Port Select.
603 * 00 AUI/10Base-2
604 * 01 10Base-T
605 * 10 DAI Port (reserved in Am2150)
606 * 11 GPSI
607 * For this card, only the first two are valid.
608 * So, PLSCC should be set to
609 * 0x00 for 10Base-2
610 * 0x02 for 10Base-T
611 * Or just set ASEL in PHYCC below!
612 */
613 switch (if_port) {
614 case 1:
615 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
616 break;
617 case 2:
618 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
619 break;
620 default:
621 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
622 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
623 and the MACE device will automatically select the operating media
624 interface port. */
625 break;
626 }
627
628 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
629 /* Poll ADDRCHG bit */
630 ct = 0;
631 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
632 {
633 if(++ ct > 500)
634 {
635 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
636 return -1;
637 }
638 }
639 /* Set PADR register */
640 for (i = 0; i < ETHER_ADDR_LEN; i++)
641 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
642
643 /* MAC Configuration Control Register should be written last */
644 /* Let set_multicast_list set this. */
645 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
646 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
647 return 0;
648 } /* mace_init */
649
650 /* ----------------------------------------------------------------------------
651 nmclan_config
652 This routine is scheduled to run after a CARD_INSERTION event
653 is received, to configure the PCMCIA socket, and to make the
654 ethernet device available to the system.
655 ---------------------------------------------------------------------------- */
656
657 #define CS_CHECK(fn, ret) \
658 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
659
660 static int nmclan_config(struct pcmcia_device *link)
661 {
662 struct net_device *dev = link->priv;
663 mace_private *lp = netdev_priv(dev);
664 tuple_t tuple;
665 u_char buf[64];
666 int i, last_ret, last_fn;
667 unsigned int ioaddr;
668
669 DEBUG(0, "nmclan_config(0x%p)\n", link);
670
671 CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
672 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
673 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
674 dev->irq = link->irq.AssignedIRQ;
675 dev->base_addr = link->io.BasePort1;
676
677 ioaddr = dev->base_addr;
678
679 /* Read the ethernet address from the CIS. */
680 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
681 tuple.TupleData = buf;
682 tuple.TupleDataMax = 64;
683 tuple.TupleOffset = 0;
684 tuple.Attributes = 0;
685 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
686 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
687 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
688
689 /* Verify configuration by reading the MACE ID. */
690 {
691 char sig[2];
692
693 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
694 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
695 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
696 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
697 sig[0], sig[1]);
698 } else {
699 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
700 " be 0x40 0x?9\n", sig[0], sig[1]);
701 return -ENODEV;
702 }
703 }
704
705 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
706 goto failed;
707
708 /* The if_port symbol can be set when the module is loaded */
709 if (if_port <= 2)
710 dev->if_port = if_port;
711 else
712 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
713
714 link->dev_node = &lp->node;
715 SET_NETDEV_DEV(dev, &handle_to_dev(link));
716
717 i = register_netdev(dev);
718 if (i != 0) {
719 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
720 link->dev_node = NULL;
721 goto failed;
722 }
723
724 strcpy(lp->node.dev_name, dev->name);
725
726 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
727 " hw_addr %pM\n",
728 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
729 dev->dev_addr);
730 return 0;
731
732 cs_failed:
733 cs_error(link, last_fn, last_ret);
734 failed:
735 nmclan_release(link);
736 return -ENODEV;
737 } /* nmclan_config */
738
739 /* ----------------------------------------------------------------------------
740 nmclan_release
741 After a card is removed, nmclan_release() will unregister the
742 net device, and release the PCMCIA configuration. If the device
743 is still open, this will be postponed until it is closed.
744 ---------------------------------------------------------------------------- */
745 static void nmclan_release(struct pcmcia_device *link)
746 {
747 DEBUG(0, "nmclan_release(0x%p)\n", link);
748 pcmcia_disable_device(link);
749 }
750
751 static int nmclan_suspend(struct pcmcia_device *link)
752 {
753 struct net_device *dev = link->priv;
754
755 if (link->open)
756 netif_device_detach(dev);
757
758 return 0;
759 }
760
761 static int nmclan_resume(struct pcmcia_device *link)
762 {
763 struct net_device *dev = link->priv;
764
765 if (link->open) {
766 nmclan_reset(dev);
767 netif_device_attach(dev);
768 }
769
770 return 0;
771 }
772
773
774 /* ----------------------------------------------------------------------------
775 nmclan_reset
776 Reset and restore all of the Xilinx and MACE registers.
777 ---------------------------------------------------------------------------- */
778 static void nmclan_reset(struct net_device *dev)
779 {
780 mace_private *lp = netdev_priv(dev);
781
782 #if RESET_XILINX
783 struct pcmcia_device *link = &lp->link;
784 conf_reg_t reg;
785 u_long OrigCorValue;
786
787 /* Save original COR value */
788 reg.Function = 0;
789 reg.Action = CS_READ;
790 reg.Offset = CISREG_COR;
791 reg.Value = 0;
792 pcmcia_access_configuration_register(link, &reg);
793 OrigCorValue = reg.Value;
794
795 /* Reset Xilinx */
796 reg.Action = CS_WRITE;
797 reg.Offset = CISREG_COR;
798 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
799 OrigCorValue);
800 reg.Value = COR_SOFT_RESET;
801 pcmcia_access_configuration_register(link, &reg);
802 /* Need to wait for 20 ms for PCMCIA to finish reset. */
803
804 /* Restore original COR configuration index */
805 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
806 pcmcia_access_configuration_register(link, &reg);
807 /* Xilinx is now completely reset along with the MACE chip. */
808 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
809
810 #endif /* #if RESET_XILINX */
811
812 /* Xilinx is now completely reset along with the MACE chip. */
813 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
814
815 /* Reinitialize the MACE chip for operation. */
816 mace_init(lp, dev->base_addr, dev->dev_addr);
817 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
818
819 /* Restore the multicast list and enable TX and RX. */
820 restore_multicast_list(dev);
821 } /* nmclan_reset */
822
823 /* ----------------------------------------------------------------------------
824 mace_config
825 [Someone tell me what this is supposed to do? Is if_port a defined
826 standard? If so, there should be defines to indicate 1=10Base-T,
827 2=10Base-2, etc. including limited automatic detection.]
828 ---------------------------------------------------------------------------- */
829 static int mace_config(struct net_device *dev, struct ifmap *map)
830 {
831 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
832 if (map->port <= 2) {
833 dev->if_port = map->port;
834 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
835 if_names[dev->if_port]);
836 } else
837 return -EINVAL;
838 }
839 return 0;
840 } /* mace_config */
841
842 /* ----------------------------------------------------------------------------
843 mace_open
844 Open device driver.
845 ---------------------------------------------------------------------------- */
846 static int mace_open(struct net_device *dev)
847 {
848 unsigned int ioaddr = dev->base_addr;
849 mace_private *lp = netdev_priv(dev);
850 struct pcmcia_device *link = lp->p_dev;
851
852 if (!pcmcia_dev_present(link))
853 return -ENODEV;
854
855 link->open++;
856
857 MACEBANK(0);
858
859 netif_start_queue(dev);
860 nmclan_reset(dev);
861
862 return 0; /* Always succeed */
863 } /* mace_open */
864
865 /* ----------------------------------------------------------------------------
866 mace_close
867 Closes device driver.
868 ---------------------------------------------------------------------------- */
869 static int mace_close(struct net_device *dev)
870 {
871 unsigned int ioaddr = dev->base_addr;
872 mace_private *lp = netdev_priv(dev);
873 struct pcmcia_device *link = lp->p_dev;
874
875 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
876
877 /* Mask off all interrupts from the MACE chip. */
878 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
879
880 link->open--;
881 netif_stop_queue(dev);
882
883 return 0;
884 } /* mace_close */
885
886 static void netdev_get_drvinfo(struct net_device *dev,
887 struct ethtool_drvinfo *info)
888 {
889 strcpy(info->driver, DRV_NAME);
890 strcpy(info->version, DRV_VERSION);
891 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
892 }
893
894 #ifdef PCMCIA_DEBUG
895 static u32 netdev_get_msglevel(struct net_device *dev)
896 {
897 return pc_debug;
898 }
899
900 static void netdev_set_msglevel(struct net_device *dev, u32 level)
901 {
902 pc_debug = level;
903 }
904 #endif /* PCMCIA_DEBUG */
905
906 static const struct ethtool_ops netdev_ethtool_ops = {
907 .get_drvinfo = netdev_get_drvinfo,
908 #ifdef PCMCIA_DEBUG
909 .get_msglevel = netdev_get_msglevel,
910 .set_msglevel = netdev_set_msglevel,
911 #endif /* PCMCIA_DEBUG */
912 };
913
914 /* ----------------------------------------------------------------------------
915 mace_start_xmit
916 This routine begins the packet transmit function. When completed,
917 it will generate a transmit interrupt.
918
919 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
920 returns 0, the "packet is now solely the responsibility of the
921 driver." If _start_xmit returns non-zero, the "transmission
922 failed, put skb back into a list."
923 ---------------------------------------------------------------------------- */
924
925 static void mace_tx_timeout(struct net_device *dev)
926 {
927 mace_private *lp = netdev_priv(dev);
928 struct pcmcia_device *link = lp->p_dev;
929
930 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
931 #if RESET_ON_TIMEOUT
932 printk("resetting card\n");
933 pcmcia_reset_card(link->socket);
934 #else /* #if RESET_ON_TIMEOUT */
935 printk("NOT resetting card\n");
936 #endif /* #if RESET_ON_TIMEOUT */
937 dev->trans_start = jiffies;
938 netif_wake_queue(dev);
939 }
940
941 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
942 struct net_device *dev)
943 {
944 mace_private *lp = netdev_priv(dev);
945 unsigned int ioaddr = dev->base_addr;
946
947 netif_stop_queue(dev);
948
949 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
950 dev->name, (long)skb->len);
951
952 #if (!TX_INTERRUPTABLE)
953 /* Disable MACE TX interrupts. */
954 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
955 ioaddr + AM2150_MACE_BASE + MACE_IMR);
956 lp->tx_irq_disabled=1;
957 #endif /* #if (!TX_INTERRUPTABLE) */
958
959 {
960 /* This block must not be interrupted by another transmit request!
961 mace_tx_timeout will take care of timer-based retransmissions from
962 the upper layers. The interrupt handler is guaranteed never to
963 service a transmit interrupt while we are in here.
964 */
965
966 lp->linux_stats.tx_bytes += skb->len;
967 lp->tx_free_frames--;
968
969 /* WARNING: Write the _exact_ number of bytes written in the header! */
970 /* Put out the word header [must be an outw()] . . . */
971 outw(skb->len, ioaddr + AM2150_XMT);
972 /* . . . and the packet [may be any combination of outw() and outb()] */
973 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
974 if (skb->len & 1) {
975 /* Odd byte transfer */
976 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
977 }
978
979 dev->trans_start = jiffies;
980
981 #if MULTI_TX
982 if (lp->tx_free_frames > 0)
983 netif_start_queue(dev);
984 #endif /* #if MULTI_TX */
985 }
986
987 #if (!TX_INTERRUPTABLE)
988 /* Re-enable MACE TX interrupts. */
989 lp->tx_irq_disabled=0;
990 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
991 #endif /* #if (!TX_INTERRUPTABLE) */
992
993 dev_kfree_skb(skb);
994
995 return NETDEV_TX_OK;
996 } /* mace_start_xmit */
997
998 /* ----------------------------------------------------------------------------
999 mace_interrupt
1000 The interrupt handler.
1001 ---------------------------------------------------------------------------- */
1002 static irqreturn_t mace_interrupt(int irq, void *dev_id)
1003 {
1004 struct net_device *dev = (struct net_device *) dev_id;
1005 mace_private *lp = netdev_priv(dev);
1006 unsigned int ioaddr;
1007 int status;
1008 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1009
1010 if (dev == NULL) {
1011 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1012 irq);
1013 return IRQ_NONE;
1014 }
1015
1016 ioaddr = dev->base_addr;
1017
1018 if (lp->tx_irq_disabled) {
1019 printk(
1020 (lp->tx_irq_disabled?
1021 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1022 "[isr=%02X, imr=%02X]\n":
1023 KERN_NOTICE "%s: Re-entering the interrupt handler "
1024 "[isr=%02X, imr=%02X]\n"),
1025 dev->name,
1026 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1027 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1028 );
1029 /* WARNING: MACE_IR has been read! */
1030 return IRQ_NONE;
1031 }
1032
1033 if (!netif_device_present(dev)) {
1034 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1035 return IRQ_NONE;
1036 }
1037
1038 do {
1039 /* WARNING: MACE_IR is a READ/CLEAR port! */
1040 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1041
1042 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1043
1044 if (status & MACE_IR_RCVINT) {
1045 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1046 }
1047
1048 if (status & MACE_IR_XMTINT) {
1049 unsigned char fifofc;
1050 unsigned char xmtrc;
1051 unsigned char xmtfs;
1052
1053 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1054 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1055 lp->linux_stats.tx_errors++;
1056 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1057 }
1058
1059 /* Transmit Retry Count (XMTRC, reg 4) */
1060 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1061 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1062 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1063
1064 if (
1065 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1066 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1067 ) {
1068 lp->mace_stats.xmtsv++;
1069
1070 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1071 if (xmtfs & MACE_XMTFS_UFLO) {
1072 /* Underflow. Indicates that the Transmit FIFO emptied before
1073 the end of frame was reached. */
1074 lp->mace_stats.uflo++;
1075 }
1076 if (xmtfs & MACE_XMTFS_LCOL) {
1077 /* Late Collision */
1078 lp->mace_stats.lcol++;
1079 }
1080 if (xmtfs & MACE_XMTFS_MORE) {
1081 /* MORE than one retry was needed */
1082 lp->mace_stats.more++;
1083 }
1084 if (xmtfs & MACE_XMTFS_ONE) {
1085 /* Exactly ONE retry occurred */
1086 lp->mace_stats.one++;
1087 }
1088 if (xmtfs & MACE_XMTFS_DEFER) {
1089 /* Transmission was defered */
1090 lp->mace_stats.defer++;
1091 }
1092 if (xmtfs & MACE_XMTFS_LCAR) {
1093 /* Loss of carrier */
1094 lp->mace_stats.lcar++;
1095 }
1096 if (xmtfs & MACE_XMTFS_RTRY) {
1097 /* Retry error: transmit aborted after 16 attempts */
1098 lp->mace_stats.rtry++;
1099 }
1100 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1101
1102 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1103
1104 lp->linux_stats.tx_packets++;
1105 lp->tx_free_frames++;
1106 netif_wake_queue(dev);
1107 } /* if (status & MACE_IR_XMTINT) */
1108
1109 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1110 if (status & MACE_IR_JAB) {
1111 /* Jabber Error. Excessive transmit duration (20-150ms). */
1112 lp->mace_stats.jab++;
1113 }
1114 if (status & MACE_IR_BABL) {
1115 /* Babble Error. >1518 bytes transmitted. */
1116 lp->mace_stats.babl++;
1117 }
1118 if (status & MACE_IR_CERR) {
1119 /* Collision Error. CERR indicates the absence of the
1120 Signal Quality Error Test message after a packet
1121 transmission. */
1122 lp->mace_stats.cerr++;
1123 }
1124 if (status & MACE_IR_RCVCCO) {
1125 /* Receive Collision Count Overflow; */
1126 lp->mace_stats.rcvcco++;
1127 }
1128 if (status & MACE_IR_RNTPCO) {
1129 /* Runt Packet Count Overflow */
1130 lp->mace_stats.rntpco++;
1131 }
1132 if (status & MACE_IR_MPCO) {
1133 /* Missed Packet Count Overflow */
1134 lp->mace_stats.mpco++;
1135 }
1136 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1137
1138 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1139
1140 return IRQ_HANDLED;
1141 } /* mace_interrupt */
1142
1143 /* ----------------------------------------------------------------------------
1144 mace_rx
1145 Receives packets.
1146 ---------------------------------------------------------------------------- */
1147 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1148 {
1149 mace_private *lp = netdev_priv(dev);
1150 unsigned int ioaddr = dev->base_addr;
1151 unsigned char rx_framecnt;
1152 unsigned short rx_status;
1153
1154 while (
1155 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1156 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1157 (RxCnt--)
1158 ) {
1159 rx_status = inw(ioaddr + AM2150_RCV);
1160
1161 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1162 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1163
1164 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1165 lp->linux_stats.rx_errors++;
1166 if (rx_status & MACE_RCVFS_OFLO) {
1167 lp->mace_stats.oflo++;
1168 }
1169 if (rx_status & MACE_RCVFS_CLSN) {
1170 lp->mace_stats.clsn++;
1171 }
1172 if (rx_status & MACE_RCVFS_FRAM) {
1173 lp->mace_stats.fram++;
1174 }
1175 if (rx_status & MACE_RCVFS_FCS) {
1176 lp->mace_stats.fcs++;
1177 }
1178 } else {
1179 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1180 /* Auto Strip is off, always subtract 4 */
1181 struct sk_buff *skb;
1182
1183 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1184 /* runt packet count */
1185 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1186 /* rcv collision count */
1187
1188 DEBUG(3, " receiving packet size 0x%X rx_status"
1189 " 0x%X.\n", pkt_len, rx_status);
1190
1191 skb = dev_alloc_skb(pkt_len+2);
1192
1193 if (skb != NULL) {
1194 skb_reserve(skb, 2);
1195 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1196 if (pkt_len & 1)
1197 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1198 skb->protocol = eth_type_trans(skb, dev);
1199
1200 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1201
1202 lp->linux_stats.rx_packets++;
1203 lp->linux_stats.rx_bytes += pkt_len;
1204 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1205 continue;
1206 } else {
1207 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1208 " %d.\n", dev->name, pkt_len);
1209 lp->linux_stats.rx_dropped++;
1210 }
1211 }
1212 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1213 } /* while */
1214
1215 return 0;
1216 } /* mace_rx */
1217
1218 /* ----------------------------------------------------------------------------
1219 pr_linux_stats
1220 ---------------------------------------------------------------------------- */
1221 static void pr_linux_stats(struct net_device_stats *pstats)
1222 {
1223 DEBUG(2, "pr_linux_stats\n");
1224 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1225 (long)pstats->rx_packets, (long)pstats->tx_packets);
1226 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1227 (long)pstats->rx_errors, (long)pstats->tx_errors);
1228 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1229 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1230 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1231 (long)pstats->multicast, (long)pstats->collisions);
1232
1233 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1234 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1235 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1236 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1237 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1238 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1239
1240 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1241 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1242 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1243 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1244 DEBUG(2, " tx_window_errors=%ld\n",
1245 (long)pstats->tx_window_errors);
1246 } /* pr_linux_stats */
1247
1248 /* ----------------------------------------------------------------------------
1249 pr_mace_stats
1250 ---------------------------------------------------------------------------- */
1251 static void pr_mace_stats(mace_statistics *pstats)
1252 {
1253 DEBUG(2, "pr_mace_stats\n");
1254
1255 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1256 pstats->xmtsv, pstats->uflo);
1257 DEBUG(2, " lcol=%-7d more=%d\n",
1258 pstats->lcol, pstats->more);
1259 DEBUG(2, " one=%-7d defer=%d\n",
1260 pstats->one, pstats->defer);
1261 DEBUG(2, " lcar=%-7d rtry=%d\n",
1262 pstats->lcar, pstats->rtry);
1263
1264 /* MACE_XMTRC */
1265 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1266 pstats->exdef, pstats->xmtrc);
1267
1268 /* RFS1--Receive Status (RCVSTS) */
1269 DEBUG(2, " oflo=%-7d clsn=%d\n",
1270 pstats->oflo, pstats->clsn);
1271 DEBUG(2, " fram=%-7d fcs=%d\n",
1272 pstats->fram, pstats->fcs);
1273
1274 /* RFS2--Runt Packet Count (RNTPC) */
1275 /* RFS3--Receive Collision Count (RCVCC) */
1276 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1277 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1278
1279 /* MACE_IR */
1280 DEBUG(2, " jab=%-7d babl=%d\n",
1281 pstats->jab, pstats->babl);
1282 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1283 pstats->cerr, pstats->rcvcco);
1284 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1285 pstats->rntpco, pstats->mpco);
1286
1287 /* MACE_MPC */
1288 DEBUG(2, " mpc=%d\n", pstats->mpc);
1289
1290 /* MACE_RNTPC */
1291 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1292
1293 /* MACE_RCVCC */
1294 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1295
1296 } /* pr_mace_stats */
1297
1298 /* ----------------------------------------------------------------------------
1299 update_stats
1300 Update statistics. We change to register window 1, so this
1301 should be run single-threaded if the device is active. This is
1302 expected to be a rare operation, and it's simpler for the rest
1303 of the driver to assume that window 0 is always valid rather
1304 than use a special window-state variable.
1305
1306 oflo & uflo should _never_ occur since it would mean the Xilinx
1307 was not able to transfer data between the MACE FIFO and the
1308 card's SRAM fast enough. If this happens, something is
1309 seriously wrong with the hardware.
1310 ---------------------------------------------------------------------------- */
1311 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1312 {
1313 mace_private *lp = netdev_priv(dev);
1314
1315 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1316 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1317 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1318 /* At this point, mace_stats is fully updated for this call.
1319 We may now update the linux_stats. */
1320
1321 /* The MACE has no equivalent for linux_stats field which are commented
1322 out. */
1323
1324 /* lp->linux_stats.multicast; */
1325 lp->linux_stats.collisions =
1326 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1327 /* Collision: The MACE may retry sending a packet 15 times
1328 before giving up. The retry count is in XMTRC.
1329 Does each retry constitute a collision?
1330 If so, why doesn't the RCVCC record these collisions? */
1331
1332 /* detailed rx_errors: */
1333 lp->linux_stats.rx_length_errors =
1334 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1335 /* lp->linux_stats.rx_over_errors */
1336 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1337 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1338 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1339 lp->linux_stats.rx_missed_errors =
1340 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1341
1342 /* detailed tx_errors */
1343 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1344 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1345 /* LCAR usually results from bad cabling. */
1346 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1347 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1348 /* lp->linux_stats.tx_window_errors; */
1349
1350 return;
1351 } /* update_stats */
1352
1353 /* ----------------------------------------------------------------------------
1354 mace_get_stats
1355 Gathers ethernet statistics from the MACE chip.
1356 ---------------------------------------------------------------------------- */
1357 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1358 {
1359 mace_private *lp = netdev_priv(dev);
1360
1361 update_stats(dev->base_addr, dev);
1362
1363 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1364 pr_linux_stats(&lp->linux_stats);
1365 pr_mace_stats(&lp->mace_stats);
1366
1367 return &lp->linux_stats;
1368 } /* net_device_stats */
1369
1370 /* ----------------------------------------------------------------------------
1371 updateCRC
1372 Modified from Am79C90 data sheet.
1373 ---------------------------------------------------------------------------- */
1374
1375 #ifdef BROKEN_MULTICAST
1376
1377 static void updateCRC(int *CRC, int bit)
1378 {
1379 int poly[]={
1380 1,1,1,0, 1,1,0,1,
1381 1,0,1,1, 1,0,0,0,
1382 1,0,0,0, 0,0,1,1,
1383 0,0,1,0, 0,0,0,0
1384 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1385 CRC generator polynomial. */
1386
1387 int j;
1388
1389 /* shift CRC and control bit (CRC[32]) */
1390 for (j = 32; j > 0; j--)
1391 CRC[j] = CRC[j-1];
1392 CRC[0] = 0;
1393
1394 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1395 if (bit ^ CRC[32])
1396 for (j = 0; j < 32; j++)
1397 CRC[j] ^= poly[j];
1398 } /* updateCRC */
1399
1400 /* ----------------------------------------------------------------------------
1401 BuildLAF
1402 Build logical address filter.
1403 Modified from Am79C90 data sheet.
1404
1405 Input
1406 ladrf: logical address filter (contents initialized to 0)
1407 adr: ethernet address
1408 ---------------------------------------------------------------------------- */
1409 static void BuildLAF(int *ladrf, int *adr)
1410 {
1411 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1412
1413 int i, byte; /* temporary array indices */
1414 int hashcode; /* the output object */
1415
1416 CRC[32]=0;
1417
1418 for (byte = 0; byte < 6; byte++)
1419 for (i = 0; i < 8; i++)
1420 updateCRC(CRC, (adr[byte] >> i) & 1);
1421
1422 hashcode = 0;
1423 for (i = 0; i < 6; i++)
1424 hashcode = (hashcode << 1) + CRC[i];
1425
1426 byte = hashcode >> 3;
1427 ladrf[byte] |= (1 << (hashcode & 7));
1428
1429 #ifdef PCMCIA_DEBUG
1430 if (pc_debug > 2)
1431 printk(KERN_DEBUG " adr =%pM\n", adr);
1432 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1433 for (i = 0; i < 8; i++)
1434 printk(KERN_CONT " %02X", ladrf[i]);
1435 printk(KERN_CONT "\n");
1436 }
1437 #endif
1438 } /* BuildLAF */
1439
1440 /* ----------------------------------------------------------------------------
1441 restore_multicast_list
1442 Restores the multicast filter for MACE chip to the last
1443 set_multicast_list() call.
1444
1445 Input
1446 multicast_num_addrs
1447 multicast_ladrf[]
1448 ---------------------------------------------------------------------------- */
1449 static void restore_multicast_list(struct net_device *dev)
1450 {
1451 mace_private *lp = netdev_priv(dev);
1452 int num_addrs = lp->multicast_num_addrs;
1453 int *ladrf = lp->multicast_ladrf;
1454 unsigned int ioaddr = dev->base_addr;
1455 int i;
1456
1457 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1458 dev->name, num_addrs);
1459
1460 if (num_addrs > 0) {
1461
1462 DEBUG(1, "Attempt to restore multicast list detected.\n");
1463
1464 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1465 /* Poll ADDRCHG bit */
1466 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1467 ;
1468 /* Set LADRF register */
1469 for (i = 0; i < MACE_LADRF_LEN; i++)
1470 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1471
1472 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1473 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1474
1475 } else if (num_addrs < 0) {
1476
1477 /* Promiscuous mode: receive all packets */
1478 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1479 mace_write(lp, ioaddr, MACE_MACCC,
1480 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1481 );
1482
1483 } else {
1484
1485 /* Normal mode */
1486 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1487 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1488
1489 }
1490 } /* restore_multicast_list */
1491
1492 /* ----------------------------------------------------------------------------
1493 set_multicast_list
1494 Set or clear the multicast filter for this adaptor.
1495
1496 Input
1497 num_addrs == -1 Promiscuous mode, receive all packets
1498 num_addrs == 0 Normal mode, clear multicast list
1499 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1500 best-effort filtering.
1501 Output
1502 multicast_num_addrs
1503 multicast_ladrf[]
1504 ---------------------------------------------------------------------------- */
1505
1506 static void set_multicast_list(struct net_device *dev)
1507 {
1508 mace_private *lp = netdev_priv(dev);
1509 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1510 int i;
1511 struct dev_mc_list *dmi = dev->mc_list;
1512
1513 #ifdef PCMCIA_DEBUG
1514 if (pc_debug > 1) {
1515 static int old;
1516 if (dev->mc_count != old) {
1517 old = dev->mc_count;
1518 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1519 dev->name, old);
1520 }
1521 }
1522 #endif
1523
1524 /* Set multicast_num_addrs. */
1525 lp->multicast_num_addrs = dev->mc_count;
1526
1527 /* Set multicast_ladrf. */
1528 if (num_addrs > 0) {
1529 /* Calculate multicast logical address filter */
1530 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1531 for (i = 0; i < dev->mc_count; i++) {
1532 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1533 dmi = dmi->next;
1534 BuildLAF(lp->multicast_ladrf, adr);
1535 }
1536 }
1537
1538 restore_multicast_list(dev);
1539
1540 } /* set_multicast_list */
1541
1542 #endif /* BROKEN_MULTICAST */
1543
1544 static void restore_multicast_list(struct net_device *dev)
1545 {
1546 unsigned int ioaddr = dev->base_addr;
1547 mace_private *lp = netdev_priv(dev);
1548
1549 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1550 lp->multicast_num_addrs);
1551
1552 if (dev->flags & IFF_PROMISC) {
1553 /* Promiscuous mode: receive all packets */
1554 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1555 mace_write(lp, ioaddr, MACE_MACCC,
1556 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1557 );
1558 } else {
1559 /* Normal mode */
1560 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1561 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1562 }
1563 } /* restore_multicast_list */
1564
1565 static void set_multicast_list(struct net_device *dev)
1566 {
1567 mace_private *lp = netdev_priv(dev);
1568
1569 #ifdef PCMCIA_DEBUG
1570 if (pc_debug > 1) {
1571 static int old;
1572 if (dev->mc_count != old) {
1573 old = dev->mc_count;
1574 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1575 dev->name, old);
1576 }
1577 }
1578 #endif
1579
1580 lp->multicast_num_addrs = dev->mc_count;
1581 restore_multicast_list(dev);
1582
1583 } /* set_multicast_list */
1584
1585 static struct pcmcia_device_id nmclan_ids[] = {
1586 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1587 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1588 PCMCIA_DEVICE_NULL,
1589 };
1590 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1591
1592 static struct pcmcia_driver nmclan_cs_driver = {
1593 .owner = THIS_MODULE,
1594 .drv = {
1595 .name = "nmclan_cs",
1596 },
1597 .probe = nmclan_probe,
1598 .remove = nmclan_detach,
1599 .id_table = nmclan_ids,
1600 .suspend = nmclan_suspend,
1601 .resume = nmclan_resume,
1602 };
1603
1604 static int __init init_nmclan_cs(void)
1605 {
1606 return pcmcia_register_driver(&nmclan_cs_driver);
1607 }
1608
1609 static void __exit exit_nmclan_cs(void)
1610 {
1611 pcmcia_unregister_driver(&nmclan_cs_driver);
1612 }
1613
1614 module_init(init_nmclan_cs);
1615 module_exit(exit_nmclan_cs);
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