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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / sfc / falcon.c
blobc049364aec46356d271ce6f52fe1ec36555d61ad
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "boards.h"
30 #include "workarounds.h"
31
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37 /**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
42 * @int_error_count: Number of internal errors seen recently
43 * @int_error_expire: Time at which error count will be expired
44 */
45 struct falcon_nic_data {
46 unsigned next_buffer_table;
47 struct pci_dev *pci_dev2;
48 struct i2c_algo_bit_data i2c_data;
49
50 unsigned int_error_count;
51 unsigned long int_error_expire;
52 };
53
54 /**************************************************************************
55 *
56 * Configurable values
57 *
58 **************************************************************************
59 */
60
61 static int disable_dma_stats;
62
63 /* This is set to 16 for a good reason. In summary, if larger than
64 * 16, the descriptor cache holds more than a default socket
65 * buffer's worth of packets (for UDP we can only have at most one
66 * socket buffer's worth outstanding). This combined with the fact
67 * that we only get 1 TX event per descriptor cache means the NIC
68 * goes idle.
69 */
70 #define TX_DC_ENTRIES 16
71 #define TX_DC_ENTRIES_ORDER 0
72 #define TX_DC_BASE 0x130000
73
74 #define RX_DC_ENTRIES 64
75 #define RX_DC_ENTRIES_ORDER 2
76 #define RX_DC_BASE 0x100000
77
78 static const unsigned int
79 /* "Large" EEPROM device: Atmel AT25640 or similar
80 * 8 KB, 16-bit address, 32 B write block */
81 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
82 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
83 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
84 /* Default flash device: Atmel AT25F1024
85 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
86 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
87 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
88 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
89 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
90 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
91
92 /* RX FIFO XOFF watermark
93 *
94 * When the amount of the RX FIFO increases used increases past this
95 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
96 * This also has an effect on RX/TX arbitration
97 */
98 static int rx_xoff_thresh_bytes = -1;
99 module_param(rx_xoff_thresh_bytes, int, 0644);
100 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
101
102 /* RX FIFO XON watermark
103 *
104 * When the amount of the RX FIFO used decreases below this
105 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
106 * This also has an effect on RX/TX arbitration
107 */
108 static int rx_xon_thresh_bytes = -1;
109 module_param(rx_xon_thresh_bytes, int, 0644);
110 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
111
112 /* TX descriptor ring size - min 512 max 4k */
113 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
114 #define FALCON_TXD_RING_SIZE 1024
115 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
116
117 /* RX descriptor ring size - min 512 max 4k */
118 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
119 #define FALCON_RXD_RING_SIZE 1024
120 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
121
122 /* Event queue size - max 32k */
123 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
124 #define FALCON_EVQ_SIZE 4096
125 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
126
127 /* If FALCON_MAX_INT_ERRORS internal errors occur within
128 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
129 * disable it.
130 */
131 #define FALCON_INT_ERROR_EXPIRE 3600
132 #define FALCON_MAX_INT_ERRORS 5
133
134 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
135 */
136 #define FALCON_FLUSH_INTERVAL 10
137 #define FALCON_FLUSH_POLL_COUNT 100
138
139 /**************************************************************************
140 *
141 * Falcon constants
142 *
143 **************************************************************************
144 */
145
146 /* DMA address mask */
147 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
148
149 /* TX DMA length mask (13-bit) */
150 #define FALCON_TX_DMA_MASK (4096 - 1)
151
152 /* Size and alignment of special buffers (4KB) */
153 #define FALCON_BUF_SIZE 4096
154
155 /* Dummy SRAM size code */
156 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
157
158 #define FALCON_IS_DUAL_FUNC(efx) \
159 (falcon_rev(efx) < FALCON_REV_B0)
160
161 /**************************************************************************
162 *
163 * Falcon hardware access
164 *
165 **************************************************************************/
166
167 /* Read the current event from the event queue */
168 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
169 unsigned int index)
170 {
171 return (((efx_qword_t *) (channel->eventq.addr)) + index);
172 }
173
174 /* See if an event is present
175 *
176 * We check both the high and low dword of the event for all ones. We
177 * wrote all ones when we cleared the event, and no valid event can
178 * have all ones in either its high or low dwords. This approach is
179 * robust against reordering.
180 *
181 * Note that using a single 64-bit comparison is incorrect; even
182 * though the CPU read will be atomic, the DMA write may not be.
183 */
184 static inline int falcon_event_present(efx_qword_t *event)
185 {
186 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
187 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
188 }
189
190 /**************************************************************************
191 *
192 * I2C bus - this is a bit-bashing interface using GPIO pins
193 * Note that it uses the output enables to tristate the outputs
194 * SDA is the data pin and SCL is the clock
195 *
196 **************************************************************************
197 */
198 static void falcon_setsda(void *data, int state)
199 {
200 struct efx_nic *efx = (struct efx_nic *)data;
201 efx_oword_t reg;
202
203 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
204 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
205 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
206 }
207
208 static void falcon_setscl(void *data, int state)
209 {
210 struct efx_nic *efx = (struct efx_nic *)data;
211 efx_oword_t reg;
212
213 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
214 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
215 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
216 }
217
218 static int falcon_getsda(void *data)
219 {
220 struct efx_nic *efx = (struct efx_nic *)data;
221 efx_oword_t reg;
222
223 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
224 return EFX_OWORD_FIELD(reg, GPIO3_IN);
225 }
226
227 static int falcon_getscl(void *data)
228 {
229 struct efx_nic *efx = (struct efx_nic *)data;
230 efx_oword_t reg;
231
232 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
233 return EFX_OWORD_FIELD(reg, GPIO0_IN);
234 }
235
236 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
237 .setsda = falcon_setsda,
238 .setscl = falcon_setscl,
239 .getsda = falcon_getsda,
240 .getscl = falcon_getscl,
241 .udelay = 5,
242 /* Wait up to 50 ms for slave to let us pull SCL high */
243 .timeout = DIV_ROUND_UP(HZ, 20),
244 };
245
246 /**************************************************************************
247 *
248 * Falcon special buffer handling
249 * Special buffers are used for event queues and the TX and RX
250 * descriptor rings.
251 *
252 *************************************************************************/
253
254 /*
255 * Initialise a Falcon special buffer
256 *
257 * This will define a buffer (previously allocated via
258 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
259 * it to be used for event queues, descriptor rings etc.
260 */
261 static void
262 falcon_init_special_buffer(struct efx_nic *efx,
263 struct efx_special_buffer *buffer)
264 {
265 efx_qword_t buf_desc;
266 int index;
267 dma_addr_t dma_addr;
268 int i;
269
270 EFX_BUG_ON_PARANOID(!buffer->addr);
271
272 /* Write buffer descriptors to NIC */
273 for (i = 0; i < buffer->entries; i++) {
274 index = buffer->index + i;
275 dma_addr = buffer->dma_addr + (i * 4096);
276 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
277 index, (unsigned long long)dma_addr);
278 EFX_POPULATE_QWORD_4(buf_desc,
279 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
280 BUF_ADR_REGION, 0,
281 BUF_ADR_FBUF, (dma_addr >> 12),
282 BUF_OWNER_ID_FBUF, 0);
283 falcon_write_sram(efx, &buf_desc, index);
284 }
285 }
286
287 /* Unmaps a buffer from Falcon and clears the buffer table entries */
288 static void
289 falcon_fini_special_buffer(struct efx_nic *efx,
290 struct efx_special_buffer *buffer)
291 {
292 efx_oword_t buf_tbl_upd;
293 unsigned int start = buffer->index;
294 unsigned int end = (buffer->index + buffer->entries - 1);
295
296 if (!buffer->entries)
297 return;
298
299 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
300 buffer->index, buffer->index + buffer->entries - 1);
301
302 EFX_POPULATE_OWORD_4(buf_tbl_upd,
303 BUF_UPD_CMD, 0,
304 BUF_CLR_CMD, 1,
305 BUF_CLR_END_ID, end,
306 BUF_CLR_START_ID, start);
307 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
308 }
309
310 /*
311 * Allocate a new Falcon special buffer
312 *
313 * This allocates memory for a new buffer, clears it and allocates a
314 * new buffer ID range. It does not write into Falcon's buffer table.
315 *
316 * This call will allocate 4KB buffers, since Falcon can't use 8KB
317 * buffers for event queues and descriptor rings.
318 */
319 static int falcon_alloc_special_buffer(struct efx_nic *efx,
320 struct efx_special_buffer *buffer,
321 unsigned int len)
322 {
323 struct falcon_nic_data *nic_data = efx->nic_data;
324
325 len = ALIGN(len, FALCON_BUF_SIZE);
326
327 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
328 &buffer->dma_addr);
329 if (!buffer->addr)
330 return -ENOMEM;
331 buffer->len = len;
332 buffer->entries = len / FALCON_BUF_SIZE;
333 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
334
335 /* All zeros is a potentially valid event so memset to 0xff */
336 memset(buffer->addr, 0xff, len);
337
338 /* Select new buffer ID */
339 buffer->index = nic_data->next_buffer_table;
340 nic_data->next_buffer_table += buffer->entries;
341
342 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
343 "(virt %p phys %llx)\n", buffer->index,
344 buffer->index + buffer->entries - 1,
345 (u64)buffer->dma_addr, len,
346 buffer->addr, (u64)virt_to_phys(buffer->addr));
347
348 return 0;
349 }
350
351 static void falcon_free_special_buffer(struct efx_nic *efx,
352 struct efx_special_buffer *buffer)
353 {
354 if (!buffer->addr)
355 return;
356
357 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
358 "(virt %p phys %llx)\n", buffer->index,
359 buffer->index + buffer->entries - 1,
360 (u64)buffer->dma_addr, buffer->len,
361 buffer->addr, (u64)virt_to_phys(buffer->addr));
362
363 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
364 buffer->dma_addr);
365 buffer->addr = NULL;
366 buffer->entries = 0;
367 }
368
369 /**************************************************************************
370 *
371 * Falcon generic buffer handling
372 * These buffers are used for interrupt status and MAC stats
373 *
374 **************************************************************************/
375
376 static int falcon_alloc_buffer(struct efx_nic *efx,
377 struct efx_buffer *buffer, unsigned int len)
378 {
379 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
380 &buffer->dma_addr);
381 if (!buffer->addr)
382 return -ENOMEM;
383 buffer->len = len;
384 memset(buffer->addr, 0, len);
385 return 0;
386 }
387
388 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
389 {
390 if (buffer->addr) {
391 pci_free_consistent(efx->pci_dev, buffer->len,
392 buffer->addr, buffer->dma_addr);
393 buffer->addr = NULL;
394 }
395 }
396
397 /**************************************************************************
398 *
399 * Falcon TX path
400 *
401 **************************************************************************/
402
403 /* Returns a pointer to the specified transmit descriptor in the TX
404 * descriptor queue belonging to the specified channel.
405 */
406 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
407 unsigned int index)
408 {
409 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
410 }
411
412 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
413 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
414 {
415 unsigned write_ptr;
416 efx_dword_t reg;
417
418 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
419 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
420 falcon_writel_page(tx_queue->efx, &reg,
421 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
422 }
423
424
425 /* For each entry inserted into the software descriptor ring, create a
426 * descriptor in the hardware TX descriptor ring (in host memory), and
427 * write a doorbell.
428 */
429 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
430 {
431
432 struct efx_tx_buffer *buffer;
433 efx_qword_t *txd;
434 unsigned write_ptr;
435
436 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
437
438 do {
439 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
440 buffer = &tx_queue->buffer[write_ptr];
441 txd = falcon_tx_desc(tx_queue, write_ptr);
442 ++tx_queue->write_count;
443
444 /* Create TX descriptor ring entry */
445 EFX_POPULATE_QWORD_5(*txd,
446 TX_KER_PORT, 0,
447 TX_KER_CONT, buffer->continuation,
448 TX_KER_BYTE_CNT, buffer->len,
449 TX_KER_BUF_REGION, 0,
450 TX_KER_BUF_ADR, buffer->dma_addr);
451 } while (tx_queue->write_count != tx_queue->insert_count);
452
453 wmb(); /* Ensure descriptors are written before they are fetched */
454 falcon_notify_tx_desc(tx_queue);
455 }
456
457 /* Allocate hardware resources for a TX queue */
458 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
459 {
460 struct efx_nic *efx = tx_queue->efx;
461 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
462 FALCON_TXD_RING_SIZE *
463 sizeof(efx_qword_t));
464 }
465
466 void falcon_init_tx(struct efx_tx_queue *tx_queue)
467 {
468 efx_oword_t tx_desc_ptr;
469 struct efx_nic *efx = tx_queue->efx;
470
471 tx_queue->flushed = false;
472
473 /* Pin TX descriptor ring */
474 falcon_init_special_buffer(efx, &tx_queue->txd);
475
476 /* Push TX descriptor ring to card */
477 EFX_POPULATE_OWORD_10(tx_desc_ptr,
478 TX_DESCQ_EN, 1,
479 TX_ISCSI_DDIG_EN, 0,
480 TX_ISCSI_HDIG_EN, 0,
481 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
482 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
483 TX_DESCQ_OWNER_ID, 0,
484 TX_DESCQ_LABEL, tx_queue->queue,
485 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
486 TX_DESCQ_TYPE, 0,
487 TX_NON_IP_DROP_DIS_B0, 1);
488
489 if (falcon_rev(efx) >= FALCON_REV_B0) {
490 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
491 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
492 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
493 }
494
495 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
496 tx_queue->queue);
497
498 if (falcon_rev(efx) < FALCON_REV_B0) {
499 efx_oword_t reg;
500
501 /* Only 128 bits in this register */
502 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
503
504 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
505 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
506 clear_bit_le(tx_queue->queue, (void *)&reg);
507 else
508 set_bit_le(tx_queue->queue, (void *)&reg);
509 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
510 }
511 }
512
513 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
514 {
515 struct efx_nic *efx = tx_queue->efx;
516 efx_oword_t tx_flush_descq;
517
518 /* Post a flush command */
519 EFX_POPULATE_OWORD_2(tx_flush_descq,
520 TX_FLUSH_DESCQ_CMD, 1,
521 TX_FLUSH_DESCQ, tx_queue->queue);
522 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
523 }
524
525 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
526 {
527 struct efx_nic *efx = tx_queue->efx;
528 efx_oword_t tx_desc_ptr;
529
530 /* The queue should have been flushed */
531 WARN_ON(!tx_queue->flushed);
532
533 /* Remove TX descriptor ring from card */
534 EFX_ZERO_OWORD(tx_desc_ptr);
535 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
536 tx_queue->queue);
537
538 /* Unpin TX descriptor ring */
539 falcon_fini_special_buffer(efx, &tx_queue->txd);
540 }
541
542 /* Free buffers backing TX queue */
543 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
544 {
545 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
546 }
547
548 /**************************************************************************
549 *
550 * Falcon RX path
551 *
552 **************************************************************************/
553
554 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
555 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
556 unsigned int index)
557 {
558 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
559 }
560
561 /* This creates an entry in the RX descriptor queue */
562 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
563 unsigned index)
564 {
565 struct efx_rx_buffer *rx_buf;
566 efx_qword_t *rxd;
567
568 rxd = falcon_rx_desc(rx_queue, index);
569 rx_buf = efx_rx_buffer(rx_queue, index);
570 EFX_POPULATE_QWORD_3(*rxd,
571 RX_KER_BUF_SIZE,
572 rx_buf->len -
573 rx_queue->efx->type->rx_buffer_padding,
574 RX_KER_BUF_REGION, 0,
575 RX_KER_BUF_ADR, rx_buf->dma_addr);
576 }
577
578 /* This writes to the RX_DESC_WPTR register for the specified receive
579 * descriptor ring.
580 */
581 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
582 {
583 efx_dword_t reg;
584 unsigned write_ptr;
585
586 while (rx_queue->notified_count != rx_queue->added_count) {
587 falcon_build_rx_desc(rx_queue,
588 rx_queue->notified_count &
589 FALCON_RXD_RING_MASK);
590 ++rx_queue->notified_count;
591 }
592
593 wmb();
594 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
595 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
596 falcon_writel_page(rx_queue->efx, &reg,
597 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
598 }
599
600 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
601 {
602 struct efx_nic *efx = rx_queue->efx;
603 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
604 FALCON_RXD_RING_SIZE *
605 sizeof(efx_qword_t));
606 }
607
608 void falcon_init_rx(struct efx_rx_queue *rx_queue)
609 {
610 efx_oword_t rx_desc_ptr;
611 struct efx_nic *efx = rx_queue->efx;
612 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
613 bool iscsi_digest_en = is_b0;
614
615 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
616 rx_queue->queue, rx_queue->rxd.index,
617 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
618
619 rx_queue->flushed = false;
620
621 /* Pin RX descriptor ring */
622 falcon_init_special_buffer(efx, &rx_queue->rxd);
623
624 /* Push RX descriptor ring to card */
625 EFX_POPULATE_OWORD_10(rx_desc_ptr,
626 RX_ISCSI_DDIG_EN, iscsi_digest_en,
627 RX_ISCSI_HDIG_EN, iscsi_digest_en,
628 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
629 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
630 RX_DESCQ_OWNER_ID, 0,
631 RX_DESCQ_LABEL, rx_queue->queue,
632 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
633 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
634 /* For >=B0 this is scatter so disable */
635 RX_DESCQ_JUMBO, !is_b0,
636 RX_DESCQ_EN, 1);
637 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
638 rx_queue->queue);
639 }
640
641 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
642 {
643 struct efx_nic *efx = rx_queue->efx;
644 efx_oword_t rx_flush_descq;
645
646 /* Post a flush command */
647 EFX_POPULATE_OWORD_2(rx_flush_descq,
648 RX_FLUSH_DESCQ_CMD, 1,
649 RX_FLUSH_DESCQ, rx_queue->queue);
650 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
651 }
652
653 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
654 {
655 efx_oword_t rx_desc_ptr;
656 struct efx_nic *efx = rx_queue->efx;
657
658 /* The queue should already have been flushed */
659 WARN_ON(!rx_queue->flushed);
660
661 /* Remove RX descriptor ring from card */
662 EFX_ZERO_OWORD(rx_desc_ptr);
663 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
664 rx_queue->queue);
665
666 /* Unpin RX descriptor ring */
667 falcon_fini_special_buffer(efx, &rx_queue->rxd);
668 }
669
670 /* Free buffers backing RX queue */
671 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
672 {
673 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
674 }
675
676 /**************************************************************************
677 *
678 * Falcon event queue processing
679 * Event queues are processed by per-channel tasklets.
680 *
681 **************************************************************************/
682
683 /* Update a channel's event queue's read pointer (RPTR) register
684 *
685 * This writes the EVQ_RPTR_REG register for the specified channel's
686 * event queue.
687 *
688 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
689 * whereas channel->eventq_read_ptr contains the index of the "next to
690 * read" event.
691 */
692 void falcon_eventq_read_ack(struct efx_channel *channel)
693 {
694 efx_dword_t reg;
695 struct efx_nic *efx = channel->efx;
696
697 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
698 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
699 channel->channel);
700 }
701
702 /* Use HW to insert a SW defined event */
703 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
704 {
705 efx_oword_t drv_ev_reg;
706
707 EFX_POPULATE_OWORD_2(drv_ev_reg,
708 DRV_EV_QID, channel->channel,
709 DRV_EV_DATA,
710 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
711 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
712 }
713
714 /* Handle a transmit completion event
715 *
716 * Falcon batches TX completion events; the message we receive is of
717 * the form "complete all TX events up to this index".
718 */
719 static void falcon_handle_tx_event(struct efx_channel *channel,
720 efx_qword_t *event)
721 {
722 unsigned int tx_ev_desc_ptr;
723 unsigned int tx_ev_q_label;
724 struct efx_tx_queue *tx_queue;
725 struct efx_nic *efx = channel->efx;
726
727 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
728 /* Transmit completion */
729 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
730 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
731 tx_queue = &efx->tx_queue[tx_ev_q_label];
732 channel->irq_mod_score +=
733 (tx_ev_desc_ptr - tx_queue->read_count) &
734 efx->type->txd_ring_mask;
735 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
736 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
737 /* Rewrite the FIFO write pointer */
738 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
739 tx_queue = &efx->tx_queue[tx_ev_q_label];
740
741 if (efx_dev_registered(efx))
742 netif_tx_lock(efx->net_dev);
743 falcon_notify_tx_desc(tx_queue);
744 if (efx_dev_registered(efx))
745 netif_tx_unlock(efx->net_dev);
746 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
747 EFX_WORKAROUND_10727(efx)) {
748 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
749 } else {
750 EFX_ERR(efx, "channel %d unexpected TX event "
751 EFX_QWORD_FMT"\n", channel->channel,
752 EFX_QWORD_VAL(*event));
753 }
754 }
755
756 /* Detect errors included in the rx_evt_pkt_ok bit. */
757 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
758 const efx_qword_t *event,
759 bool *rx_ev_pkt_ok,
760 bool *discard)
761 {
762 struct efx_nic *efx = rx_queue->efx;
763 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
764 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
765 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
766 bool rx_ev_other_err, rx_ev_pause_frm;
767 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
768 unsigned rx_ev_pkt_type;
769
770 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
771 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
772 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
773 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
774 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
775 RX_EV_BUF_OWNER_ID_ERR);
776 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
777 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
778 RX_EV_IP_HDR_CHKSUM_ERR);
779 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
780 RX_EV_TCP_UDP_CHKSUM_ERR);
781 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
782 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
783 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
784 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
785 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
786
787 /* Every error apart from tobe_disc and pause_frm */
788 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
789 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
790 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
791
792 /* Count errors that are not in MAC stats. Ignore expected
793 * checksum errors during self-test. */
794 if (rx_ev_frm_trunc)
795 ++rx_queue->channel->n_rx_frm_trunc;
796 else if (rx_ev_tobe_disc)
797 ++rx_queue->channel->n_rx_tobe_disc;
798 else if (!efx->loopback_selftest) {
799 if (rx_ev_ip_hdr_chksum_err)
800 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
801 else if (rx_ev_tcp_udp_chksum_err)
802 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
803 }
804 if (rx_ev_ip_frag_err)
805 ++rx_queue->channel->n_rx_ip_frag_err;
806
807 /* The frame must be discarded if any of these are true. */
808 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
809 rx_ev_tobe_disc | rx_ev_pause_frm);
810
811 /* TOBE_DISC is expected on unicast mismatches; don't print out an
812 * error message. FRM_TRUNC indicates RXDP dropped the packet due
813 * to a FIFO overflow.
814 */
815 #ifdef EFX_ENABLE_DEBUG
816 if (rx_ev_other_err) {
817 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
818 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
819 rx_queue->queue, EFX_QWORD_VAL(*event),
820 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
821 rx_ev_ip_hdr_chksum_err ?
822 " [IP_HDR_CHKSUM_ERR]" : "",
823 rx_ev_tcp_udp_chksum_err ?
824 " [TCP_UDP_CHKSUM_ERR]" : "",
825 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
826 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
827 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
828 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
829 rx_ev_pause_frm ? " [PAUSE]" : "");
830 }
831 #endif
832 }
833
834 /* Handle receive events that are not in-order. */
835 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
836 unsigned index)
837 {
838 struct efx_nic *efx = rx_queue->efx;
839 unsigned expected, dropped;
840
841 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
842 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
843 FALCON_RXD_RING_MASK);
844 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
845 dropped, index, expected);
846
847 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
848 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
849 }
850
851 /* Handle a packet received event
852 *
853 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
854 * wrong destination address
855 * Also "is multicast" and "matches multicast filter" flags can be used to
856 * discard non-matching multicast packets.
857 */
858 static void falcon_handle_rx_event(struct efx_channel *channel,
859 const efx_qword_t *event)
860 {
861 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
862 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
863 unsigned expected_ptr;
864 bool rx_ev_pkt_ok, discard = false, checksummed;
865 struct efx_rx_queue *rx_queue;
866 struct efx_nic *efx = channel->efx;
867
868 /* Basic packet information */
869 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
870 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
871 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
872 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
873 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
874 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
875
876 rx_queue = &efx->rx_queue[channel->channel];
877
878 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
879 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
880 if (unlikely(rx_ev_desc_ptr != expected_ptr))
881 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
882
883 if (likely(rx_ev_pkt_ok)) {
884 /* If packet is marked as OK and packet type is TCP/IPv4 or
885 * UDP/IPv4, then we can rely on the hardware checksum.
886 */
887 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
888 } else {
889 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
890 &discard);
891 checksummed = false;
892 }
893
894 /* Detect multicast packets that didn't match the filter */
895 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
896 if (rx_ev_mcast_pkt) {
897 unsigned int rx_ev_mcast_hash_match =
898 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
899
900 if (unlikely(!rx_ev_mcast_hash_match))
901 discard = true;
902 }
903
904 channel->irq_mod_score += 2;
905
906 /* Handle received packet */
907 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
908 checksummed, discard);
909 }
910
911 /* Global events are basically PHY events */
912 static void falcon_handle_global_event(struct efx_channel *channel,
913 efx_qword_t *event)
914 {
915 struct efx_nic *efx = channel->efx;
916 bool handled = false;
917
918 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
919 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
920 EFX_QWORD_FIELD(*event, XG_PHY_INTR) ||
921 EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
922 efx->phy_op->clear_interrupt(efx);
923 queue_work(efx->workqueue, &efx->phy_work);
924 handled = true;
925 }
926
927 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
928 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) {
929 queue_work(efx->workqueue, &efx->mac_work);
930 handled = true;
931 }
932
933 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
934 EFX_ERR(efx, "channel %d seen global RX_RESET "
935 "event. Resetting.\n", channel->channel);
936
937 atomic_inc(&efx->rx_reset);
938 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
939 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
940 handled = true;
941 }
942
943 if (!handled)
944 EFX_ERR(efx, "channel %d unknown global event "
945 EFX_QWORD_FMT "\n", channel->channel,
946 EFX_QWORD_VAL(*event));
947 }
948
949 static void falcon_handle_driver_event(struct efx_channel *channel,
950 efx_qword_t *event)
951 {
952 struct efx_nic *efx = channel->efx;
953 unsigned int ev_sub_code;
954 unsigned int ev_sub_data;
955
956 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
957 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
958
959 switch (ev_sub_code) {
960 case TX_DESCQ_FLS_DONE_EV_DECODE:
961 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
962 channel->channel, ev_sub_data);
963 break;
964 case RX_DESCQ_FLS_DONE_EV_DECODE:
965 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
966 channel->channel, ev_sub_data);
967 break;
968 case EVQ_INIT_DONE_EV_DECODE:
969 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
970 channel->channel, ev_sub_data);
971 break;
972 case SRM_UPD_DONE_EV_DECODE:
973 EFX_TRACE(efx, "channel %d SRAM update done\n",
974 channel->channel);
975 break;
976 case WAKE_UP_EV_DECODE:
977 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
978 channel->channel, ev_sub_data);
979 break;
980 case TIMER_EV_DECODE:
981 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
982 channel->channel, ev_sub_data);
983 break;
984 case RX_RECOVERY_EV_DECODE:
985 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
986 "Resetting.\n", channel->channel);
987 atomic_inc(&efx->rx_reset);
988 efx_schedule_reset(efx,
989 EFX_WORKAROUND_6555(efx) ?
990 RESET_TYPE_RX_RECOVERY :
991 RESET_TYPE_DISABLE);
992 break;
993 case RX_DSC_ERROR_EV_DECODE:
994 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
995 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
996 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
997 break;
998 case TX_DSC_ERROR_EV_DECODE:
999 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1000 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1001 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1002 break;
1003 default:
1004 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1005 "data %04x\n", channel->channel, ev_sub_code,
1006 ev_sub_data);
1007 break;
1008 }
1009 }
1010
1011 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1012 {
1013 unsigned int read_ptr;
1014 efx_qword_t event, *p_event;
1015 int ev_code;
1016 int rx_packets = 0;
1017
1018 read_ptr = channel->eventq_read_ptr;
1019
1020 do {
1021 p_event = falcon_event(channel, read_ptr);
1022 event = *p_event;
1023
1024 if (!falcon_event_present(&event))
1025 /* End of events */
1026 break;
1027
1028 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1029 channel->channel, EFX_QWORD_VAL(event));
1030
1031 /* Clear this event by marking it all ones */
1032 EFX_SET_QWORD(*p_event);
1033
1034 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1035
1036 switch (ev_code) {
1037 case RX_IP_EV_DECODE:
1038 falcon_handle_rx_event(channel, &event);
1039 ++rx_packets;
1040 break;
1041 case TX_IP_EV_DECODE:
1042 falcon_handle_tx_event(channel, &event);
1043 break;
1044 case DRV_GEN_EV_DECODE:
1045 channel->eventq_magic
1046 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1047 EFX_LOG(channel->efx, "channel %d received generated "
1048 "event "EFX_QWORD_FMT"\n", channel->channel,
1049 EFX_QWORD_VAL(event));
1050 break;
1051 case GLOBAL_EV_DECODE:
1052 falcon_handle_global_event(channel, &event);
1053 break;
1054 case DRIVER_EV_DECODE:
1055 falcon_handle_driver_event(channel, &event);
1056 break;
1057 default:
1058 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1059 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1060 ev_code, EFX_QWORD_VAL(event));
1061 }
1062
1063 /* Increment read pointer */
1064 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1065
1066 } while (rx_packets < rx_quota);
1067
1068 channel->eventq_read_ptr = read_ptr;
1069 return rx_packets;
1070 }
1071
1072 void falcon_set_int_moderation(struct efx_channel *channel)
1073 {
1074 efx_dword_t timer_cmd;
1075 struct efx_nic *efx = channel->efx;
1076
1077 /* Set timer register */
1078 if (channel->irq_moderation) {
1079 /* Round to resolution supported by hardware. The value we
1080 * program is based at 0. So actual interrupt moderation
1081 * achieved is ((x + 1) * res).
1082 */
1083 channel->irq_moderation -= (channel->irq_moderation %
1084 FALCON_IRQ_MOD_RESOLUTION);
1085 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1086 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1087 EFX_POPULATE_DWORD_2(timer_cmd,
1088 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1089 TIMER_VAL,
1090 channel->irq_moderation /
1091 FALCON_IRQ_MOD_RESOLUTION - 1);
1092 } else {
1093 EFX_POPULATE_DWORD_2(timer_cmd,
1094 TIMER_MODE, TIMER_MODE_DIS,
1095 TIMER_VAL, 0);
1096 }
1097 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1098 channel->channel);
1099
1100 }
1101
1102 /* Allocate buffer table entries for event queue */
1103 int falcon_probe_eventq(struct efx_channel *channel)
1104 {
1105 struct efx_nic *efx = channel->efx;
1106 unsigned int evq_size;
1107
1108 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1109 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1110 }
1111
1112 void falcon_init_eventq(struct efx_channel *channel)
1113 {
1114 efx_oword_t evq_ptr;
1115 struct efx_nic *efx = channel->efx;
1116
1117 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1118 channel->channel, channel->eventq.index,
1119 channel->eventq.index + channel->eventq.entries - 1);
1120
1121 /* Pin event queue buffer */
1122 falcon_init_special_buffer(efx, &channel->eventq);
1123
1124 /* Fill event queue with all ones (i.e. empty events) */
1125 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1126
1127 /* Push event queue to card */
1128 EFX_POPULATE_OWORD_3(evq_ptr,
1129 EVQ_EN, 1,
1130 EVQ_SIZE, FALCON_EVQ_ORDER,
1131 EVQ_BUF_BASE_ID, channel->eventq.index);
1132 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1133 channel->channel);
1134
1135 falcon_set_int_moderation(channel);
1136 }
1137
1138 void falcon_fini_eventq(struct efx_channel *channel)
1139 {
1140 efx_oword_t eventq_ptr;
1141 struct efx_nic *efx = channel->efx;
1142
1143 /* Remove event queue from card */
1144 EFX_ZERO_OWORD(eventq_ptr);
1145 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1146 channel->channel);
1147
1148 /* Unpin event queue */
1149 falcon_fini_special_buffer(efx, &channel->eventq);
1150 }
1151
1152 /* Free buffers backing event queue */
1153 void falcon_remove_eventq(struct efx_channel *channel)
1154 {
1155 falcon_free_special_buffer(channel->efx, &channel->eventq);
1156 }
1157
1158
1159 /* Generates a test event on the event queue. A subsequent call to
1160 * process_eventq() should pick up the event and place the value of
1161 * "magic" into channel->eventq_magic;
1162 */
1163 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1164 {
1165 efx_qword_t test_event;
1166
1167 EFX_POPULATE_QWORD_2(test_event,
1168 EV_CODE, DRV_GEN_EV_DECODE,
1169 EVQ_MAGIC, magic);
1170 falcon_generate_event(channel, &test_event);
1171 }
1172
1173 void falcon_sim_phy_event(struct efx_nic *efx)
1174 {
1175 efx_qword_t phy_event;
1176
1177 EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1178 if (EFX_IS10G(efx))
1179 EFX_SET_QWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1180 else
1181 EFX_SET_QWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1182
1183 falcon_generate_event(&efx->channel[0], &phy_event);
1184 }
1185
1186 /**************************************************************************
1187 *
1188 * Flush handling
1189 *
1190 **************************************************************************/
1191
1192
1193 static void falcon_poll_flush_events(struct efx_nic *efx)
1194 {
1195 struct efx_channel *channel = &efx->channel[0];
1196 struct efx_tx_queue *tx_queue;
1197 struct efx_rx_queue *rx_queue;
1198 unsigned int read_ptr = channel->eventq_read_ptr;
1199 unsigned int end_ptr = (read_ptr - 1) & FALCON_EVQ_MASK;
1200
1201 do {
1202 efx_qword_t *event = falcon_event(channel, read_ptr);
1203 int ev_code, ev_sub_code, ev_queue;
1204 bool ev_failed;
1205
1206 if (!falcon_event_present(event))
1207 break;
1208
1209 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1210 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1211 if (ev_code == DRIVER_EV_DECODE &&
1212 ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) {
1213 ev_queue = EFX_QWORD_FIELD(*event,
1214 DRIVER_EV_TX_DESCQ_ID);
1215 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1216 tx_queue = efx->tx_queue + ev_queue;
1217 tx_queue->flushed = true;
1218 }
1219 } else if (ev_code == DRIVER_EV_DECODE &&
1220 ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) {
1221 ev_queue = EFX_QWORD_FIELD(*event,
1222 DRIVER_EV_RX_DESCQ_ID);
1223 ev_failed = EFX_QWORD_FIELD(*event,
1224 DRIVER_EV_RX_FLUSH_FAIL);
1225 if (ev_queue < efx->n_rx_queues) {
1226 rx_queue = efx->rx_queue + ev_queue;
1227
1228 /* retry the rx flush */
1229 if (ev_failed)
1230 falcon_flush_rx_queue(rx_queue);
1231 else
1232 rx_queue->flushed = true;
1233 }
1234 }
1235
1236 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1237 } while (read_ptr != end_ptr);
1238 }
1239
1240 /* Handle tx and rx flushes at the same time, since they run in
1241 * parallel in the hardware and there's no reason for us to
1242 * serialise them */
1243 int falcon_flush_queues(struct efx_nic *efx)
1244 {
1245 struct efx_rx_queue *rx_queue;
1246 struct efx_tx_queue *tx_queue;
1247 int i;
1248 bool outstanding;
1249
1250 /* Issue flush requests */
1251 efx_for_each_tx_queue(tx_queue, efx) {
1252 tx_queue->flushed = false;
1253 falcon_flush_tx_queue(tx_queue);
1254 }
1255 efx_for_each_rx_queue(rx_queue, efx) {
1256 rx_queue->flushed = false;
1257 falcon_flush_rx_queue(rx_queue);
1258 }
1259
1260 /* Poll the evq looking for flush completions. Since we're not pushing
1261 * any more rx or tx descriptors at this point, we're in no danger of
1262 * overflowing the evq whilst we wait */
1263 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1264 msleep(FALCON_FLUSH_INTERVAL);
1265 falcon_poll_flush_events(efx);
1266
1267 /* Check if every queue has been succesfully flushed */
1268 outstanding = false;
1269 efx_for_each_tx_queue(tx_queue, efx)
1270 outstanding |= !tx_queue->flushed;
1271 efx_for_each_rx_queue(rx_queue, efx)
1272 outstanding |= !rx_queue->flushed;
1273 if (!outstanding)
1274 return 0;
1275 }
1276
1277 /* Mark the queues as all flushed. We're going to return failure
1278 * leading to a reset, or fake up success anyway. "flushed" now
1279 * indicates that we tried to flush. */
1280 efx_for_each_tx_queue(tx_queue, efx) {
1281 if (!tx_queue->flushed)
1282 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1283 tx_queue->queue);
1284 tx_queue->flushed = true;
1285 }
1286 efx_for_each_rx_queue(rx_queue, efx) {
1287 if (!rx_queue->flushed)
1288 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1289 rx_queue->queue);
1290 rx_queue->flushed = true;
1291 }
1292
1293 if (EFX_WORKAROUND_7803(efx))
1294 return 0;
1295
1296 return -ETIMEDOUT;
1297 }
1298
1299 /**************************************************************************
1300 *
1301 * Falcon hardware interrupts
1302 * The hardware interrupt handler does very little work; all the event
1303 * queue processing is carried out by per-channel tasklets.
1304 *
1305 **************************************************************************/
1306
1307 /* Enable/disable/generate Falcon interrupts */
1308 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1309 int force)
1310 {
1311 efx_oword_t int_en_reg_ker;
1312
1313 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1314 KER_INT_KER, force,
1315 DRV_INT_EN_KER, enabled);
1316 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1317 }
1318
1319 void falcon_enable_interrupts(struct efx_nic *efx)
1320 {
1321 efx_oword_t int_adr_reg_ker;
1322 struct efx_channel *channel;
1323
1324 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1325 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1326
1327 /* Program address */
1328 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1329 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1330 INT_ADR_KER, efx->irq_status.dma_addr);
1331 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1332
1333 /* Enable interrupts */
1334 falcon_interrupts(efx, 1, 0);
1335
1336 /* Force processing of all the channels to get the EVQ RPTRs up to
1337 date */
1338 efx_for_each_channel(channel, efx)
1339 efx_schedule_channel(channel);
1340 }
1341
1342 void falcon_disable_interrupts(struct efx_nic *efx)
1343 {
1344 /* Disable interrupts */
1345 falcon_interrupts(efx, 0, 0);
1346 }
1347
1348 /* Generate a Falcon test interrupt
1349 * Interrupt must already have been enabled, otherwise nasty things
1350 * may happen.
1351 */
1352 void falcon_generate_interrupt(struct efx_nic *efx)
1353 {
1354 falcon_interrupts(efx, 1, 1);
1355 }
1356
1357 /* Acknowledge a legacy interrupt from Falcon
1358 *
1359 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1360 *
1361 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1362 * BIU. Interrupt acknowledge is read sensitive so must write instead
1363 * (then read to ensure the BIU collector is flushed)
1364 *
1365 * NB most hardware supports MSI interrupts
1366 */
1367 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1368 {
1369 efx_dword_t reg;
1370
1371 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1372 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1373 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1374 }
1375
1376 /* Process a fatal interrupt
1377 * Disable bus mastering ASAP and schedule a reset
1378 */
1379 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1380 {
1381 struct falcon_nic_data *nic_data = efx->nic_data;
1382 efx_oword_t *int_ker = efx->irq_status.addr;
1383 efx_oword_t fatal_intr;
1384 int error, mem_perr;
1385
1386 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1387 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1388
1389 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1390 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1391 EFX_OWORD_VAL(fatal_intr),
1392 error ? "disabling bus mastering" : "no recognised error");
1393 if (error == 0)
1394 goto out;
1395
1396 /* If this is a memory parity error dump which blocks are offending */
1397 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1398 if (mem_perr) {
1399 efx_oword_t reg;
1400 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1401 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1402 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1403 }
1404
1405 /* Disable both devices */
1406 pci_clear_master(efx->pci_dev);
1407 if (FALCON_IS_DUAL_FUNC(efx))
1408 pci_clear_master(nic_data->pci_dev2);
1409 falcon_disable_interrupts(efx);
1410
1411 /* Count errors and reset or disable the NIC accordingly */
1412 if (nic_data->int_error_count == 0 ||
1413 time_after(jiffies, nic_data->int_error_expire)) {
1414 nic_data->int_error_count = 0;
1415 nic_data->int_error_expire =
1416 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1417 }
1418 if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1419 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1420 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1421 } else {
1422 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1423 "NIC will be disabled\n");
1424 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1425 }
1426 out:
1427 return IRQ_HANDLED;
1428 }
1429
1430 /* Handle a legacy interrupt from Falcon
1431 * Acknowledges the interrupt and schedule event queue processing.
1432 */
1433 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1434 {
1435 struct efx_nic *efx = dev_id;
1436 efx_oword_t *int_ker = efx->irq_status.addr;
1437 irqreturn_t result = IRQ_NONE;
1438 struct efx_channel *channel;
1439 efx_dword_t reg;
1440 u32 queues;
1441 int syserr;
1442
1443 /* Read the ISR which also ACKs the interrupts */
1444 falcon_readl(efx, &reg, INT_ISR0_B0);
1445 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1446
1447 /* Check to see if we have a serious error condition */
1448 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1449 if (unlikely(syserr))
1450 return falcon_fatal_interrupt(efx);
1451
1452 /* Schedule processing of any interrupting queues */
1453 efx_for_each_channel(channel, efx) {
1454 if ((queues & 1) ||
1455 falcon_event_present(
1456 falcon_event(channel, channel->eventq_read_ptr))) {
1457 efx_schedule_channel(channel);
1458 result = IRQ_HANDLED;
1459 }
1460 queues >>= 1;
1461 }
1462
1463 if (result == IRQ_HANDLED) {
1464 efx->last_irq_cpu = raw_smp_processor_id();
1465 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1466 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1467 }
1468
1469 return result;
1470 }
1471
1472
1473 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1474 {
1475 struct efx_nic *efx = dev_id;
1476 efx_oword_t *int_ker = efx->irq_status.addr;
1477 struct efx_channel *channel;
1478 int syserr;
1479 int queues;
1480
1481 /* Check to see if this is our interrupt. If it isn't, we
1482 * exit without having touched the hardware.
1483 */
1484 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1485 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1486 raw_smp_processor_id());
1487 return IRQ_NONE;
1488 }
1489 efx->last_irq_cpu = raw_smp_processor_id();
1490 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1491 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1492
1493 /* Check to see if we have a serious error condition */
1494 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1495 if (unlikely(syserr))
1496 return falcon_fatal_interrupt(efx);
1497
1498 /* Determine interrupting queues, clear interrupt status
1499 * register and acknowledge the device interrupt.
1500 */
1501 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1502 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1503 EFX_ZERO_OWORD(*int_ker);
1504 wmb(); /* Ensure the vector is cleared before interrupt ack */
1505 falcon_irq_ack_a1(efx);
1506
1507 /* Schedule processing of any interrupting queues */
1508 channel = &efx->channel[0];
1509 while (queues) {
1510 if (queues & 0x01)
1511 efx_schedule_channel(channel);
1512 channel++;
1513 queues >>= 1;
1514 }
1515
1516 return IRQ_HANDLED;
1517 }
1518
1519 /* Handle an MSI interrupt from Falcon
1520 *
1521 * Handle an MSI hardware interrupt. This routine schedules event
1522 * queue processing. No interrupt acknowledgement cycle is necessary.
1523 * Also, we never need to check that the interrupt is for us, since
1524 * MSI interrupts cannot be shared.
1525 */
1526 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1527 {
1528 struct efx_channel *channel = dev_id;
1529 struct efx_nic *efx = channel->efx;
1530 efx_oword_t *int_ker = efx->irq_status.addr;
1531 int syserr;
1532
1533 efx->last_irq_cpu = raw_smp_processor_id();
1534 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1535 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1536
1537 /* Check to see if we have a serious error condition */
1538 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1539 if (unlikely(syserr))
1540 return falcon_fatal_interrupt(efx);
1541
1542 /* Schedule processing of the channel */
1543 efx_schedule_channel(channel);
1544
1545 return IRQ_HANDLED;
1546 }
1547
1548
1549 /* Setup RSS indirection table.
1550 * This maps from the hash value of the packet to RXQ
1551 */
1552 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1553 {
1554 int i = 0;
1555 unsigned long offset;
1556 efx_dword_t dword;
1557
1558 if (falcon_rev(efx) < FALCON_REV_B0)
1559 return;
1560
1561 for (offset = RX_RSS_INDIR_TBL_B0;
1562 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1563 offset += 0x10) {
1564 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1565 i % efx->n_rx_queues);
1566 falcon_writel(efx, &dword, offset);
1567 i++;
1568 }
1569 }
1570
1571 /* Hook interrupt handler(s)
1572 * Try MSI and then legacy interrupts.
1573 */
1574 int falcon_init_interrupt(struct efx_nic *efx)
1575 {
1576 struct efx_channel *channel;
1577 int rc;
1578
1579 if (!EFX_INT_MODE_USE_MSI(efx)) {
1580 irq_handler_t handler;
1581 if (falcon_rev(efx) >= FALCON_REV_B0)
1582 handler = falcon_legacy_interrupt_b0;
1583 else
1584 handler = falcon_legacy_interrupt_a1;
1585
1586 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1587 efx->name, efx);
1588 if (rc) {
1589 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1590 efx->pci_dev->irq);
1591 goto fail1;
1592 }
1593 return 0;
1594 }
1595
1596 /* Hook MSI or MSI-X interrupt */
1597 efx_for_each_channel(channel, efx) {
1598 rc = request_irq(channel->irq, falcon_msi_interrupt,
1599 IRQF_PROBE_SHARED, /* Not shared */
1600 channel->name, channel);
1601 if (rc) {
1602 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1603 goto fail2;
1604 }
1605 }
1606
1607 return 0;
1608
1609 fail2:
1610 efx_for_each_channel(channel, efx)
1611 free_irq(channel->irq, channel);
1612 fail1:
1613 return rc;
1614 }
1615
1616 void falcon_fini_interrupt(struct efx_nic *efx)
1617 {
1618 struct efx_channel *channel;
1619 efx_oword_t reg;
1620
1621 /* Disable MSI/MSI-X interrupts */
1622 efx_for_each_channel(channel, efx) {
1623 if (channel->irq)
1624 free_irq(channel->irq, channel);
1625 }
1626
1627 /* ACK legacy interrupt */
1628 if (falcon_rev(efx) >= FALCON_REV_B0)
1629 falcon_read(efx, &reg, INT_ISR0_B0);
1630 else
1631 falcon_irq_ack_a1(efx);
1632
1633 /* Disable legacy interrupt */
1634 if (efx->legacy_irq)
1635 free_irq(efx->legacy_irq, efx);
1636 }
1637
1638 /**************************************************************************
1639 *
1640 * EEPROM/flash
1641 *
1642 **************************************************************************
1643 */
1644
1645 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1646
1647 static int falcon_spi_poll(struct efx_nic *efx)
1648 {
1649 efx_oword_t reg;
1650 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1651 return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1652 }
1653
1654 /* Wait for SPI command completion */
1655 static int falcon_spi_wait(struct efx_nic *efx)
1656 {
1657 /* Most commands will finish quickly, so we start polling at
1658 * very short intervals. Sometimes the command may have to
1659 * wait for VPD or expansion ROM access outside of our
1660 * control, so we allow up to 100 ms. */
1661 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1662 int i;
1663
1664 for (i = 0; i < 10; i++) {
1665 if (!falcon_spi_poll(efx))
1666 return 0;
1667 udelay(10);
1668 }
1669
1670 for (;;) {
1671 if (!falcon_spi_poll(efx))
1672 return 0;
1673 if (time_after_eq(jiffies, timeout)) {
1674 EFX_ERR(efx, "timed out waiting for SPI\n");
1675 return -ETIMEDOUT;
1676 }
1677 schedule_timeout_uninterruptible(1);
1678 }
1679 }
1680
1681 int falcon_spi_cmd(const struct efx_spi_device *spi,
1682 unsigned int command, int address,
1683 const void *in, void *out, size_t len)
1684 {
1685 struct efx_nic *efx = spi->efx;
1686 bool addressed = (address >= 0);
1687 bool reading = (out != NULL);
1688 efx_oword_t reg;
1689 int rc;
1690
1691 /* Input validation */
1692 if (len > FALCON_SPI_MAX_LEN)
1693 return -EINVAL;
1694 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1695
1696 /* Check that previous command is not still running */
1697 rc = falcon_spi_poll(efx);
1698 if (rc)
1699 return rc;
1700
1701 /* Program address register, if we have an address */
1702 if (addressed) {
1703 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1704 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1705 }
1706
1707 /* Program data register, if we have data */
1708 if (in != NULL) {
1709 memcpy(&reg, in, len);
1710 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1711 }
1712
1713 /* Issue read/write command */
1714 EFX_POPULATE_OWORD_7(reg,
1715 EE_SPI_HCMD_CMD_EN, 1,
1716 EE_SPI_HCMD_SF_SEL, spi->device_id,
1717 EE_SPI_HCMD_DABCNT, len,
1718 EE_SPI_HCMD_READ, reading,
1719 EE_SPI_HCMD_DUBCNT, 0,
1720 EE_SPI_HCMD_ADBCNT,
1721 (addressed ? spi->addr_len : 0),
1722 EE_SPI_HCMD_ENC, command);
1723 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1724
1725 /* Wait for read/write to complete */
1726 rc = falcon_spi_wait(efx);
1727 if (rc)
1728 return rc;
1729
1730 /* Read data */
1731 if (out != NULL) {
1732 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1733 memcpy(out, &reg, len);
1734 }
1735
1736 return 0;
1737 }
1738
1739 static size_t
1740 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1741 {
1742 return min(FALCON_SPI_MAX_LEN,
1743 (spi->block_size - (start & (spi->block_size - 1))));
1744 }
1745
1746 static inline u8
1747 efx_spi_munge_command(const struct efx_spi_device *spi,
1748 const u8 command, const unsigned int address)
1749 {
1750 return command | (((address >> 8) & spi->munge_address) << 3);
1751 }
1752
1753 /* Wait up to 10 ms for buffered write completion */
1754 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1755 {
1756 struct efx_nic *efx = spi->efx;
1757 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1758 u8 status;
1759 int rc;
1760
1761 for (;;) {
1762 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1763 &status, sizeof(status));
1764 if (rc)
1765 return rc;
1766 if (!(status & SPI_STATUS_NRDY))
1767 return 0;
1768 if (time_after_eq(jiffies, timeout)) {
1769 EFX_ERR(efx, "SPI write timeout on device %d"
1770 " last status=0x%02x\n",
1771 spi->device_id, status);
1772 return -ETIMEDOUT;
1773 }
1774 schedule_timeout_uninterruptible(1);
1775 }
1776 }
1777
1778 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1779 size_t len, size_t *retlen, u8 *buffer)
1780 {
1781 size_t block_len, pos = 0;
1782 unsigned int command;
1783 int rc = 0;
1784
1785 while (pos < len) {
1786 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1787
1788 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1789 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1790 buffer + pos, block_len);
1791 if (rc)
1792 break;
1793 pos += block_len;
1794
1795 /* Avoid locking up the system */
1796 cond_resched();
1797 if (signal_pending(current)) {
1798 rc = -EINTR;
1799 break;
1800 }
1801 }
1802
1803 if (retlen)
1804 *retlen = pos;
1805 return rc;
1806 }
1807
1808 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1809 size_t len, size_t *retlen, const u8 *buffer)
1810 {
1811 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1812 size_t block_len, pos = 0;
1813 unsigned int command;
1814 int rc = 0;
1815
1816 while (pos < len) {
1817 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1818 if (rc)
1819 break;
1820
1821 block_len = min(len - pos,
1822 falcon_spi_write_limit(spi, start + pos));
1823 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1824 rc = falcon_spi_cmd(spi, command, start + pos,
1825 buffer + pos, NULL, block_len);
1826 if (rc)
1827 break;
1828
1829 rc = falcon_spi_wait_write(spi);
1830 if (rc)
1831 break;
1832
1833 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1834 rc = falcon_spi_cmd(spi, command, start + pos,
1835 NULL, verify_buffer, block_len);
1836 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1837 rc = -EIO;
1838 break;
1839 }
1840
1841 pos += block_len;
1842
1843 /* Avoid locking up the system */
1844 cond_resched();
1845 if (signal_pending(current)) {
1846 rc = -EINTR;
1847 break;
1848 }
1849 }
1850
1851 if (retlen)
1852 *retlen = pos;
1853 return rc;
1854 }
1855
1856 /**************************************************************************
1857 *
1858 * MAC wrapper
1859 *
1860 **************************************************************************
1861 */
1862
1863 static int falcon_reset_macs(struct efx_nic *efx)
1864 {
1865 efx_oword_t reg;
1866 int count;
1867
1868 if (falcon_rev(efx) < FALCON_REV_B0) {
1869 /* It's not safe to use GLB_CTL_REG to reset the
1870 * macs, so instead use the internal MAC resets
1871 */
1872 if (!EFX_IS10G(efx)) {
1873 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1);
1874 falcon_write(efx, &reg, GM_CFG1_REG);
1875 udelay(1000);
1876
1877 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0);
1878 falcon_write(efx, &reg, GM_CFG1_REG);
1879 udelay(1000);
1880 return 0;
1881 } else {
1882 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
1883 falcon_write(efx, &reg, XM_GLB_CFG_REG);
1884
1885 for (count = 0; count < 10000; count++) {
1886 falcon_read(efx, &reg, XM_GLB_CFG_REG);
1887 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
1888 return 0;
1889 udelay(10);
1890 }
1891
1892 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1893 return -ETIMEDOUT;
1894 }
1895 }
1896
1897 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1898 * the drain sequence with the statistics fetch */
1899 efx_stats_disable(efx);
1900
1901 falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1902 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);
1903 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1904
1905 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1906 EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1);
1907 EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1);
1908 EFX_SET_OWORD_FIELD(reg, RST_EM, 1);
1909 falcon_write(efx, &reg, GLB_CTL_REG_KER);
1910
1911 count = 0;
1912 while (1) {
1913 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1914 if (!EFX_OWORD_FIELD(reg, RST_XGTX) &&
1915 !EFX_OWORD_FIELD(reg, RST_XGRX) &&
1916 !EFX_OWORD_FIELD(reg, RST_EM)) {
1917 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1918 count);
1919 break;
1920 }
1921 if (count > 20) {
1922 EFX_ERR(efx, "MAC reset failed\n");
1923 break;
1924 }
1925 count++;
1926 udelay(10);
1927 }
1928
1929 efx_stats_enable(efx);
1930
1931 /* If we've reset the EM block and the link is up, then
1932 * we'll have to kick the XAUI link so the PHY can recover */
1933 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1934 falcon_reset_xaui(efx);
1935
1936 return 0;
1937 }
1938
1939 void falcon_drain_tx_fifo(struct efx_nic *efx)
1940 {
1941 efx_oword_t reg;
1942
1943 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1944 (efx->loopback_mode != LOOPBACK_NONE))
1945 return;
1946
1947 falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1948 /* There is no point in draining more than once */
1949 if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0))
1950 return;
1951
1952 falcon_reset_macs(efx);
1953 }
1954
1955 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1956 {
1957 efx_oword_t reg;
1958
1959 if (falcon_rev(efx) < FALCON_REV_B0)
1960 return;
1961
1962 /* Isolate the MAC -> RX */
1963 falcon_read(efx, &reg, RX_CFG_REG_KER);
1964 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0);
1965 falcon_write(efx, &reg, RX_CFG_REG_KER);
1966
1967 if (!efx->link_up)
1968 falcon_drain_tx_fifo(efx);
1969 }
1970
1971 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1972 {
1973 efx_oword_t reg;
1974 int link_speed;
1975 bool tx_fc;
1976
1977 switch (efx->link_speed) {
1978 case 10000: link_speed = 3; break;
1979 case 1000: link_speed = 2; break;
1980 case 100: link_speed = 1; break;
1981 default: link_speed = 0; break;
1982 }
1983 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1984 * as advertised. Disable to ensure packets are not
1985 * indefinitely held and TX queue can be flushed at any point
1986 * while the link is down. */
1987 EFX_POPULATE_OWORD_5(reg,
1988 MAC_XOFF_VAL, 0xffff /* max pause time */,
1989 MAC_BCAD_ACPT, 1,
1990 MAC_UC_PROM, efx->promiscuous,
1991 MAC_LINK_STATUS, 1, /* always set */
1992 MAC_SPEED, link_speed);
1993 /* On B0, MAC backpressure can be disabled and packets get
1994 * discarded. */
1995 if (falcon_rev(efx) >= FALCON_REV_B0) {
1996 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1997 !efx->link_up);
1998 }
1999
2000 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
2001
2002 /* Restore the multicast hash registers. */
2003 falcon_set_multicast_hash(efx);
2004
2005 /* Transmission of pause frames when RX crosses the threshold is
2006 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2007 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2008 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2009 falcon_read(efx, &reg, RX_CFG_REG_KER);
2010 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
2011
2012 /* Unisolate the MAC -> RX */
2013 if (falcon_rev(efx) >= FALCON_REV_B0)
2014 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2015 falcon_write(efx, &reg, RX_CFG_REG_KER);
2016 }
2017
2018 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2019 {
2020 efx_oword_t reg;
2021 u32 *dma_done;
2022 int i;
2023
2024 if (disable_dma_stats)
2025 return 0;
2026
2027 /* Statistics fetch will fail if the MAC is in TX drain */
2028 if (falcon_rev(efx) >= FALCON_REV_B0) {
2029 efx_oword_t temp;
2030 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2031 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2032 return 0;
2033 }
2034
2035 dma_done = (efx->stats_buffer.addr + done_offset);
2036 *dma_done = FALCON_STATS_NOT_DONE;
2037 wmb(); /* ensure done flag is clear */
2038
2039 /* Initiate DMA transfer of stats */
2040 EFX_POPULATE_OWORD_2(reg,
2041 MAC_STAT_DMA_CMD, 1,
2042 MAC_STAT_DMA_ADR,
2043 efx->stats_buffer.dma_addr);
2044 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
2045
2046 /* Wait for transfer to complete */
2047 for (i = 0; i < 400; i++) {
2048 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2049 rmb(); /* Ensure the stats are valid. */
2050 return 0;
2051 }
2052 udelay(10);
2053 }
2054
2055 EFX_ERR(efx, "timed out waiting for statistics\n");
2056 return -ETIMEDOUT;
2057 }
2058
2059 /**************************************************************************
2060 *
2061 * PHY access via GMII
2062 *
2063 **************************************************************************
2064 */
2065
2066 /* Wait for GMII access to complete */
2067 static int falcon_gmii_wait(struct efx_nic *efx)
2068 {
2069 efx_dword_t md_stat;
2070 int count;
2071
2072 /* wait upto 50ms - taken max from datasheet */
2073 for (count = 0; count < 5000; count++) {
2074 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2075 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2076 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2077 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2078 EFX_ERR(efx, "error from GMII access "
2079 EFX_DWORD_FMT"\n",
2080 EFX_DWORD_VAL(md_stat));
2081 return -EIO;
2082 }
2083 return 0;
2084 }
2085 udelay(10);
2086 }
2087 EFX_ERR(efx, "timed out waiting for GMII\n");
2088 return -ETIMEDOUT;
2089 }
2090
2091 /* Write an MDIO register of a PHY connected to Falcon. */
2092 static int falcon_mdio_write(struct net_device *net_dev,
2093 int prtad, int devad, u16 addr, u16 value)
2094 {
2095 struct efx_nic *efx = netdev_priv(net_dev);
2096 efx_oword_t reg;
2097 int rc;
2098
2099 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2100 prtad, devad, addr, value);
2101
2102 spin_lock_bh(&efx->phy_lock);
2103
2104 /* Check MDIO not currently being accessed */
2105 rc = falcon_gmii_wait(efx);
2106 if (rc)
2107 goto out;
2108
2109 /* Write the address/ID register */
2110 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2111 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2112
2113 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2114 falcon_write(efx, &reg, MD_ID_REG_KER);
2115
2116 /* Write data */
2117 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2118 falcon_write(efx, &reg, MD_TXD_REG_KER);
2119
2120 EFX_POPULATE_OWORD_2(reg,
2121 MD_WRC, 1,
2122 MD_GC, 0);
2123 falcon_write(efx, &reg, MD_CS_REG_KER);
2124
2125 /* Wait for data to be written */
2126 rc = falcon_gmii_wait(efx);
2127 if (rc) {
2128 /* Abort the write operation */
2129 EFX_POPULATE_OWORD_2(reg,
2130 MD_WRC, 0,
2131 MD_GC, 1);
2132 falcon_write(efx, &reg, MD_CS_REG_KER);
2133 udelay(10);
2134 }
2135
2136 out:
2137 spin_unlock_bh(&efx->phy_lock);
2138 return rc;
2139 }
2140
2141 /* Read an MDIO register of a PHY connected to Falcon. */
2142 static int falcon_mdio_read(struct net_device *net_dev,
2143 int prtad, int devad, u16 addr)
2144 {
2145 struct efx_nic *efx = netdev_priv(net_dev);
2146 efx_oword_t reg;
2147 int rc;
2148
2149 spin_lock_bh(&efx->phy_lock);
2150
2151 /* Check MDIO not currently being accessed */
2152 rc = falcon_gmii_wait(efx);
2153 if (rc)
2154 goto out;
2155
2156 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2157 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2158
2159 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2160 falcon_write(efx, &reg, MD_ID_REG_KER);
2161
2162 /* Request data to be read */
2163 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2164 falcon_write(efx, &reg, MD_CS_REG_KER);
2165
2166 /* Wait for data to become available */
2167 rc = falcon_gmii_wait(efx);
2168 if (rc == 0) {
2169 falcon_read(efx, &reg, MD_RXD_REG_KER);
2170 rc = EFX_OWORD_FIELD(reg, MD_RXD);
2171 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2172 prtad, devad, addr, rc);
2173 } else {
2174 /* Abort the read operation */
2175 EFX_POPULATE_OWORD_2(reg,
2176 MD_RIC, 0,
2177 MD_GC, 1);
2178 falcon_write(efx, &reg, MD_CS_REG_KER);
2179
2180 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2181 prtad, devad, addr, rc);
2182 }
2183
2184 out:
2185 spin_unlock_bh(&efx->phy_lock);
2186 return rc;
2187 }
2188
2189 static int falcon_probe_phy(struct efx_nic *efx)
2190 {
2191 switch (efx->phy_type) {
2192 case PHY_TYPE_SFX7101:
2193 efx->phy_op = &falcon_sfx7101_phy_ops;
2194 break;
2195 case PHY_TYPE_SFT9001A:
2196 case PHY_TYPE_SFT9001B:
2197 efx->phy_op = &falcon_sft9001_phy_ops;
2198 break;
2199 case PHY_TYPE_QT2022C2:
2200 case PHY_TYPE_QT2025C:
2201 efx->phy_op = &falcon_xfp_phy_ops;
2202 break;
2203 default:
2204 EFX_ERR(efx, "Unknown PHY type %d\n",
2205 efx->phy_type);
2206 return -1;
2207 }
2208
2209 if (efx->phy_op->macs & EFX_XMAC)
2210 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2211 (1 << LOOPBACK_XGXS) |
2212 (1 << LOOPBACK_XAUI));
2213 if (efx->phy_op->macs & EFX_GMAC)
2214 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2215 efx->loopback_modes |= efx->phy_op->loopbacks;
2216
2217 return 0;
2218 }
2219
2220 int falcon_switch_mac(struct efx_nic *efx)
2221 {
2222 struct efx_mac_operations *old_mac_op = efx->mac_op;
2223 efx_oword_t nic_stat;
2224 unsigned strap_val;
2225 int rc = 0;
2226
2227 /* Don't try to fetch MAC stats while we're switching MACs */
2228 efx_stats_disable(efx);
2229
2230 /* Internal loopbacks override the phy speed setting */
2231 if (efx->loopback_mode == LOOPBACK_GMAC) {
2232 efx->link_speed = 1000;
2233 efx->link_fd = true;
2234 } else if (LOOPBACK_INTERNAL(efx)) {
2235 efx->link_speed = 10000;
2236 efx->link_fd = true;
2237 }
2238
2239 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2240 efx->mac_op = (EFX_IS10G(efx) ?
2241 &falcon_xmac_operations : &falcon_gmac_operations);
2242
2243 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2244 * changed, because this function is run post online reset */
2245 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2246 strap_val = EFX_IS10G(efx) ? 5 : 3;
2247 if (falcon_rev(efx) >= FALCON_REV_B0) {
2248 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2249 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2250 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2251 } else {
2252 /* Falcon A1 does not support 1G/10G speed switching
2253 * and must not be used with a PHY that does. */
2254 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2255 }
2256
2257 if (old_mac_op == efx->mac_op)
2258 goto out;
2259
2260 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2261 /* Not all macs support a mac-level link state */
2262 efx->mac_up = true;
2263
2264 rc = falcon_reset_macs(efx);
2265 out:
2266 efx_stats_enable(efx);
2267 return rc;
2268 }
2269
2270 /* This call is responsible for hooking in the MAC and PHY operations */
2271 int falcon_probe_port(struct efx_nic *efx)
2272 {
2273 int rc;
2274
2275 /* Hook in PHY operations table */
2276 rc = falcon_probe_phy(efx);
2277 if (rc)
2278 return rc;
2279
2280 /* Set up MDIO structure for PHY */
2281 efx->mdio.mmds = efx->phy_op->mmds;
2282 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2283 efx->mdio.mdio_read = falcon_mdio_read;
2284 efx->mdio.mdio_write = falcon_mdio_write;
2285
2286 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2287 if (falcon_rev(efx) >= FALCON_REV_B0)
2288 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2289 else
2290 efx->wanted_fc = EFX_FC_RX;
2291
2292 /* Allocate buffer for stats */
2293 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2294 FALCON_MAC_STATS_SIZE);
2295 if (rc)
2296 return rc;
2297 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2298 (u64)efx->stats_buffer.dma_addr,
2299 efx->stats_buffer.addr,
2300 (u64)virt_to_phys(efx->stats_buffer.addr));
2301
2302 return 0;
2303 }
2304
2305 void falcon_remove_port(struct efx_nic *efx)
2306 {
2307 falcon_free_buffer(efx, &efx->stats_buffer);
2308 }
2309
2310 /**************************************************************************
2311 *
2312 * Multicast filtering
2313 *
2314 **************************************************************************
2315 */
2316
2317 void falcon_set_multicast_hash(struct efx_nic *efx)
2318 {
2319 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2320
2321 /* Broadcast packets go through the multicast hash filter.
2322 * ether_crc_le() of the broadcast address is 0xbe2612ff
2323 * so we always add bit 0xff to the mask.
2324 */
2325 set_bit_le(0xff, mc_hash->byte);
2326
2327 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2328 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2329 }
2330
2331
2332 /**************************************************************************
2333 *
2334 * Falcon test code
2335 *
2336 **************************************************************************/
2337
2338 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2339 {
2340 struct falcon_nvconfig *nvconfig;
2341 struct efx_spi_device *spi;
2342 void *region;
2343 int rc, magic_num, struct_ver;
2344 __le16 *word, *limit;
2345 u32 csum;
2346
2347 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2348 if (!spi)
2349 return -EINVAL;
2350
2351 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2352 if (!region)
2353 return -ENOMEM;
2354 nvconfig = region + NVCONFIG_OFFSET;
2355
2356 mutex_lock(&efx->spi_lock);
2357 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2358 mutex_unlock(&efx->spi_lock);
2359 if (rc) {
2360 EFX_ERR(efx, "Failed to read %s\n",
2361 efx->spi_flash ? "flash" : "EEPROM");
2362 rc = -EIO;
2363 goto out;
2364 }
2365
2366 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2367 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2368
2369 rc = -EINVAL;
2370 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2371 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2372 goto out;
2373 }
2374 if (struct_ver < 2) {
2375 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2376 goto out;
2377 } else if (struct_ver < 4) {
2378 word = &nvconfig->board_magic_num;
2379 limit = (__le16 *) (nvconfig + 1);
2380 } else {
2381 word = region;
2382 limit = region + FALCON_NVCONFIG_END;
2383 }
2384 for (csum = 0; word < limit; ++word)
2385 csum += le16_to_cpu(*word);
2386
2387 if (~csum & 0xffff) {
2388 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2389 goto out;
2390 }
2391
2392 rc = 0;
2393 if (nvconfig_out)
2394 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2395
2396 out:
2397 kfree(region);
2398 return rc;
2399 }
2400
2401 /* Registers tested in the falcon register test */
2402 static struct {
2403 unsigned address;
2404 efx_oword_t mask;
2405 } efx_test_registers[] = {
2406 { ADR_REGION_REG_KER,
2407 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2408 { RX_CFG_REG_KER,
2409 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2410 { TX_CFG_REG_KER,
2411 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2412 { TX_CFG2_REG_KER,
2413 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2414 { MAC0_CTRL_REG_KER,
2415 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2416 { SRM_TX_DC_CFG_REG_KER,
2417 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2418 { RX_DC_CFG_REG_KER,
2419 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2420 { RX_DC_PF_WM_REG_KER,
2421 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2422 { DP_CTRL_REG,
2423 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2424 { GM_CFG2_REG,
2425 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2426 { GMF_CFG0_REG,
2427 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2428 { XM_GLB_CFG_REG,
2429 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2430 { XM_TX_CFG_REG,
2431 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2432 { XM_RX_CFG_REG,
2433 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2434 { XM_RX_PARAM_REG,
2435 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2436 { XM_FC_REG,
2437 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2438 { XM_ADR_LO_REG,
2439 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2440 { XX_SD_CTL_REG,
2441 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2442 };
2443
2444 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2445 const efx_oword_t *mask)
2446 {
2447 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2448 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2449 }
2450
2451 int falcon_test_registers(struct efx_nic *efx)
2452 {
2453 unsigned address = 0, i, j;
2454 efx_oword_t mask, imask, original, reg, buf;
2455
2456 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2457 WARN_ON(!LOOPBACK_INTERNAL(efx));
2458
2459 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2460 address = efx_test_registers[i].address;
2461 mask = imask = efx_test_registers[i].mask;
2462 EFX_INVERT_OWORD(imask);
2463
2464 falcon_read(efx, &original, address);
2465
2466 /* bit sweep on and off */
2467 for (j = 0; j < 128; j++) {
2468 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2469 continue;
2470
2471 /* Test this testable bit can be set in isolation */
2472 EFX_AND_OWORD(reg, original, mask);
2473 EFX_SET_OWORD32(reg, j, j, 1);
2474
2475 falcon_write(efx, &reg, address);
2476 falcon_read(efx, &buf, address);
2477
2478 if (efx_masked_compare_oword(&reg, &buf, &mask))
2479 goto fail;
2480
2481 /* Test this testable bit can be cleared in isolation */
2482 EFX_OR_OWORD(reg, original, mask);
2483 EFX_SET_OWORD32(reg, j, j, 0);
2484
2485 falcon_write(efx, &reg, address);
2486 falcon_read(efx, &buf, address);
2487
2488 if (efx_masked_compare_oword(&reg, &buf, &mask))
2489 goto fail;
2490 }
2491
2492 falcon_write(efx, &original, address);
2493 }
2494
2495 return 0;
2496
2497 fail:
2498 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2499 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2500 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2501 return -EIO;
2502 }
2503
2504 /**************************************************************************
2505 *
2506 * Device reset
2507 *
2508 **************************************************************************
2509 */
2510
2511 /* Resets NIC to known state. This routine must be called in process
2512 * context and is allowed to sleep. */
2513 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2514 {
2515 struct falcon_nic_data *nic_data = efx->nic_data;
2516 efx_oword_t glb_ctl_reg_ker;
2517 int rc;
2518
2519 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2520
2521 /* Initiate device reset */
2522 if (method == RESET_TYPE_WORLD) {
2523 rc = pci_save_state(efx->pci_dev);
2524 if (rc) {
2525 EFX_ERR(efx, "failed to backup PCI state of primary "
2526 "function prior to hardware reset\n");
2527 goto fail1;
2528 }
2529 if (FALCON_IS_DUAL_FUNC(efx)) {
2530 rc = pci_save_state(nic_data->pci_dev2);
2531 if (rc) {
2532 EFX_ERR(efx, "failed to backup PCI state of "
2533 "secondary function prior to "
2534 "hardware reset\n");
2535 goto fail2;
2536 }
2537 }
2538
2539 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2540 EXT_PHY_RST_DUR, 0x7,
2541 SWRST, 1);
2542 } else {
2543 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2544 EXCLUDE_FROM_RESET : 0);
2545
2546 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2547 EXT_PHY_RST_CTL, reset_phy,
2548 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2549 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2550 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2551 EE_RST_CTL, EXCLUDE_FROM_RESET,
2552 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2553 SWRST, 1);
2554 }
2555 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2556
2557 EFX_LOG(efx, "waiting for hardware reset\n");
2558 schedule_timeout_uninterruptible(HZ / 20);
2559
2560 /* Restore PCI configuration if needed */
2561 if (method == RESET_TYPE_WORLD) {
2562 if (FALCON_IS_DUAL_FUNC(efx)) {
2563 rc = pci_restore_state(nic_data->pci_dev2);
2564 if (rc) {
2565 EFX_ERR(efx, "failed to restore PCI config for "
2566 "the secondary function\n");
2567 goto fail3;
2568 }
2569 }
2570 rc = pci_restore_state(efx->pci_dev);
2571 if (rc) {
2572 EFX_ERR(efx, "failed to restore PCI config for the "
2573 "primary function\n");
2574 goto fail4;
2575 }
2576 EFX_LOG(efx, "successfully restored PCI config\n");
2577 }
2578
2579 /* Assert that reset complete */
2580 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2581 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2582 rc = -ETIMEDOUT;
2583 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2584 goto fail5;
2585 }
2586 EFX_LOG(efx, "hardware reset complete\n");
2587
2588 return 0;
2589
2590 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2591 fail2:
2592 fail3:
2593 pci_restore_state(efx->pci_dev);
2594 fail1:
2595 fail4:
2596 fail5:
2597 return rc;
2598 }
2599
2600 /* Zeroes out the SRAM contents. This routine must be called in
2601 * process context and is allowed to sleep.
2602 */
2603 static int falcon_reset_sram(struct efx_nic *efx)
2604 {
2605 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2606 int count;
2607
2608 /* Set the SRAM wake/sleep GPIO appropriately. */
2609 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2610 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2611 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2612 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2613
2614 /* Initiate SRAM reset */
2615 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2616 SRAM_OOB_BT_INIT_EN, 1,
2617 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2618 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2619
2620 /* Wait for SRAM reset to complete */
2621 count = 0;
2622 do {
2623 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2624
2625 /* SRAM reset is slow; expect around 16ms */
2626 schedule_timeout_uninterruptible(HZ / 50);
2627
2628 /* Check for reset complete */
2629 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2630 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2631 EFX_LOG(efx, "SRAM reset complete\n");
2632
2633 return 0;
2634 }
2635 } while (++count < 20); /* wait upto 0.4 sec */
2636
2637 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2638 return -ETIMEDOUT;
2639 }
2640
2641 static int falcon_spi_device_init(struct efx_nic *efx,
2642 struct efx_spi_device **spi_device_ret,
2643 unsigned int device_id, u32 device_type)
2644 {
2645 struct efx_spi_device *spi_device;
2646
2647 if (device_type != 0) {
2648 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2649 if (!spi_device)
2650 return -ENOMEM;
2651 spi_device->device_id = device_id;
2652 spi_device->size =
2653 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2654 spi_device->addr_len =
2655 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2656 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2657 spi_device->addr_len == 1);
2658 spi_device->erase_command =
2659 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2660 spi_device->erase_size =
2661 1 << SPI_DEV_TYPE_FIELD(device_type,
2662 SPI_DEV_TYPE_ERASE_SIZE);
2663 spi_device->block_size =
2664 1 << SPI_DEV_TYPE_FIELD(device_type,
2665 SPI_DEV_TYPE_BLOCK_SIZE);
2666
2667 spi_device->efx = efx;
2668 } else {
2669 spi_device = NULL;
2670 }
2671
2672 kfree(*spi_device_ret);
2673 *spi_device_ret = spi_device;
2674 return 0;
2675 }
2676
2677
2678 static void falcon_remove_spi_devices(struct efx_nic *efx)
2679 {
2680 kfree(efx->spi_eeprom);
2681 efx->spi_eeprom = NULL;
2682 kfree(efx->spi_flash);
2683 efx->spi_flash = NULL;
2684 }
2685
2686 /* Extract non-volatile configuration */
2687 static int falcon_probe_nvconfig(struct efx_nic *efx)
2688 {
2689 struct falcon_nvconfig *nvconfig;
2690 int board_rev;
2691 int rc;
2692
2693 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2694 if (!nvconfig)
2695 return -ENOMEM;
2696
2697 rc = falcon_read_nvram(efx, nvconfig);
2698 if (rc == -EINVAL) {
2699 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2700 efx->phy_type = PHY_TYPE_NONE;
2701 efx->mdio.prtad = MDIO_PRTAD_NONE;
2702 board_rev = 0;
2703 rc = 0;
2704 } else if (rc) {
2705 goto fail1;
2706 } else {
2707 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2708 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2709
2710 efx->phy_type = v2->port0_phy_type;
2711 efx->mdio.prtad = v2->port0_phy_addr;
2712 board_rev = le16_to_cpu(v2->board_revision);
2713
2714 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2715 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2716 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2717 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2718 EE_SPI_FLASH,
2719 le32_to_cpu(fl));
2720 if (rc)
2721 goto fail2;
2722 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2723 EE_SPI_EEPROM,
2724 le32_to_cpu(ee));
2725 if (rc)
2726 goto fail2;
2727 }
2728 }
2729
2730 /* Read the MAC addresses */
2731 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2732
2733 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2734
2735 efx_set_board_info(efx, board_rev);
2736
2737 kfree(nvconfig);
2738 return 0;
2739
2740 fail2:
2741 falcon_remove_spi_devices(efx);
2742 fail1:
2743 kfree(nvconfig);
2744 return rc;
2745 }
2746
2747 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2748 * count, port speed). Set workaround and feature flags accordingly.
2749 */
2750 static int falcon_probe_nic_variant(struct efx_nic *efx)
2751 {
2752 efx_oword_t altera_build;
2753 efx_oword_t nic_stat;
2754
2755 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2756 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2757 EFX_ERR(efx, "Falcon FPGA not supported\n");
2758 return -ENODEV;
2759 }
2760
2761 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2762
2763 switch (falcon_rev(efx)) {
2764 case FALCON_REV_A0:
2765 case 0xff:
2766 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2767 return -ENODEV;
2768
2769 case FALCON_REV_A1:
2770 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2771 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2772 return -ENODEV;
2773 }
2774 break;
2775
2776 case FALCON_REV_B0:
2777 break;
2778
2779 default:
2780 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2781 return -ENODEV;
2782 }
2783
2784 /* Initial assumed speed */
2785 efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2786
2787 return 0;
2788 }
2789
2790 /* Probe all SPI devices on the NIC */
2791 static void falcon_probe_spi_devices(struct efx_nic *efx)
2792 {
2793 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2794 int boot_dev;
2795
2796 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2797 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2798 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2799
2800 if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2801 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2802 EE_SPI_FLASH : EE_SPI_EEPROM);
2803 EFX_LOG(efx, "Booted from %s\n",
2804 boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2805 } else {
2806 /* Disable VPD and set clock dividers to safe
2807 * values for initial programming. */
2808 boot_dev = -1;
2809 EFX_LOG(efx, "Booted from internal ASIC settings;"
2810 " setting SPI config\n");
2811 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2812 /* 125 MHz / 7 ~= 20 MHz */
2813 EE_SF_CLOCK_DIV, 7,
2814 /* 125 MHz / 63 ~= 2 MHz */
2815 EE_EE_CLOCK_DIV, 63);
2816 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2817 }
2818
2819 if (boot_dev == EE_SPI_FLASH)
2820 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2821 default_flash_type);
2822 if (boot_dev == EE_SPI_EEPROM)
2823 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2824 large_eeprom_type);
2825 }
2826
2827 int falcon_probe_nic(struct efx_nic *efx)
2828 {
2829 struct falcon_nic_data *nic_data;
2830 int rc;
2831
2832 /* Allocate storage for hardware specific data */
2833 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2834 if (!nic_data)
2835 return -ENOMEM;
2836 efx->nic_data = nic_data;
2837
2838 /* Determine number of ports etc. */
2839 rc = falcon_probe_nic_variant(efx);
2840 if (rc)
2841 goto fail1;
2842
2843 /* Probe secondary function if expected */
2844 if (FALCON_IS_DUAL_FUNC(efx)) {
2845 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2846
2847 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2848 dev))) {
2849 if (dev->bus == efx->pci_dev->bus &&
2850 dev->devfn == efx->pci_dev->devfn + 1) {
2851 nic_data->pci_dev2 = dev;
2852 break;
2853 }
2854 }
2855 if (!nic_data->pci_dev2) {
2856 EFX_ERR(efx, "failed to find secondary function\n");
2857 rc = -ENODEV;
2858 goto fail2;
2859 }
2860 }
2861
2862 /* Now we can reset the NIC */
2863 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2864 if (rc) {
2865 EFX_ERR(efx, "failed to reset NIC\n");
2866 goto fail3;
2867 }
2868
2869 /* Allocate memory for INT_KER */
2870 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2871 if (rc)
2872 goto fail4;
2873 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2874
2875 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2876 (u64)efx->irq_status.dma_addr,
2877 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2878
2879 falcon_probe_spi_devices(efx);
2880
2881 /* Read in the non-volatile configuration */
2882 rc = falcon_probe_nvconfig(efx);
2883 if (rc)
2884 goto fail5;
2885
2886 /* Initialise I2C adapter */
2887 efx->i2c_adap.owner = THIS_MODULE;
2888 nic_data->i2c_data = falcon_i2c_bit_operations;
2889 nic_data->i2c_data.data = efx;
2890 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2891 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2892 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2893 rc = i2c_bit_add_bus(&efx->i2c_adap);
2894 if (rc)
2895 goto fail5;
2896
2897 return 0;
2898
2899 fail5:
2900 falcon_remove_spi_devices(efx);
2901 falcon_free_buffer(efx, &efx->irq_status);
2902 fail4:
2903 fail3:
2904 if (nic_data->pci_dev2) {
2905 pci_dev_put(nic_data->pci_dev2);
2906 nic_data->pci_dev2 = NULL;
2907 }
2908 fail2:
2909 fail1:
2910 kfree(efx->nic_data);
2911 return rc;
2912 }
2913
2914 /* This call performs hardware-specific global initialisation, such as
2915 * defining the descriptor cache sizes and number of RSS channels.
2916 * It does not set up any buffers, descriptor rings or event queues.
2917 */
2918 int falcon_init_nic(struct efx_nic *efx)
2919 {
2920 efx_oword_t temp;
2921 unsigned thresh;
2922 int rc;
2923
2924 /* Use on-chip SRAM */
2925 falcon_read(efx, &temp, NIC_STAT_REG);
2926 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2927 falcon_write(efx, &temp, NIC_STAT_REG);
2928
2929 /* Set the source of the GMAC clock */
2930 if (falcon_rev(efx) == FALCON_REV_B0) {
2931 falcon_read(efx, &temp, GPIO_CTL_REG_KER);
2932 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true);
2933 falcon_write(efx, &temp, GPIO_CTL_REG_KER);
2934 }
2935
2936 /* Set buffer table mode */
2937 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2938 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2939
2940 rc = falcon_reset_sram(efx);
2941 if (rc)
2942 return rc;
2943
2944 /* Set positions of descriptor caches in SRAM. */
2945 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2946 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2947 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2948 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2949
2950 /* Set TX descriptor cache size. */
2951 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2952 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2953 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2954
2955 /* Set RX descriptor cache size. Set low watermark to size-8, as
2956 * this allows most efficient prefetching.
2957 */
2958 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2959 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2960 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2961 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2962 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2963
2964 /* Clear the parity enables on the TX data fifos as
2965 * they produce false parity errors because of timing issues
2966 */
2967 if (EFX_WORKAROUND_5129(efx)) {
2968 falcon_read(efx, &temp, SPARE_REG_KER);
2969 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2970 falcon_write(efx, &temp, SPARE_REG_KER);
2971 }
2972
2973 /* Enable all the genuinely fatal interrupts. (They are still
2974 * masked by the overall interrupt mask, controlled by
2975 * falcon_interrupts()).
2976 *
2977 * Note: All other fatal interrupts are enabled
2978 */
2979 EFX_POPULATE_OWORD_3(temp,
2980 ILL_ADR_INT_KER_EN, 1,
2981 RBUF_OWN_INT_KER_EN, 1,
2982 TBUF_OWN_INT_KER_EN, 1);
2983 EFX_INVERT_OWORD(temp);
2984 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2985
2986 if (EFX_WORKAROUND_7244(efx)) {
2987 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2988 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2989 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2990 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2991 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2992 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2993 }
2994
2995 falcon_setup_rss_indir_table(efx);
2996
2997 /* Setup RX. Wait for descriptor is broken and must
2998 * be disabled. RXDP recovery shouldn't be needed, but is.
2999 */
3000 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
3001 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
3002 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
3003 if (EFX_WORKAROUND_5583(efx))
3004 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
3005 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
3006
3007 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3008 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3009 */
3010 falcon_read(efx, &temp, TX_CFG2_REG_KER);
3011 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3012 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3013 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3014 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3015 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3016 /* Enable SW_EV to inherit in char driver - assume harmless here */
3017 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3018 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3019 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3020 /* Squash TX of packets of 16 bytes or less */
3021 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3022 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3023 falcon_write(efx, &temp, TX_CFG2_REG_KER);
3024
3025 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3026 * descriptors (which is bad).
3027 */
3028 falcon_read(efx, &temp, TX_CFG_REG_KER);
3029 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
3030 falcon_write(efx, &temp, TX_CFG_REG_KER);
3031
3032 /* RX config */
3033 falcon_read(efx, &temp, RX_CFG_REG_KER);
3034 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
3035 if (EFX_WORKAROUND_7575(efx))
3036 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
3037 (3 * 4096) / 32);
3038 if (falcon_rev(efx) >= FALCON_REV_B0)
3039 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
3040
3041 /* RX FIFO flow control thresholds */
3042 thresh = ((rx_xon_thresh_bytes >= 0) ?
3043 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
3044 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
3045 thresh = ((rx_xoff_thresh_bytes >= 0) ?
3046 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
3047 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
3048 /* RX control FIFO thresholds [32 entries] */
3049 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3050 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3051 falcon_write(efx, &temp, RX_CFG_REG_KER);
3052
3053 /* Set destination of both TX and RX Flush events */
3054 if (falcon_rev(efx) >= FALCON_REV_B0) {
3055 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3056 falcon_write(efx, &temp, DP_CTRL_REG);
3057 }
3058
3059 return 0;
3060 }
3061
3062 void falcon_remove_nic(struct efx_nic *efx)
3063 {
3064 struct falcon_nic_data *nic_data = efx->nic_data;
3065 int rc;
3066
3067 /* Remove I2C adapter and clear it in preparation for a retry */
3068 rc = i2c_del_adapter(&efx->i2c_adap);
3069 BUG_ON(rc);
3070 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3071
3072 falcon_remove_spi_devices(efx);
3073 falcon_free_buffer(efx, &efx->irq_status);
3074
3075 falcon_reset_hw(efx, RESET_TYPE_ALL);
3076
3077 /* Release the second function after the reset */
3078 if (nic_data->pci_dev2) {
3079 pci_dev_put(nic_data->pci_dev2);
3080 nic_data->pci_dev2 = NULL;
3081 }
3082
3083 /* Tear down the private nic state */
3084 kfree(efx->nic_data);
3085 efx->nic_data = NULL;
3086 }
3087
3088 void falcon_update_nic_stats(struct efx_nic *efx)
3089 {
3090 efx_oword_t cnt;
3091
3092 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3093 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3094 }
3095
3096 /**************************************************************************
3097 *
3098 * Revision-dependent attributes used by efx.c
3099 *
3100 **************************************************************************
3101 */
3102
3103 struct efx_nic_type falcon_a_nic_type = {
3104 .mem_bar = 2,
3105 .mem_map_size = 0x20000,
3106 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3107 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3108 .buf_tbl_base = BUF_TBL_KER_A1,
3109 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3110 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3111 .txd_ring_mask = FALCON_TXD_RING_MASK,
3112 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3113 .evq_size = FALCON_EVQ_SIZE,
3114 .max_dma_mask = FALCON_DMA_MASK,
3115 .tx_dma_mask = FALCON_TX_DMA_MASK,
3116 .bug5391_mask = 0xf,
3117 .rx_xoff_thresh = 2048,
3118 .rx_xon_thresh = 512,
3119 .rx_buffer_padding = 0x24,
3120 .max_interrupt_mode = EFX_INT_MODE_MSI,
3121 .phys_addr_channels = 4,
3122 };
3123
3124 struct efx_nic_type falcon_b_nic_type = {
3125 .mem_bar = 2,
3126 /* Map everything up to and including the RSS indirection
3127 * table. Don't map MSI-X table, MSI-X PBA since Linux
3128 * requires that they not be mapped. */
3129 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3130 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3131 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3132 .buf_tbl_base = BUF_TBL_KER_B0,
3133 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3134 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3135 .txd_ring_mask = FALCON_TXD_RING_MASK,
3136 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3137 .evq_size = FALCON_EVQ_SIZE,
3138 .max_dma_mask = FALCON_DMA_MASK,
3139 .tx_dma_mask = FALCON_TX_DMA_MASK,
3140 .bug5391_mask = 0,
3141 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3142 .rx_xon_thresh = 27648, /* ~3*max MTU */
3143 .rx_buffer_padding = 0,
3144 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3145 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3146 * interrupt handler only supports 32
3147 * channels */
3148 };
3149
Verdex Pro support