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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / wan / pc300_drv.c
blob79dabc557bd395b58fdf137efe7a79d65b2df956
1 #define USE_PCI_CLOCK
2 static char rcsid[] =
3 "Revision: 3.4.5 Date: 2002/03/07 ";
4
5 /*
6 * pc300.c Cyclades-PC300(tm) Driver.
7 *
8 * Author: Ivan Passos <ivan@cyclades.com>
9 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
10 *
11 * Copyright: (c) 1999-2003 Cyclades Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Using tabstop = 4.
19 *
20 * $Log: pc300_drv.c,v $
21 * Revision 3.23 2002/03/20 13:58:40 henrique
22 * Fixed ortographic mistakes
23 *
24 * Revision 3.22 2002/03/13 16:56:56 henrique
25 * Take out the debug messages
26 *
27 * Revision 3.21 2002/03/07 14:17:09 henrique
28 * License data fixed
29 *
30 * Revision 3.20 2002/01/17 17:58:52 ivan
31 * Support for PC300-TE/M (PMC).
32 *
33 * Revision 3.19 2002/01/03 17:08:47 daniela
34 * Enables DMA reception when the SCA-II disables it improperly.
35 *
36 * Revision 3.18 2001/12/03 18:47:50 daniela
37 * Esthetic changes.
38 *
39 * Revision 3.17 2001/10/19 16:50:13 henrique
40 * Patch to kernel 2.4.12 and new generic hdlc.
41 *
42 * Revision 3.16 2001/10/16 15:12:31 regina
43 * clear statistics
44 *
45 * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46 * More DMA fixes for noisy lines.
47 * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48 * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49 * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50 * Fixed BOF interrupt treatment. Created dma_start routine.
51 * Changed min and max to cpc_min and cpc_max.
52 *
53 * Revision 3.10 2001/08/06 12:01:51 regina
54 * Fixed problem in DSR_DE bit.
55 *
56 * Revision 3.9 2001/07/18 19:27:26 daniela
57 * Added some history comments.
58 *
59 * Revision 3.8 2001/07/12 13:11:19 regina
60 * bug fix - DCD-OFF in pc300 tty driver
61 *
62 * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63 * Removing kernel 2.4.3 and previous support.
64 * DMA transmission bug fix.
65 * MTU check in cpc_net_rx fixed.
66 * Boot messages reviewed.
67 * New configuration parameters (line code, CRC calculation and clock).
68 *
69 * Revision 3.2 2001/06/22 13:13:02 regina
70 * MLPPP implementation. Changed the header of message trace to include
71 * the device name. New format : "hdlcX[R/T]: ".
72 * Default configuration changed.
73 *
74 * Revision 3.1 2001/06/15 regina
75 * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76 * upping major version number
77 *
78 * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79 * PC300 initial CVS version (3.4.0-pre1)
80 *
81 * Revision 3.0.1.2 2001/06/08 daniela
82 * Did some changes in the DMA programming implementation to avoid the
83 * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84 *
85 * Revision 3.0.1.1 2001/05/02 daniela
86 * Added kernel 2.4.3 support.
87 *
88 * Revision 3.0.1.0 2001/03/13 daniela, henrique
89 * Added Frame Relay Support.
90 * Driver now uses HDLC generic driver to provide protocol support.
91 *
92 * Revision 3.0.0.8 2001/03/02 daniela
93 * Fixed ram size detection.
94 * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95 *
96 * Revision 3.0.0.7 2001/02/23 daniela
97 * netif_stop_queue called before the SCA-II transmition commands in
98 * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99 * transmition interrupts.
100 * Fixed falc_check_status for Unframed E1.
101 *
102 * Revision 3.0.0.6 2000/12/13 daniela
103 * Implemented pc300util support: trace, statistics, status and loopback
104 * tests for the PC300 TE boards.
105 *
106 * Revision 3.0.0.5 2000/12/12 ivan
107 * Added support for Unframed E1.
108 * Implemented monitor mode.
109 * Fixed DCD sensitivity on the second channel.
110 * Driver now complies with new PCI kernel architecture.
111 *
112 * Revision 3.0.0.4 2000/09/28 ivan
113 * Implemented DCD sensitivity.
114 * Moved hardware-specific open to the end of cpc_open, to avoid race
115 * conditions with early reception interrupts.
116 * Included code for [request|release]_mem_region().
117 * Changed location of pc300.h .
118 * Minor code revision (contrib. of Jeff Garzik).
119 *
120 * Revision 3.0.0.3 2000/07/03 ivan
121 * Previous bugfix for the framing errors with external clock made X21
122 * boards stop working. This version fixes it.
123 *
124 * Revision 3.0.0.2 2000/06/23 ivan
125 * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126 * handling when Tx timeouts occur.
127 * Revisited Rx statistics.
128 * Fixed a bug in the SCA-II programming that would cause framing errors
129 * when external clock was configured.
130 *
131 * Revision 3.0.0.1 2000/05/26 ivan
132 * Added logic in the SCA interrupt handler so that no board can monopolize
133 * the driver.
134 * Request PLX I/O region, although driver doesn't use it, to avoid
135 * problems with other drivers accessing it.
136 *
137 * Revision 3.0.0.0 2000/05/15 ivan
138 * Did some changes in the DMA programming implementation to avoid the
139 * occurrence of a SCA-II bug in the second channel.
140 * Implemented workaround for PLX9050 bug that would cause a system lockup
141 * in certain systems, depending on the MMIO addresses allocated to the
142 * board.
143 * Fixed the FALC chip programming to avoid synchronization problems in the
144 * second channel (TE only).
145 * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146 * cpc_queue_xmit().
147 * Changed the built-in driver implementation so that the driver can use the
148 * general 'hdlcN' naming convention instead of proprietary device names.
149 * Driver load messages are now device-centric, instead of board-centric.
150 * Dynamic allocation of net_device structures.
151 * Code is now compliant with the new module interface (module_[init|exit]).
152 * Make use of the PCI helper functions to access PCI resources.
153 *
154 * Revision 2.0.0.0 2000/04/15 ivan
155 * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156 *
157 * Revision 1.1.0.0 2000/02/28 ivan
158 * Major changes in the driver architecture.
159 * Softnet compliancy implemented.
160 * Driver now reports physical instead of virtual memory addresses.
161 * Added cpc_change_mtu function.
162 *
163 * Revision 1.0.0.0 1999/12/16 ivan
164 * First official release.
165 * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166 * Support for monolythic installation (i.e., drv built into the kernel).
167 * X.25 additional checking when lapb_[dis]connect_request returns an error.
168 * SCA programming now covers X.21 as well.
169 *
170 * Revision 0.3.1.0 1999/11/18 ivan
171 * Made X.25 support configuration-dependent (as it depends on external
172 * modules to work).
173 * Changed X.25-specific function names to comply with adopted convention.
174 * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175 * Fixed bug in ch_config that would disable interrupts on a previously
176 * enabled channel if the other channel on the same board was enabled later.
177 *
178 * Revision 0.3.0.0 1999/11/16 daniela
179 * X.25 support.
180 *
181 * Revision 0.2.3.0 1999/11/15 ivan
182 * Function cpc_ch_status now provides more detailed information.
183 * Added support for X.21 clock configuration.
184 * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185 * Now using PCI clock instead of internal oscillator clock for the SCA.
186 *
187 * Revision 0.2.2.0 1999/11/10 ivan
188 * Changed the *_dma_buf_check functions so that they would print only
189 * the useful info instead of the whole buffer descriptor bank.
190 * Fixed bug in cpc_queue_xmit that would eventually crash the system
191 * in case of a packet drop.
192 * Implemented TX underrun handling.
193 * Improved SCA fine tuning to boost up its performance.
194 *
195 * Revision 0.2.1.0 1999/11/03 ivan
196 * Added functions *dma_buf_pt_init to allow independent initialization
197 * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198 * Kernel buffer release and tbusy clearing is now done in the interrupt
199 * handler.
200 * Fixed bug in cpc_open that would cause an interface reopen to fail.
201 * Added a protocol-specific code section in cpc_net_rx.
202 * Removed printk level defs (they might be added back after the beta phase).
203 *
204 * Revision 0.2.0.0 1999/10/28 ivan
205 * Revisited the code so that new protocols can be easily added / supported.
206 *
207 * Revision 0.1.0.1 1999/10/20 ivan
208 * Mostly "esthetic" changes.
209 *
210 * Revision 0.1.0.0 1999/10/11 ivan
211 * Initial version.
212 *
213 */
214
215 #include <linux/module.h>
216 #include <linux/kernel.h>
217 #include <linux/mm.h>
218 #include <linux/ioport.h>
219 #include <linux/pci.h>
220 #include <linux/errno.h>
221 #include <linux/string.h>
222 #include <linux/init.h>
223 #include <linux/delay.h>
224 #include <linux/net.h>
225 #include <linux/skbuff.h>
226 #include <linux/if_arp.h>
227 #include <linux/netdevice.h>
228 #include <linux/etherdevice.h>
229 #include <linux/spinlock.h>
230 #include <linux/if.h>
231 #include <net/arp.h>
232
233 #include <asm/io.h>
234 #include <asm/uaccess.h>
235
236 #include "pc300.h"
237
238 #define CPC_LOCK(card,flags) \
239 do { \
240 spin_lock_irqsave(&card->card_lock, flags); \
241 } while (0)
242
243 #define CPC_UNLOCK(card,flags) \
244 do { \
245 spin_unlock_irqrestore(&card->card_lock, flags); \
246 } while (0)
247
248 #undef PC300_DEBUG_PCI
249 #undef PC300_DEBUG_INTR
250 #undef PC300_DEBUG_TX
251 #undef PC300_DEBUG_RX
252 #undef PC300_DEBUG_OTHER
253
254 static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
255 /* PC300/RSV or PC300/X21, 2 chan */
256 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
257 /* PC300/RSV or PC300/X21, 1 chan */
258 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
259 /* PC300/TE, 2 chan */
260 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
261 /* PC300/TE, 1 chan */
262 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
263 /* PC300/TE-M, 2 chan */
264 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
265 /* PC300/TE-M, 1 chan */
266 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
267 /* End of table */
268 {0,},
269 };
270 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
271
272 #ifndef cpc_min
273 #define cpc_min(a,b) (((a)<(b))?(a):(b))
274 #endif
275 #ifndef cpc_max
276 #define cpc_max(a,b) (((a)>(b))?(a):(b))
277 #endif
278
279 /* prototypes */
280 static void tx_dma_buf_pt_init(pc300_t *, int);
281 static void tx_dma_buf_init(pc300_t *, int);
282 static void rx_dma_buf_pt_init(pc300_t *, int);
283 static void rx_dma_buf_init(pc300_t *, int);
284 static void tx_dma_buf_check(pc300_t *, int);
285 static void rx_dma_buf_check(pc300_t *, int);
286 static irqreturn_t cpc_intr(int, void *);
287 static int clock_rate_calc(u32, u32, int *);
288 static u32 detect_ram(pc300_t *);
289 static void plx_init(pc300_t *);
290 static void cpc_trace(struct net_device *, struct sk_buff *, char);
291 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
292 static int cpc_close(struct net_device *dev);
293
294 #ifdef CONFIG_PC300_MLPPP
295 void cpc_tty_init(pc300dev_t * dev);
296 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
297 void cpc_tty_receive(pc300dev_t * pc300dev);
298 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
299 void cpc_tty_reset_var(void);
300 #endif
301
302 /************************/
303 /*** DMA Routines ***/
304 /************************/
305 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
306 {
307 int i;
308 int ch_factor = ch * N_DMA_TX_BUF;
309 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
310 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
311
312 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
313 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
314 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
315 cpc_writel(&ptdescr->ptbuf,
316 (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
317 }
318 }
319
320 static void tx_dma_buf_init(pc300_t * card, int ch)
321 {
322 int i;
323 int ch_factor = ch * N_DMA_TX_BUF;
324 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
325 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
326
327 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
328 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
329 cpc_writew(&ptdescr->len, 0);
330 cpc_writeb(&ptdescr->status, DST_OSB);
331 }
332 tx_dma_buf_pt_init(card, ch);
333 }
334
335 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
336 {
337 int i;
338 int ch_factor = ch * N_DMA_RX_BUF;
339 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
340 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
341
342 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
343 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
344 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
345 cpc_writel(&ptdescr->ptbuf,
346 (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
347 }
348 }
349
350 static void rx_dma_buf_init(pc300_t * card, int ch)
351 {
352 int i;
353 int ch_factor = ch * N_DMA_RX_BUF;
354 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
355 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
356
357 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
358 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
359 cpc_writew(&ptdescr->len, 0);
360 cpc_writeb(&ptdescr->status, 0);
361 }
362 rx_dma_buf_pt_init(card, ch);
363 }
364
365 static void tx_dma_buf_check(pc300_t * card, int ch)
366 {
367 volatile pcsca_bd_t __iomem *ptdescr;
368 int i;
369 u16 first_bd = card->chan[ch].tx_first_bd;
370 u16 next_bd = card->chan[ch].tx_next_bd;
371
372 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
373 first_bd, TX_BD_ADDR(ch, first_bd),
374 next_bd, TX_BD_ADDR(ch, next_bd));
375 for (i = first_bd,
376 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
377 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
378 i = (i + 1) & (N_DMA_TX_BUF - 1),
379 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
380 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
381 ch, i, cpc_readl(&ptdescr->next),
382 cpc_readl(&ptdescr->ptbuf),
383 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
384 }
385 printk("\n");
386 }
387
388 #ifdef PC300_DEBUG_OTHER
389 /* Show all TX buffer descriptors */
390 static void tx1_dma_buf_check(pc300_t * card, int ch)
391 {
392 volatile pcsca_bd_t __iomem *ptdescr;
393 int i;
394 u16 first_bd = card->chan[ch].tx_first_bd;
395 u16 next_bd = card->chan[ch].tx_next_bd;
396 u32 scabase = card->hw.scabase;
397
398 printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
399 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
400 first_bd, TX_BD_ADDR(ch, first_bd),
401 next_bd, TX_BD_ADDR(ch, next_bd));
402 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
403 cpc_readl(scabase + DTX_REG(CDAL, ch)),
404 cpc_readl(scabase + DTX_REG(EDAL, ch)));
405 for (i = 0; i < N_DMA_TX_BUF; i++) {
406 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
407 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
408 ch, i, cpc_readl(&ptdescr->next),
409 cpc_readl(&ptdescr->ptbuf),
410 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
411 }
412 printk("\n");
413 }
414 #endif
415
416 static void rx_dma_buf_check(pc300_t * card, int ch)
417 {
418 volatile pcsca_bd_t __iomem *ptdescr;
419 int i;
420 u16 first_bd = card->chan[ch].rx_first_bd;
421 u16 last_bd = card->chan[ch].rx_last_bd;
422 int ch_factor;
423
424 ch_factor = ch * N_DMA_RX_BUF;
425 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
426 for (i = 0, ptdescr = (card->hw.rambase +
427 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
428 i < N_DMA_RX_BUF; i++, ptdescr++) {
429 if (cpc_readb(&ptdescr->status) & DST_OSB)
430 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
431 ch, i, cpc_readl(&ptdescr->next),
432 cpc_readl(&ptdescr->ptbuf),
433 cpc_readb(&ptdescr->status),
434 cpc_readw(&ptdescr->len));
435 }
436 printk("\n");
437 }
438
439 static int dma_get_rx_frame_size(pc300_t * card, int ch)
440 {
441 volatile pcsca_bd_t __iomem *ptdescr;
442 u16 first_bd = card->chan[ch].rx_first_bd;
443 int rcvd = 0;
444 volatile u8 status;
445
446 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
447 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
448 rcvd += cpc_readw(&ptdescr->len);
449 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
450 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
451 /* Return the size of a good frame or incomplete bad frame
452 * (dma_buf_read will clean the buffer descriptors in this case). */
453 return (rcvd);
454 }
455 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
456 }
457 return (-1);
458 }
459
460 /*
461 * dma_buf_write: writes a frame to the Tx DMA buffers
462 * NOTE: this function writes one frame at a time.
463 */
464 static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
465 {
466 int i, nchar;
467 volatile pcsca_bd_t __iomem *ptdescr;
468 int tosend = len;
469 u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
470
471 if (nbuf >= card->chan[ch].nfree_tx_bd) {
472 return -ENOMEM;
473 }
474
475 for (i = 0; i < nbuf; i++) {
476 ptdescr = (card->hw.rambase +
477 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
478 nchar = cpc_min(BD_DEF_LEN, tosend);
479 if (cpc_readb(&ptdescr->status) & DST_OSB) {
480 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
481 &ptdata[len - tosend], nchar);
482 cpc_writew(&ptdescr->len, nchar);
483 card->chan[ch].nfree_tx_bd--;
484 if ((i + 1) == nbuf) {
485 /* This must be the last BD to be used */
486 cpc_writeb(&ptdescr->status, DST_EOM);
487 } else {
488 cpc_writeb(&ptdescr->status, 0);
489 }
490 } else {
491 return -ENOMEM;
492 }
493 tosend -= nchar;
494 card->chan[ch].tx_next_bd =
495 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
496 }
497 /* If it gets to here, it means we have sent the whole frame */
498 return 0;
499 }
500
501 /*
502 * dma_buf_read: reads a frame from the Rx DMA buffers
503 * NOTE: this function reads one frame at a time.
504 */
505 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
506 {
507 int nchar;
508 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
509 volatile pcsca_bd_t __iomem *ptdescr;
510 int rcvd = 0;
511 volatile u8 status;
512
513 ptdescr = (card->hw.rambase +
514 RX_BD_ADDR(ch, chan->rx_first_bd));
515 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
516 nchar = cpc_readw(&ptdescr->len);
517 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
518 || (nchar > BD_DEF_LEN)) {
519
520 if (nchar > BD_DEF_LEN)
521 status |= DST_RBIT;
522 rcvd = -status;
523 /* Discard remaining descriptors used by the bad frame */
524 while (chan->rx_first_bd != chan->rx_last_bd) {
525 cpc_writeb(&ptdescr->status, 0);
526 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
527 if (status & DST_EOM)
528 break;
529 ptdescr = (card->hw.rambase +
530 cpc_readl(&ptdescr->next));
531 status = cpc_readb(&ptdescr->status);
532 }
533 break;
534 }
535 if (nchar != 0) {
536 if (skb) {
537 memcpy_fromio(skb_put(skb, nchar),
538 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
539 }
540 rcvd += nchar;
541 }
542 cpc_writeb(&ptdescr->status, 0);
543 cpc_writeb(&ptdescr->len, 0);
544 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
545
546 if (status & DST_EOM)
547 break;
548
549 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
550 }
551
552 if (rcvd != 0) {
553 /* Update pointer */
554 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
555 /* Update EDA */
556 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
557 RX_BD_ADDR(ch, chan->rx_last_bd));
558 }
559 return (rcvd);
560 }
561
562 static void tx_dma_stop(pc300_t * card, int ch)
563 {
564 void __iomem *scabase = card->hw.scabase;
565 u8 drr_ena_bit = 1 << (5 + 2 * ch);
566 u8 drr_rst_bit = 1 << (1 + 2 * ch);
567
568 /* Disable DMA */
569 cpc_writeb(scabase + DRR, drr_ena_bit);
570 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
571 }
572
573 static void rx_dma_stop(pc300_t * card, int ch)
574 {
575 void __iomem *scabase = card->hw.scabase;
576 u8 drr_ena_bit = 1 << (4 + 2 * ch);
577 u8 drr_rst_bit = 1 << (2 * ch);
578
579 /* Disable DMA */
580 cpc_writeb(scabase + DRR, drr_ena_bit);
581 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
582 }
583
584 static void rx_dma_start(pc300_t * card, int ch)
585 {
586 void __iomem *scabase = card->hw.scabase;
587 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
588
589 /* Start DMA */
590 cpc_writel(scabase + DRX_REG(CDAL, ch),
591 RX_BD_ADDR(ch, chan->rx_first_bd));
592 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
593 RX_BD_ADDR(ch, chan->rx_first_bd)) {
594 cpc_writel(scabase + DRX_REG(CDAL, ch),
595 RX_BD_ADDR(ch, chan->rx_first_bd));
596 }
597 cpc_writel(scabase + DRX_REG(EDAL, ch),
598 RX_BD_ADDR(ch, chan->rx_last_bd));
599 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
600 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
601 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
602 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
603 }
604 }
605
606 /*************************/
607 /*** FALC Routines ***/
608 /*************************/
609 static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
610 {
611 void __iomem *falcbase = card->hw.falcbase;
612 unsigned long i = 0;
613
614 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
615 if (i++ >= PC300_FALC_MAXLOOP) {
616 printk("%s: FALC command locked(cmd=0x%x).\n",
617 card->chan[ch].d.name, cmd);
618 break;
619 }
620 }
621 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
622 }
623
624 static void falc_intr_enable(pc300_t * card, int ch)
625 {
626 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
627 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
628 falc_t *pfalc = (falc_t *) & chan->falc;
629 void __iomem *falcbase = card->hw.falcbase;
630
631 /* Interrupt pins are open-drain */
632 cpc_writeb(falcbase + F_REG(IPC, ch),
633 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
634 /* Conters updated each second */
635 cpc_writeb(falcbase + F_REG(FMR1, ch),
636 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
637 /* Enable SEC and ES interrupts */
638 cpc_writeb(falcbase + F_REG(IMR3, ch),
639 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
640 if (conf->fr_mode == PC300_FR_UNFRAMED) {
641 cpc_writeb(falcbase + F_REG(IMR4, ch),
642 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
643 } else {
644 cpc_writeb(falcbase + F_REG(IMR4, ch),
645 cpc_readb(falcbase + F_REG(IMR4, ch)) &
646 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
647 }
648 if (conf->media == IF_IFACE_T1) {
649 cpc_writeb(falcbase + F_REG(IMR3, ch),
650 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
651 } else {
652 cpc_writeb(falcbase + F_REG(IPC, ch),
653 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
654 if (conf->fr_mode == PC300_FR_UNFRAMED) {
655 cpc_writeb(falcbase + F_REG(IMR2, ch),
656 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
657 } else {
658 cpc_writeb(falcbase + F_REG(IMR2, ch),
659 cpc_readb(falcbase + F_REG(IMR2, ch)) &
660 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
661 if (pfalc->multiframe_mode) {
662 cpc_writeb(falcbase + F_REG(IMR2, ch),
663 cpc_readb(falcbase + F_REG(IMR2, ch)) &
664 ~(IMR2_T400MS | IMR2_MFAR));
665 } else {
666 cpc_writeb(falcbase + F_REG(IMR2, ch),
667 cpc_readb(falcbase + F_REG(IMR2, ch)) |
668 IMR2_T400MS | IMR2_MFAR);
669 }
670 }
671 }
672 }
673
674 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
675 {
676 void __iomem *falcbase = card->hw.falcbase;
677 u8 tshf = card->chan[ch].falc.offset;
678
679 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
680 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
681 ~(0x80 >> ((timeslot - tshf) & 0x07)));
682 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
683 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
684 (0x80 >> (timeslot & 0x07)));
685 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
686 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
687 (0x80 >> (timeslot & 0x07)));
688 }
689
690 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
691 {
692 void __iomem *falcbase = card->hw.falcbase;
693 u8 tshf = card->chan[ch].falc.offset;
694
695 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
696 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
697 (0x80 >> ((timeslot - tshf) & 0x07)));
698 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
699 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
700 ~(0x80 >> (timeslot & 0x07)));
701 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
702 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
703 ~(0x80 >> (timeslot & 0x07)));
704 }
705
706 static void falc_close_all_timeslots(pc300_t * card, int ch)
707 {
708 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
709 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
710 void __iomem *falcbase = card->hw.falcbase;
711
712 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
713 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
714 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
715 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
716 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
717 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
718 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
719 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
720 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
721 if (conf->media == IF_IFACE_E1) {
722 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
723 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
724 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
725 }
726 }
727
728 static void falc_open_all_timeslots(pc300_t * card, int ch)
729 {
730 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
731 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
732 void __iomem *falcbase = card->hw.falcbase;
733
734 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
735 if (conf->fr_mode == PC300_FR_UNFRAMED) {
736 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
737 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
738 } else {
739 /* Timeslot 0 is never enabled */
740 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
741 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
742 }
743 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
744 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
745 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
746 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
747 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
748 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
749 if (conf->media == IF_IFACE_E1) {
750 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
751 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
752 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
753 } else {
754 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
755 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
756 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
757 }
758 }
759
760 static void falc_init_timeslot(pc300_t * card, int ch)
761 {
762 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
763 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
764 falc_t *pfalc = (falc_t *) & chan->falc;
765 int tslot;
766
767 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
768 if (conf->tslot_bitmap & (1 << tslot)) {
769 // Channel enabled
770 falc_open_timeslot(card, ch, tslot + 1);
771 } else {
772 // Channel disabled
773 falc_close_timeslot(card, ch, tslot + 1);
774 }
775 }
776 }
777
778 static void falc_enable_comm(pc300_t * card, int ch)
779 {
780 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
781 falc_t *pfalc = (falc_t *) & chan->falc;
782
783 if (pfalc->full_bandwidth) {
784 falc_open_all_timeslots(card, ch);
785 } else {
786 falc_init_timeslot(card, ch);
787 }
788 // CTS/DCD ON
789 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
790 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
791 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
792 }
793
794 static void falc_disable_comm(pc300_t * card, int ch)
795 {
796 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
797 falc_t *pfalc = (falc_t *) & chan->falc;
798
799 if (pfalc->loop_active != 2) {
800 falc_close_all_timeslots(card, ch);
801 }
802 // CTS/DCD OFF
803 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
804 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
805 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
806 }
807
808 static void falc_init_t1(pc300_t * card, int ch)
809 {
810 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
811 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
812 falc_t *pfalc = (falc_t *) & chan->falc;
813 void __iomem *falcbase = card->hw.falcbase;
814 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
815
816 /* Switch to T1 mode (PCM 24) */
817 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
818
819 /* Wait 20 us for setup */
820 udelay(20);
821
822 /* Transmit Buffer Size (1 frame) */
823 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
824
825 /* Clock mode */
826 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
827 cpc_writeb(falcbase + F_REG(LIM0, ch),
828 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
829 } else { /* Slave mode */
830 cpc_writeb(falcbase + F_REG(LIM0, ch),
831 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
832 cpc_writeb(falcbase + F_REG(LOOP, ch),
833 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
834 }
835
836 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
837 cpc_writeb(falcbase + F_REG(FMR0, ch),
838 cpc_readb(falcbase + F_REG(FMR0, ch)) &
839 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
840
841 switch (conf->lcode) {
842 case PC300_LC_AMI:
843 cpc_writeb(falcbase + F_REG(FMR0, ch),
844 cpc_readb(falcbase + F_REG(FMR0, ch)) |
845 FMR0_XC1 | FMR0_RC1);
846 /* Clear Channel register to ON for all channels */
847 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
848 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
849 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
850 break;
851
852 case PC300_LC_B8ZS:
853 cpc_writeb(falcbase + F_REG(FMR0, ch),
854 cpc_readb(falcbase + F_REG(FMR0, ch)) |
855 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
856 break;
857
858 case PC300_LC_NRZ:
859 cpc_writeb(falcbase + F_REG(FMR0, ch),
860 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
861 break;
862 }
863
864 cpc_writeb(falcbase + F_REG(LIM0, ch),
865 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
866 cpc_writeb(falcbase + F_REG(LIM0, ch),
867 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
868 /* Set interface mode to 2 MBPS */
869 cpc_writeb(falcbase + F_REG(FMR1, ch),
870 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
871
872 switch (conf->fr_mode) {
873 case PC300_FR_ESF:
874 pfalc->multiframe_mode = 0;
875 cpc_writeb(falcbase + F_REG(FMR4, ch),
876 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
877 cpc_writeb(falcbase + F_REG(FMR1, ch),
878 cpc_readb(falcbase + F_REG(FMR1, ch)) |
879 FMR1_CRC | FMR1_EDL);
880 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
881 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
882 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
883 cpc_writeb(falcbase + F_REG(FMR0, ch),
884 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
885 cpc_writeb(falcbase + F_REG(FMR2, ch),
886 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
887 break;
888
889 case PC300_FR_D4:
890 pfalc->multiframe_mode = 1;
891 cpc_writeb(falcbase + F_REG(FMR4, ch),
892 cpc_readb(falcbase + F_REG(FMR4, ch)) &
893 ~(FMR4_FM1 | FMR4_FM0));
894 cpc_writeb(falcbase + F_REG(FMR0, ch),
895 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
896 cpc_writeb(falcbase + F_REG(FMR2, ch),
897 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
898 break;
899 }
900
901 /* Enable Automatic Resynchronization */
902 cpc_writeb(falcbase + F_REG(FMR4, ch),
903 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
904
905 /* Transmit Automatic Remote Alarm */
906 cpc_writeb(falcbase + F_REG(FMR2, ch),
907 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
908
909 /* Channel translation mode 1 : one to one */
910 cpc_writeb(falcbase + F_REG(FMR1, ch),
911 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
912
913 /* No signaling */
914 cpc_writeb(falcbase + F_REG(FMR1, ch),
915 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
916 cpc_writeb(falcbase + F_REG(FMR5, ch),
917 cpc_readb(falcbase + F_REG(FMR5, ch)) &
918 ~(FMR5_EIBR | FMR5_SRS));
919 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
920
921 cpc_writeb(falcbase + F_REG(LIM1, ch),
922 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
923
924 switch (conf->lbo) {
925 /* Provides proper Line Build Out */
926 case PC300_LBO_0_DB:
927 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
928 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
929 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
930 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
931 break;
932 case PC300_LBO_7_5_DB:
933 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
934 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
935 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
936 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
937 break;
938 case PC300_LBO_15_DB:
939 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
940 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
941 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
942 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
943 break;
944 case PC300_LBO_22_5_DB:
945 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
946 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
947 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
948 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
949 break;
950 }
951
952 /* Transmit Clock-Slot Offset */
953 cpc_writeb(falcbase + F_REG(XC0, ch),
954 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
955 /* Transmit Time-slot Offset */
956 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
957 /* Receive Clock-Slot offset */
958 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
959 /* Receive Time-slot offset */
960 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
961
962 /* LOS Detection after 176 consecutive 0s */
963 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
964 /* LOS Recovery after 22 ones in the time window of PCD */
965 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
966
967 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
968
969 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
970 cpc_writeb(falcbase + F_REG(RC1, ch),
971 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
972 }
973
974 falc_close_all_timeslots(card, ch);
975 }
976
977 static void falc_init_e1(pc300_t * card, int ch)
978 {
979 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
980 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
981 falc_t *pfalc = (falc_t *) & chan->falc;
982 void __iomem *falcbase = card->hw.falcbase;
983 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
984
985 /* Switch to E1 mode (PCM 30) */
986 cpc_writeb(falcbase + F_REG(FMR1, ch),
987 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
988
989 /* Clock mode */
990 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
991 cpc_writeb(falcbase + F_REG(LIM0, ch),
992 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
993 } else { /* Slave mode */
994 cpc_writeb(falcbase + F_REG(LIM0, ch),
995 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
996 }
997 cpc_writeb(falcbase + F_REG(LOOP, ch),
998 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
999
1000 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1001 cpc_writeb(falcbase + F_REG(FMR0, ch),
1002 cpc_readb(falcbase + F_REG(FMR0, ch)) &
1003 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1004
1005 switch (conf->lcode) {
1006 case PC300_LC_AMI:
1007 cpc_writeb(falcbase + F_REG(FMR0, ch),
1008 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1009 FMR0_XC1 | FMR0_RC1);
1010 break;
1011
1012 case PC300_LC_HDB3:
1013 cpc_writeb(falcbase + F_REG(FMR0, ch),
1014 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1015 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1016 break;
1017
1018 case PC300_LC_NRZ:
1019 break;
1020 }
1021
1022 cpc_writeb(falcbase + F_REG(LIM0, ch),
1023 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1024 /* Set interface mode to 2 MBPS */
1025 cpc_writeb(falcbase + F_REG(FMR1, ch),
1026 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1027
1028 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1029 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1030 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1031
1032 switch (conf->fr_mode) {
1033 case PC300_FR_MF_CRC4:
1034 pfalc->multiframe_mode = 1;
1035 cpc_writeb(falcbase + F_REG(FMR1, ch),
1036 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1037 cpc_writeb(falcbase + F_REG(FMR2, ch),
1038 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1039 cpc_writeb(falcbase + F_REG(FMR2, ch),
1040 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1041 cpc_writeb(falcbase + F_REG(FMR3, ch),
1042 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1043
1044 /* MultiFrame Resynchronization */
1045 cpc_writeb(falcbase + F_REG(FMR1, ch),
1046 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1047
1048 /* Automatic Loss of Multiframe > 914 CRC errors */
1049 cpc_writeb(falcbase + F_REG(FMR2, ch),
1050 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1051
1052 /* S1 and SI1/SI2 spare Bits set to 1 */
1053 cpc_writeb(falcbase + F_REG(XSP, ch),
1054 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1055 cpc_writeb(falcbase + F_REG(XSP, ch),
1056 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1057 cpc_writeb(falcbase + F_REG(XSP, ch),
1058 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1059
1060 /* Automatic Force Resynchronization */
1061 cpc_writeb(falcbase + F_REG(FMR1, ch),
1062 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1063
1064 /* Transmit Automatic Remote Alarm */
1065 cpc_writeb(falcbase + F_REG(FMR2, ch),
1066 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1067
1068 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1069 cpc_writeb(falcbase + F_REG(XSW, ch),
1070 cpc_readb(falcbase + F_REG(XSW, ch)) |
1071 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1072 break;
1073
1074 case PC300_FR_MF_NON_CRC4:
1075 case PC300_FR_D4:
1076 pfalc->multiframe_mode = 0;
1077 cpc_writeb(falcbase + F_REG(FMR1, ch),
1078 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1079 cpc_writeb(falcbase + F_REG(FMR2, ch),
1080 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1081 ~(FMR2_RFS1 | FMR2_RFS0));
1082 cpc_writeb(falcbase + F_REG(XSW, ch),
1083 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1084 cpc_writeb(falcbase + F_REG(XSP, ch),
1085 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1086
1087 /* Automatic Force Resynchronization */
1088 cpc_writeb(falcbase + F_REG(FMR1, ch),
1089 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1090
1091 /* Transmit Automatic Remote Alarm */
1092 cpc_writeb(falcbase + F_REG(FMR2, ch),
1093 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1094
1095 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1096 cpc_writeb(falcbase + F_REG(XSW, ch),
1097 cpc_readb(falcbase + F_REG(XSW, ch)) |
1098 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1099 break;
1100
1101 case PC300_FR_UNFRAMED:
1102 pfalc->multiframe_mode = 0;
1103 cpc_writeb(falcbase + F_REG(FMR1, ch),
1104 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1105 cpc_writeb(falcbase + F_REG(FMR2, ch),
1106 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1107 ~(FMR2_RFS1 | FMR2_RFS0));
1108 cpc_writeb(falcbase + F_REG(XSP, ch),
1109 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1110 cpc_writeb(falcbase + F_REG(XSW, ch),
1111 cpc_readb(falcbase + F_REG(XSW, ch)) &
1112 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1113 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1114 cpc_writeb(falcbase + F_REG(FMR2, ch),
1115 cpc_readb(falcbase + F_REG(FMR2, ch)) |
1116 (FMR2_RTM | FMR2_DAIS));
1117 cpc_writeb(falcbase + F_REG(FMR2, ch),
1118 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1119 cpc_writeb(falcbase + F_REG(FMR1, ch),
1120 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1121 pfalc->sync = 1;
1122 cpc_writeb(falcbase + card->hw.cpld_reg2,
1123 cpc_readb(falcbase + card->hw.cpld_reg2) |
1124 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1125 break;
1126 }
1127
1128 /* No signaling */
1129 cpc_writeb(falcbase + F_REG(XSP, ch),
1130 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1131 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1132
1133 cpc_writeb(falcbase + F_REG(LIM1, ch),
1134 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1135 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1136
1137 /* Transmit Clock-Slot Offset */
1138 cpc_writeb(falcbase + F_REG(XC0, ch),
1139 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1140 /* Transmit Time-slot Offset */
1141 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1142 /* Receive Clock-Slot offset */
1143 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1144 /* Receive Time-slot offset */
1145 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1146
1147 /* LOS Detection after 176 consecutive 0s */
1148 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1149 /* LOS Recovery after 22 ones in the time window of PCD */
1150 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1151
1152 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1153
1154 falc_close_all_timeslots(card, ch);
1155 }
1156
1157 static void falc_init_hdlc(pc300_t * card, int ch)
1158 {
1159 void __iomem *falcbase = card->hw.falcbase;
1160 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1161 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1162
1163 /* Enable transparent data transfer */
1164 if (conf->fr_mode == PC300_FR_UNFRAMED) {
1165 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1166 } else {
1167 cpc_writeb(falcbase + F_REG(MODE, ch),
1168 cpc_readb(falcbase + F_REG(MODE, ch)) |
1169 (MODE_HRAC | MODE_MDS2));
1170 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1171 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1172 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1173 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1174 }
1175
1176 /* Tx/Rx reset */
1177 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1178
1179 /* Enable interrupt sources */
1180 falc_intr_enable(card, ch);
1181 }
1182
1183 static void te_config(pc300_t * card, int ch)
1184 {
1185 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1186 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1187 falc_t *pfalc = (falc_t *) & chan->falc;
1188 void __iomem *falcbase = card->hw.falcbase;
1189 u8 dummy;
1190 unsigned long flags;
1191
1192 memset(pfalc, 0, sizeof(falc_t));
1193 switch (conf->media) {
1194 case IF_IFACE_T1:
1195 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1196 pfalc->offset = 1;
1197 break;
1198 case IF_IFACE_E1:
1199 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1200 pfalc->offset = 0;
1201 break;
1202 }
1203 if (conf->tslot_bitmap == 0xffffffffUL)
1204 pfalc->full_bandwidth = 1;
1205 else
1206 pfalc->full_bandwidth = 0;
1207
1208 CPC_LOCK(card, flags);
1209 /* Reset the FALC chip */
1210 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1211 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1212 (CPLD_REG1_FALC_RESET << (2 * ch)));
1213 udelay(10000);
1214 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1215 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1216 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1217
1218 if (conf->media == IF_IFACE_T1) {
1219 falc_init_t1(card, ch);
1220 } else {
1221 falc_init_e1(card, ch);
1222 }
1223 falc_init_hdlc(card, ch);
1224 if (conf->rx_sens == PC300_RX_SENS_SH) {
1225 cpc_writeb(falcbase + F_REG(LIM0, ch),
1226 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1227 } else {
1228 cpc_writeb(falcbase + F_REG(LIM0, ch),
1229 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1230 }
1231 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1232 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1233 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1234
1235 /* Clear all interrupt registers */
1236 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1237 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1238 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1239 cpc_readb(falcbase + F_REG(FISR3, ch));
1240 CPC_UNLOCK(card, flags);
1241 }
1242
1243 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1244 {
1245 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1246 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1247 falc_t *pfalc = (falc_t *) & chan->falc;
1248 void __iomem *falcbase = card->hw.falcbase;
1249
1250 /* Verify LOS */
1251 if (frs0 & FRS0_LOS) {
1252 if (!pfalc->red_alarm) {
1253 pfalc->red_alarm = 1;
1254 pfalc->los++;
1255 if (!pfalc->blue_alarm) {
1256 // EVENT_FALC_ABNORMAL
1257 if (conf->media == IF_IFACE_T1) {
1258 /* Disable this interrupt as it may otherwise interfere
1259 * with other working boards. */
1260 cpc_writeb(falcbase + F_REG(IMR0, ch),
1261 cpc_readb(falcbase + F_REG(IMR0, ch))
1262 | IMR0_PDEN);
1263 }
1264 falc_disable_comm(card, ch);
1265 // EVENT_FALC_ABNORMAL
1266 }
1267 }
1268 } else {
1269 if (pfalc->red_alarm) {
1270 pfalc->red_alarm = 0;
1271 pfalc->losr++;
1272 }
1273 }
1274
1275 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1276 /* Verify AIS alarm */
1277 if (frs0 & FRS0_AIS) {
1278 if (!pfalc->blue_alarm) {
1279 pfalc->blue_alarm = 1;
1280 pfalc->ais++;
1281 // EVENT_AIS
1282 if (conf->media == IF_IFACE_T1) {
1283 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1284 cpc_writeb(falcbase + F_REG(IMR0, ch),
1285 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1286 }
1287 falc_disable_comm(card, ch);
1288 // EVENT_AIS
1289 }
1290 } else {
1291 pfalc->blue_alarm = 0;
1292 }
1293
1294 /* Verify LFA */
1295 if (frs0 & FRS0_LFA) {
1296 if (!pfalc->loss_fa) {
1297 pfalc->loss_fa = 1;
1298 pfalc->lfa++;
1299 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1300 // EVENT_FALC_ABNORMAL
1301 if (conf->media == IF_IFACE_T1) {
1302 /* Disable this interrupt as it may otherwise
1303 * interfere with other working boards. */
1304 cpc_writeb(falcbase + F_REG(IMR0, ch),
1305 cpc_readb(falcbase + F_REG(IMR0, ch))
1306 | IMR0_PDEN);
1307 }
1308 falc_disable_comm(card, ch);
1309 // EVENT_FALC_ABNORMAL
1310 }
1311 }
1312 } else {
1313 if (pfalc->loss_fa) {
1314 pfalc->loss_fa = 0;
1315 pfalc->farec++;
1316 }
1317 }
1318
1319 /* Verify LMFA */
1320 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1321 /* D4 or CRC4 frame mode */
1322 if (!pfalc->loss_mfa) {
1323 pfalc->loss_mfa = 1;
1324 pfalc->lmfa++;
1325 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1326 !pfalc->loss_fa) {
1327 // EVENT_FALC_ABNORMAL
1328 if (conf->media == IF_IFACE_T1) {
1329 /* Disable this interrupt as it may otherwise
1330 * interfere with other working boards. */
1331 cpc_writeb(falcbase + F_REG(IMR0, ch),
1332 cpc_readb(falcbase + F_REG(IMR0, ch))
1333 | IMR0_PDEN);
1334 }
1335 falc_disable_comm(card, ch);
1336 // EVENT_FALC_ABNORMAL
1337 }
1338 }
1339 } else {
1340 pfalc->loss_mfa = 0;
1341 }
1342
1343 /* Verify Remote Alarm */
1344 if (frs0 & FRS0_RRA) {
1345 if (!pfalc->yellow_alarm) {
1346 pfalc->yellow_alarm = 1;
1347 pfalc->rai++;
1348 if (pfalc->sync) {
1349 // EVENT_RAI
1350 falc_disable_comm(card, ch);
1351 // EVENT_RAI
1352 }
1353 }
1354 } else {
1355 pfalc->yellow_alarm = 0;
1356 }
1357 } /* if !PC300_UNFRAMED */
1358
1359 if (pfalc->red_alarm || pfalc->loss_fa ||
1360 pfalc->loss_mfa || pfalc->blue_alarm) {
1361 if (pfalc->sync) {
1362 pfalc->sync = 0;
1363 chan->d.line_off++;
1364 cpc_writeb(falcbase + card->hw.cpld_reg2,
1365 cpc_readb(falcbase + card->hw.cpld_reg2) &
1366 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1367 }
1368 } else {
1369 if (!pfalc->sync) {
1370 pfalc->sync = 1;
1371 chan->d.line_on++;
1372 cpc_writeb(falcbase + card->hw.cpld_reg2,
1373 cpc_readb(falcbase + card->hw.cpld_reg2) |
1374 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1375 }
1376 }
1377
1378 if (pfalc->sync && !pfalc->yellow_alarm) {
1379 if (!pfalc->active) {
1380 // EVENT_FALC_NORMAL
1381 if (pfalc->loop_active) {
1382 return;
1383 }
1384 if (conf->media == IF_IFACE_T1) {
1385 cpc_writeb(falcbase + F_REG(IMR0, ch),
1386 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1387 }
1388 falc_enable_comm(card, ch);
1389 // EVENT_FALC_NORMAL
1390 pfalc->active = 1;
1391 }
1392 } else {
1393 if (pfalc->active) {
1394 pfalc->active = 0;
1395 }
1396 }
1397 }
1398
1399 static void falc_update_stats(pc300_t * card, int ch)
1400 {
1401 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1402 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1403 falc_t *pfalc = (falc_t *) & chan->falc;
1404 void __iomem *falcbase = card->hw.falcbase;
1405 u16 counter;
1406
1407 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1408 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1409 pfalc->fec += counter;
1410
1411 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1412 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1413 pfalc->cvc += counter;
1414
1415 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1416 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1417 pfalc->cec += counter;
1418
1419 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1420 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1421 pfalc->ebc += counter;
1422
1423 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1424 mdelay(10);
1425 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1426 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1427 pfalc->bec += counter;
1428
1429 if (((conf->media == IF_IFACE_T1) &&
1430 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1431 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1432 ||
1433 ((conf->media == IF_IFACE_E1) &&
1434 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1435 pfalc->prbs = 2;
1436 } else {
1437 pfalc->prbs = 1;
1438 }
1439 }
1440 }
1441
1442 /*----------------------------------------------------------------------------
1443 * falc_remote_loop
1444 *----------------------------------------------------------------------------
1445 * Description: In the remote loopback mode the clock and data recovered
1446 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1447 * to the line outputs XL1/2 or XDOP/XDON via the analog
1448 * transmitter. As in normal mode they are processsed by
1449 * the synchronizer and then sent to the system interface.
1450 *----------------------------------------------------------------------------
1451 */
1452 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1453 {
1454 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1455 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1456 falc_t *pfalc = (falc_t *) & chan->falc;
1457 void __iomem *falcbase = card->hw.falcbase;
1458
1459 if (loop_on) {
1460 // EVENT_FALC_ABNORMAL
1461 if (conf->media == IF_IFACE_T1) {
1462 /* Disable this interrupt as it may otherwise interfere with
1463 * other working boards. */
1464 cpc_writeb(falcbase + F_REG(IMR0, ch),
1465 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1466 }
1467 falc_disable_comm(card, ch);
1468 // EVENT_FALC_ABNORMAL
1469 cpc_writeb(falcbase + F_REG(LIM1, ch),
1470 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1471 pfalc->loop_active = 1;
1472 } else {
1473 cpc_writeb(falcbase + F_REG(LIM1, ch),
1474 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1475 pfalc->sync = 0;
1476 cpc_writeb(falcbase + card->hw.cpld_reg2,
1477 cpc_readb(falcbase + card->hw.cpld_reg2) &
1478 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1479 pfalc->active = 0;
1480 falc_issue_cmd(card, ch, CMDR_XRES);
1481 pfalc->loop_active = 0;
1482 }
1483 }
1484
1485 /*----------------------------------------------------------------------------
1486 * falc_local_loop
1487 *----------------------------------------------------------------------------
1488 * Description: The local loopback mode disconnects the receive lines
1489 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1490 * signals coming from the line the data provided by system
1491 * interface are routed through the analog receiver back to
1492 * the system interface. The unipolar bit stream will be
1493 * undisturbed transmitted on the line. Receiver and transmitter
1494 * coding must be identical.
1495 *----------------------------------------------------------------------------
1496 */
1497 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1498 {
1499 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1500 falc_t *pfalc = (falc_t *) & chan->falc;
1501 void __iomem *falcbase = card->hw.falcbase;
1502
1503 if (loop_on) {
1504 cpc_writeb(falcbase + F_REG(LIM0, ch),
1505 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1506 pfalc->loop_active = 1;
1507 } else {
1508 cpc_writeb(falcbase + F_REG(LIM0, ch),
1509 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1510 pfalc->loop_active = 0;
1511 }
1512 }
1513
1514 /*----------------------------------------------------------------------------
1515 * falc_payload_loop
1516 *----------------------------------------------------------------------------
1517 * Description: This routine allows to enable/disable payload loopback.
1518 * When the payload loop is activated, the received 192 bits
1519 * of payload data will be looped back to the transmit
1520 * direction. The framing bits, CRC6 and DL bits are not
1521 * looped. They are originated by the FALC-LH transmitter.
1522 *----------------------------------------------------------------------------
1523 */
1524 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1525 {
1526 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1527 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1528 falc_t *pfalc = (falc_t *) & chan->falc;
1529 void __iomem *falcbase = card->hw.falcbase;
1530
1531 if (loop_on) {
1532 // EVENT_FALC_ABNORMAL
1533 if (conf->media == IF_IFACE_T1) {
1534 /* Disable this interrupt as it may otherwise interfere with
1535 * other working boards. */
1536 cpc_writeb(falcbase + F_REG(IMR0, ch),
1537 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1538 }
1539 falc_disable_comm(card, ch);
1540 // EVENT_FALC_ABNORMAL
1541 cpc_writeb(falcbase + F_REG(FMR2, ch),
1542 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1543 if (conf->media == IF_IFACE_T1) {
1544 cpc_writeb(falcbase + F_REG(FMR4, ch),
1545 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1546 } else {
1547 cpc_writeb(falcbase + F_REG(FMR5, ch),
1548 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1549 }
1550 falc_open_all_timeslots(card, ch);
1551 pfalc->loop_active = 2;
1552 } else {
1553 cpc_writeb(falcbase + F_REG(FMR2, ch),
1554 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1555 if (conf->media == IF_IFACE_T1) {
1556 cpc_writeb(falcbase + F_REG(FMR4, ch),
1557 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1558 } else {
1559 cpc_writeb(falcbase + F_REG(FMR5, ch),
1560 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1561 }
1562 pfalc->sync = 0;
1563 cpc_writeb(falcbase + card->hw.cpld_reg2,
1564 cpc_readb(falcbase + card->hw.cpld_reg2) &
1565 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1566 pfalc->active = 0;
1567 falc_issue_cmd(card, ch, CMDR_XRES);
1568 pfalc->loop_active = 0;
1569 }
1570 }
1571
1572 /*----------------------------------------------------------------------------
1573 * turn_off_xlu
1574 *----------------------------------------------------------------------------
1575 * Description: Turns XLU bit off in the proper register
1576 *----------------------------------------------------------------------------
1577 */
1578 static void turn_off_xlu(pc300_t * card, int ch)
1579 {
1580 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1581 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1582 void __iomem *falcbase = card->hw.falcbase;
1583
1584 if (conf->media == IF_IFACE_T1) {
1585 cpc_writeb(falcbase + F_REG(FMR5, ch),
1586 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1587 } else {
1588 cpc_writeb(falcbase + F_REG(FMR3, ch),
1589 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1590 }
1591 }
1592
1593 /*----------------------------------------------------------------------------
1594 * turn_off_xld
1595 *----------------------------------------------------------------------------
1596 * Description: Turns XLD bit off in the proper register
1597 *----------------------------------------------------------------------------
1598 */
1599 static void turn_off_xld(pc300_t * card, int ch)
1600 {
1601 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1602 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1603 void __iomem *falcbase = card->hw.falcbase;
1604
1605 if (conf->media == IF_IFACE_T1) {
1606 cpc_writeb(falcbase + F_REG(FMR5, ch),
1607 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1608 } else {
1609 cpc_writeb(falcbase + F_REG(FMR3, ch),
1610 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1611 }
1612 }
1613
1614 /*----------------------------------------------------------------------------
1615 * falc_generate_loop_up_code
1616 *----------------------------------------------------------------------------
1617 * Description: This routine writes the proper FALC chip register in order
1618 * to generate a LOOP activation code over a T1/E1 line.
1619 *----------------------------------------------------------------------------
1620 */
1621 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1622 {
1623 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1624 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1625 falc_t *pfalc = (falc_t *) & chan->falc;
1626 void __iomem *falcbase = card->hw.falcbase;
1627
1628 if (conf->media == IF_IFACE_T1) {
1629 cpc_writeb(falcbase + F_REG(FMR5, ch),
1630 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1631 } else {
1632 cpc_writeb(falcbase + F_REG(FMR3, ch),
1633 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1634 }
1635 // EVENT_FALC_ABNORMAL
1636 if (conf->media == IF_IFACE_T1) {
1637 /* Disable this interrupt as it may otherwise interfere with
1638 * other working boards. */
1639 cpc_writeb(falcbase + F_REG(IMR0, ch),
1640 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1641 }
1642 falc_disable_comm(card, ch);
1643 // EVENT_FALC_ABNORMAL
1644 pfalc->loop_gen = 1;
1645 }
1646
1647 /*----------------------------------------------------------------------------
1648 * falc_generate_loop_down_code
1649 *----------------------------------------------------------------------------
1650 * Description: This routine writes the proper FALC chip register in order
1651 * to generate a LOOP deactivation code over a T1/E1 line.
1652 *----------------------------------------------------------------------------
1653 */
1654 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1655 {
1656 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1657 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1658 falc_t *pfalc = (falc_t *) & chan->falc;
1659 void __iomem *falcbase = card->hw.falcbase;
1660
1661 if (conf->media == IF_IFACE_T1) {
1662 cpc_writeb(falcbase + F_REG(FMR5, ch),
1663 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1664 } else {
1665 cpc_writeb(falcbase + F_REG(FMR3, ch),
1666 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1667 }
1668 pfalc->sync = 0;
1669 cpc_writeb(falcbase + card->hw.cpld_reg2,
1670 cpc_readb(falcbase + card->hw.cpld_reg2) &
1671 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1672 pfalc->active = 0;
1673 //? falc_issue_cmd(card, ch, CMDR_XRES);
1674 pfalc->loop_gen = 0;
1675 }
1676
1677 /*----------------------------------------------------------------------------
1678 * falc_pattern_test
1679 *----------------------------------------------------------------------------
1680 * Description: This routine generates a pattern code and checks
1681 * it on the reception side.
1682 *----------------------------------------------------------------------------
1683 */
1684 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1685 {
1686 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1687 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1688 falc_t *pfalc = (falc_t *) & chan->falc;
1689 void __iomem *falcbase = card->hw.falcbase;
1690
1691 if (activate) {
1692 pfalc->prbs = 1;
1693 pfalc->bec = 0;
1694 if (conf->media == IF_IFACE_T1) {
1695 /* Disable local loop activation/deactivation detect */
1696 cpc_writeb(falcbase + F_REG(IMR3, ch),
1697 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1698 } else {
1699 /* Disable local loop activation/deactivation detect */
1700 cpc_writeb(falcbase + F_REG(IMR1, ch),
1701 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1702 }
1703 /* Activates generation and monitoring of PRBS
1704 * (Pseudo Random Bit Sequence) */
1705 cpc_writeb(falcbase + F_REG(LCR1, ch),
1706 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1707 } else {
1708 pfalc->prbs = 0;
1709 /* Deactivates generation and monitoring of PRBS
1710 * (Pseudo Random Bit Sequence) */
1711 cpc_writeb(falcbase + F_REG(LCR1, ch),
1712 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1713 if (conf->media == IF_IFACE_T1) {
1714 /* Enable local loop activation/deactivation detect */
1715 cpc_writeb(falcbase + F_REG(IMR3, ch),
1716 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1717 } else {
1718 /* Enable local loop activation/deactivation detect */
1719 cpc_writeb(falcbase + F_REG(IMR1, ch),
1720 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1721 }
1722 }
1723 }
1724
1725 /*----------------------------------------------------------------------------
1726 * falc_pattern_test_error
1727 *----------------------------------------------------------------------------
1728 * Description: This routine returns the bit error counter value
1729 *----------------------------------------------------------------------------
1730 */
1731 static u16 falc_pattern_test_error(pc300_t * card, int ch)
1732 {
1733 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1734 falc_t *pfalc = (falc_t *) & chan->falc;
1735
1736 return (pfalc->bec);
1737 }
1738
1739 /**********************************/
1740 /*** Net Interface Routines ***/
1741 /**********************************/
1742
1743 static void
1744 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1745 {
1746 struct sk_buff *skb;
1747
1748 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1749 printk("%s: out of memory\n", dev->name);
1750 return;
1751 }
1752 skb_put(skb, 10 + skb_main->len);
1753
1754 skb->dev = dev;
1755 skb->protocol = htons(ETH_P_CUST);
1756 skb_reset_mac_header(skb);
1757 skb->pkt_type = PACKET_HOST;
1758 skb->len = 10 + skb_main->len;
1759
1760 skb_copy_to_linear_data(skb, dev->name, 5);
1761 skb->data[5] = '[';
1762 skb->data[6] = rx_tx;
1763 skb->data[7] = ']';
1764 skb->data[8] = ':';
1765 skb->data[9] = ' ';
1766 skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1767
1768 netif_rx(skb);
1769 }
1770
1771 static void cpc_tx_timeout(struct net_device *dev)
1772 {
1773 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1774 pc300ch_t *chan = (pc300ch_t *) d->chan;
1775 pc300_t *card = (pc300_t *) chan->card;
1776 int ch = chan->channel;
1777 unsigned long flags;
1778 u8 ilar;
1779
1780 dev->stats.tx_errors++;
1781 dev->stats.tx_aborted_errors++;
1782 CPC_LOCK(card, flags);
1783 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1784 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1785 cpc_writeb(card->hw.scabase + ILAR, ilar);
1786 cpc_writeb(card->hw.scabase + DMER, 0x80);
1787 }
1788 if (card->hw.type == PC300_TE) {
1789 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1790 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1791 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1792 }
1793 dev->trans_start = jiffies;
1794 CPC_UNLOCK(card, flags);
1795 netif_wake_queue(dev);
1796 }
1797
1798 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1799 {
1800 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1801 pc300ch_t *chan = (pc300ch_t *) d->chan;
1802 pc300_t *card = (pc300_t *) chan->card;
1803 int ch = chan->channel;
1804 unsigned long flags;
1805 #ifdef PC300_DEBUG_TX
1806 int i;
1807 #endif
1808
1809 if (!netif_carrier_ok(dev)) {
1810 /* DCD must be OFF: drop packet */
1811 dev_kfree_skb(skb);
1812 dev->stats.tx_errors++;
1813 dev->stats.tx_carrier_errors++;
1814 return 0;
1815 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1816 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1817 dev->stats.tx_errors++;
1818 dev->stats.tx_carrier_errors++;
1819 dev_kfree_skb(skb);
1820 netif_carrier_off(dev);
1821 CPC_LOCK(card, flags);
1822 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1823 if (card->hw.type == PC300_TE) {
1824 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1825 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1826 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1827 }
1828 CPC_UNLOCK(card, flags);
1829 netif_wake_queue(dev);
1830 return 0;
1831 }
1832
1833 /* Write buffer to DMA buffers */
1834 if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1835 // printk("%s: write error. Dropping TX packet.\n", dev->name);
1836 netif_stop_queue(dev);
1837 dev_kfree_skb(skb);
1838 dev->stats.tx_errors++;
1839 dev->stats.tx_dropped++;
1840 return 0;
1841 }
1842 #ifdef PC300_DEBUG_TX
1843 printk("%s T:", dev->name);
1844 for (i = 0; i < skb->len; i++)
1845 printk(" %02x", *(skb->data + i));
1846 printk("\n");
1847 #endif
1848
1849 if (d->trace_on) {
1850 cpc_trace(dev, skb, 'T');
1851 }
1852 dev->trans_start = jiffies;
1853
1854 /* Start transmission */
1855 CPC_LOCK(card, flags);
1856 /* verify if it has more than one free descriptor */
1857 if (card->chan[ch].nfree_tx_bd <= 1) {
1858 /* don't have so stop the queue */
1859 netif_stop_queue(dev);
1860 }
1861 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1862 TX_BD_ADDR(ch, chan->tx_next_bd));
1863 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1864 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1865 if (card->hw.type == PC300_TE) {
1866 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1867 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1868 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1869 }
1870 CPC_UNLOCK(card, flags);
1871 dev_kfree_skb(skb);
1872
1873 return 0;
1874 }
1875
1876 static void cpc_net_rx(struct net_device *dev)
1877 {
1878 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1879 pc300ch_t *chan = (pc300ch_t *) d->chan;
1880 pc300_t *card = (pc300_t *) chan->card;
1881 int ch = chan->channel;
1882 #ifdef PC300_DEBUG_RX
1883 int i;
1884 #endif
1885 int rxb;
1886 struct sk_buff *skb;
1887
1888 while (1) {
1889 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1890 return;
1891
1892 if (!netif_carrier_ok(dev)) {
1893 /* DCD must be OFF: drop packet */
1894 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1895 skb = NULL;
1896 } else {
1897 if (rxb > (dev->mtu + 40)) { /* add headers */
1898 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1899 skb = NULL;
1900 } else {
1901 skb = dev_alloc_skb(rxb);
1902 if (skb == NULL) {
1903 printk("%s: Memory squeeze!!\n", dev->name);
1904 return;
1905 }
1906 skb->dev = dev;
1907 }
1908 }
1909
1910 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1911 #ifdef PC300_DEBUG_RX
1912 printk("%s: rxb = %x\n", dev->name, rxb);
1913 #endif
1914 if ((skb == NULL) && (rxb > 0)) {
1915 /* rxb > dev->mtu */
1916 dev->stats.rx_errors++;
1917 dev->stats.rx_length_errors++;
1918 continue;
1919 }
1920
1921 if (rxb < 0) { /* Invalid frame */
1922 rxb = -rxb;
1923 if (rxb & DST_OVR) {
1924 dev->stats.rx_errors++;
1925 dev->stats.rx_fifo_errors++;
1926 }
1927 if (rxb & DST_CRC) {
1928 dev->stats.rx_errors++;
1929 dev->stats.rx_crc_errors++;
1930 }
1931 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1932 dev->stats.rx_errors++;
1933 dev->stats.rx_frame_errors++;
1934 }
1935 }
1936 if (skb) {
1937 dev_kfree_skb_irq(skb);
1938 }
1939 continue;
1940 }
1941
1942 dev->stats.rx_bytes += rxb;
1943
1944 #ifdef PC300_DEBUG_RX
1945 printk("%s R:", dev->name);
1946 for (i = 0; i < skb->len; i++)
1947 printk(" %02x", *(skb->data + i));
1948 printk("\n");
1949 #endif
1950 if (d->trace_on) {
1951 cpc_trace(dev, skb, 'R');
1952 }
1953 dev->stats.rx_packets++;
1954 skb->protocol = hdlc_type_trans(skb, dev);
1955 netif_rx(skb);
1956 }
1957 }
1958
1959 /************************************/
1960 /*** PC300 Interrupt Routines ***/
1961 /************************************/
1962 static void sca_tx_intr(pc300dev_t *dev)
1963 {
1964 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1965 pc300_t *card = (pc300_t *)chan->card;
1966 int ch = chan->channel;
1967 volatile pcsca_bd_t __iomem * ptdescr;
1968
1969 /* Clean up descriptors from previous transmission */
1970 ptdescr = (card->hw.rambase +
1971 TX_BD_ADDR(ch,chan->tx_first_bd));
1972 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1973 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1974 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1975 dev->dev->stats.tx_packets++;
1976 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1977 cpc_writeb(&ptdescr->status, DST_OSB);
1978 cpc_writew(&ptdescr->len, 0);
1979 chan->nfree_tx_bd++;
1980 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1981 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1982 }
1983
1984 #ifdef CONFIG_PC300_MLPPP
1985 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1986 cpc_tty_trigger_poll(dev);
1987 } else {
1988 #endif
1989 /* Tell the upper layer we are ready to transmit more packets */
1990 netif_wake_queue(dev->dev);
1991 #ifdef CONFIG_PC300_MLPPP
1992 }
1993 #endif
1994 }
1995
1996 static void sca_intr(pc300_t * card)
1997 {
1998 void __iomem *scabase = card->hw.scabase;
1999 volatile u32 status;
2000 int ch;
2001 int intr_count = 0;
2002 unsigned char dsr_rx;
2003
2004 while ((status = cpc_readl(scabase + ISR0)) != 0) {
2005 for (ch = 0; ch < card->hw.nchan; ch++) {
2006 pc300ch_t *chan = &card->chan[ch];
2007 pc300dev_t *d = &chan->d;
2008 struct net_device *dev = d->dev;
2009
2010 spin_lock(&card->card_lock);
2011
2012 /**** Reception ****/
2013 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2014 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
2015
2016 /* Clear RX interrupts */
2017 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2018
2019 #ifdef PC300_DEBUG_INTR
2020 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2021 ch, status, drx_stat);
2022 #endif
2023 if (status & IR0_DRX(IR0_DMIA, ch)) {
2024 if (drx_stat & DSR_BOF) {
2025 #ifdef CONFIG_PC300_MLPPP
2026 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2027 /* verify if driver is TTY */
2028 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2029 rx_dma_stop(card, ch);
2030 }
2031 cpc_tty_receive(d);
2032 rx_dma_start(card, ch);
2033 } else
2034 #endif
2035 {
2036 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2037 rx_dma_stop(card, ch);
2038 }
2039 cpc_net_rx(dev);
2040 /* Discard invalid frames */
2041 dev->stats.rx_errors++;
2042 dev->stats.rx_over_errors++;
2043 chan->rx_first_bd = 0;
2044 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2045 rx_dma_start(card, ch);
2046 }
2047 }
2048 }
2049 if (status & IR0_DRX(IR0_DMIB, ch)) {
2050 if (drx_stat & DSR_EOM) {
2051 if (card->hw.type == PC300_TE) {
2052 cpc_writeb(card->hw.falcbase +
2053 card->hw.cpld_reg2,
2054 cpc_readb (card->hw.falcbase +
2055 card->hw.cpld_reg2) |
2056 (CPLD_REG2_FALC_LED1 << (2 * ch)));
2057 }
2058 #ifdef CONFIG_PC300_MLPPP
2059 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2060 /* verify if driver is TTY */
2061 cpc_tty_receive(d);
2062 } else {
2063 cpc_net_rx(dev);
2064 }
2065 #else
2066 cpc_net_rx(dev);
2067 #endif
2068 if (card->hw.type == PC300_TE) {
2069 cpc_writeb(card->hw.falcbase +
2070 card->hw.cpld_reg2,
2071 cpc_readb (card->hw.falcbase +
2072 card->hw.cpld_reg2) &
2073 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2074 }
2075 }
2076 }
2077 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2078 #ifdef PC300_DEBUG_INTR
2079 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2080 dev->name, ch, status, drx_stat, dsr_rx);
2081 #endif
2082 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2083 }
2084 }
2085
2086 /**** Transmission ****/
2087 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2088 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2089
2090 /* Clear TX interrupts */
2091 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2092
2093 #ifdef PC300_DEBUG_INTR
2094 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2095 ch, status, dtx_stat);
2096 #endif
2097 if (status & IR0_DTX(IR0_EFT, ch)) {
2098 if (dtx_stat & DSR_UDRF) {
2099 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2100 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2101 }
2102 if (card->hw.type == PC300_TE) {
2103 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2104 cpc_readb (card->hw.falcbase +
2105 card->hw.cpld_reg2) &
2106 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2107 }
2108 dev->stats.tx_errors++;
2109 dev->stats.tx_fifo_errors++;
2110 sca_tx_intr(d);
2111 }
2112 }
2113 if (status & IR0_DTX(IR0_DMIA, ch)) {
2114 if (dtx_stat & DSR_BOF) {
2115 }
2116 }
2117 if (status & IR0_DTX(IR0_DMIB, ch)) {
2118 if (dtx_stat & DSR_EOM) {
2119 if (card->hw.type == PC300_TE) {
2120 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2121 cpc_readb (card->hw.falcbase +
2122 card->hw.cpld_reg2) &
2123 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2124 }
2125 sca_tx_intr(d);
2126 }
2127 }
2128 }
2129
2130 /**** MSCI ****/
2131 if (status & IR0_M(IR0_RXINTA, ch)) {
2132 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
2133
2134 /* Clear MSCI interrupts */
2135 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2136
2137 #ifdef PC300_DEBUG_INTR
2138 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2139 ch, status, st1);
2140 #endif
2141 if (st1 & ST1_CDCD) { /* DCD changed */
2142 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2143 printk ("%s: DCD is OFF. Going administrative down.\n",
2144 dev->name);
2145 #ifdef CONFIG_PC300_MLPPP
2146 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2147 netif_carrier_off(dev);
2148 }
2149 #else
2150 netif_carrier_off(dev);
2151
2152 #endif
2153 card->chan[ch].d.line_off++;
2154 } else { /* DCD = 1 */
2155 printk ("%s: DCD is ON. Going administrative up.\n",
2156 dev->name);
2157 #ifdef CONFIG_PC300_MLPPP
2158 if (chan->conf.proto != PC300_PROTO_MLPPP)
2159 /* verify if driver is not TTY */
2160 #endif
2161 netif_carrier_on(dev);
2162 card->chan[ch].d.line_on++;
2163 }
2164 }
2165 }
2166 spin_unlock(&card->card_lock);
2167 }
2168 if (++intr_count == 10)
2169 /* Too much work at this board. Force exit */
2170 break;
2171 }
2172 }
2173
2174 static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
2175 {
2176 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2177 falc_t *pfalc = (falc_t *) & chan->falc;
2178 void __iomem *falcbase = card->hw.falcbase;
2179
2180 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2181 !pfalc->loop_gen) {
2182 if (frs1 & FRS1_LLBDD) {
2183 // A Line Loop Back Deactivation signal detected
2184 if (pfalc->loop_active) {
2185 falc_remote_loop(card, ch, 0);
2186 }
2187 } else {
2188 if ((frs1 & FRS1_LLBAD) &&
2189 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2190 // A Line Loop Back Activation signal detected
2191 if (!pfalc->loop_active) {
2192 falc_remote_loop(card, ch, 1);
2193 }
2194 }
2195 }
2196 }
2197 }
2198
2199 static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
2200 {
2201 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2202 falc_t *pfalc = (falc_t *) & chan->falc;
2203 void __iomem *falcbase = card->hw.falcbase;
2204
2205 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2206 !pfalc->loop_gen) {
2207 if (rsp & RSP_LLBDD) {
2208 // A Line Loop Back Deactivation signal detected
2209 if (pfalc->loop_active) {
2210 falc_remote_loop(card, ch, 0);
2211 }
2212 } else {
2213 if ((rsp & RSP_LLBAD) &&
2214 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2215 // A Line Loop Back Activation signal detected
2216 if (!pfalc->loop_active) {
2217 falc_remote_loop(card, ch, 1);
2218 }
2219 }
2220 }
2221 }
2222 }
2223
2224 static void falc_t1_intr(pc300_t * card, int ch)
2225 {
2226 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2227 falc_t *pfalc = (falc_t *) & chan->falc;
2228 void __iomem *falcbase = card->hw.falcbase;
2229 u8 isr0, isr3, gis;
2230 u8 dummy;
2231
2232 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2233 if (gis & GIS_ISR0) {
2234 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2235 if (isr0 & FISR0_PDEN) {
2236 /* Read the bit to clear the situation */
2237 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2238 FRS1_PDEN) {
2239 pfalc->pden++;
2240 }
2241 }
2242 }
2243
2244 if (gis & GIS_ISR1) {
2245 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2246 }
2247
2248 if (gis & GIS_ISR2) {
2249 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2250 }
2251
2252 if (gis & GIS_ISR3) {
2253 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2254 if (isr3 & FISR3_SEC) {
2255 pfalc->sec++;
2256 falc_update_stats(card, ch);
2257 falc_check_status(card, ch,
2258 cpc_readb(falcbase + F_REG(FRS0, ch)));
2259 }
2260 if (isr3 & FISR3_ES) {
2261 pfalc->es++;
2262 }
2263 if (isr3 & FISR3_LLBSC) {
2264 falc_t1_loop_detection(card, ch,
2265 cpc_readb(falcbase + F_REG(FRS1, ch)));
2266 }
2267 }
2268 }
2269 }
2270
2271 static void falc_e1_intr(pc300_t * card, int ch)
2272 {
2273 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2274 falc_t *pfalc = (falc_t *) & chan->falc;
2275 void __iomem *falcbase = card->hw.falcbase;
2276 u8 isr1, isr2, isr3, gis, rsp;
2277 u8 dummy;
2278
2279 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2280 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2281
2282 if (gis & GIS_ISR0) {
2283 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2284 }
2285 if (gis & GIS_ISR1) {
2286 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2287 if (isr1 & FISR1_XMB) {
2288 if ((pfalc->xmb_cause & 2)
2289 && pfalc->multiframe_mode) {
2290 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2291 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2292 cpc_writeb(falcbase + F_REG(XSP, ch),
2293 cpc_readb(falcbase + F_REG(XSP, ch))
2294 & ~XSP_AXS);
2295 } else {
2296 cpc_writeb(falcbase + F_REG(XSP, ch),
2297 cpc_readb(falcbase + F_REG(XSP, ch))
2298 | XSP_AXS);
2299 }
2300 }
2301 pfalc->xmb_cause = 0;
2302 cpc_writeb(falcbase + F_REG(IMR1, ch),
2303 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2304 }
2305 if (isr1 & FISR1_LLBSC) {
2306 falc_e1_loop_detection(card, ch, rsp);
2307 }
2308 }
2309 if (gis & GIS_ISR2) {
2310 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2311 if (isr2 & FISR2_T400MS) {
2312 cpc_writeb(falcbase + F_REG(XSW, ch),
2313 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2314 }
2315 if (isr2 & FISR2_MFAR) {
2316 cpc_writeb(falcbase + F_REG(XSW, ch),
2317 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2318 }
2319 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2320 pfalc->xmb_cause |= 2;
2321 cpc_writeb(falcbase + F_REG(IMR1, ch),
2322 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2323 }
2324 }
2325 if (gis & GIS_ISR3) {
2326 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2327 if (isr3 & FISR3_SEC) {
2328 pfalc->sec++;
2329 falc_update_stats(card, ch);
2330 falc_check_status(card, ch,
2331 cpc_readb(falcbase + F_REG(FRS0, ch)));
2332 }
2333 if (isr3 & FISR3_ES) {
2334 pfalc->es++;
2335 }
2336 }
2337 }
2338 }
2339
2340 static void falc_intr(pc300_t * card)
2341 {
2342 int ch;
2343
2344 for (ch = 0; ch < card->hw.nchan; ch++) {
2345 pc300ch_t *chan = &card->chan[ch];
2346 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2347
2348 if (conf->media == IF_IFACE_T1) {
2349 falc_t1_intr(card, ch);
2350 } else {
2351 falc_e1_intr(card, ch);
2352 }
2353 }
2354 }
2355
2356 static irqreturn_t cpc_intr(int irq, void *dev_id)
2357 {
2358 pc300_t *card = dev_id;
2359 volatile u8 plx_status;
2360
2361 if (!card) {
2362 #ifdef PC300_DEBUG_INTR
2363 printk("cpc_intr: spurious intr %d\n", irq);
2364 #endif
2365 return IRQ_NONE; /* spurious intr */
2366 }
2367
2368 if (!card->hw.rambase) {
2369 #ifdef PC300_DEBUG_INTR
2370 printk("cpc_intr: spurious intr2 %d\n", irq);
2371 #endif
2372 return IRQ_NONE; /* spurious intr */
2373 }
2374
2375 switch (card->hw.type) {
2376 case PC300_RSV:
2377 case PC300_X21:
2378 sca_intr(card);
2379 break;
2380
2381 case PC300_TE:
2382 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2383 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2384 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2385 sca_intr(card);
2386 }
2387 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2388 falc_intr(card);
2389 }
2390 }
2391 break;
2392 }
2393 return IRQ_HANDLED;
2394 }
2395
2396 static void cpc_sca_status(pc300_t * card, int ch)
2397 {
2398 u8 ilar;
2399 void __iomem *scabase = card->hw.scabase;
2400 unsigned long flags;
2401
2402 tx_dma_buf_check(card, ch);
2403 rx_dma_buf_check(card, ch);
2404 ilar = cpc_readb(scabase + ILAR);
2405 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2406 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2407 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2408 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2409 cpc_readl(scabase + DTX_REG(CDAL, ch)),
2410 cpc_readl(scabase + DTX_REG(EDAL, ch)));
2411 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2412 cpc_readl(scabase + DRX_REG(CDAL, ch)),
2413 cpc_readl(scabase + DRX_REG(EDAL, ch)),
2414 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2415 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2416 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2417 cpc_readb(scabase + DSR_RX(ch)));
2418 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2419 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2420 cpc_readb(scabase + DIR_TX(ch)),
2421 cpc_readb(scabase + DIR_RX(ch)));
2422 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2423 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2424 cpc_readb(scabase + FCT_TX(ch)),
2425 cpc_readb(scabase + FCT_RX(ch)));
2426 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2427 cpc_readb(scabase + M_REG(MD0, ch)),
2428 cpc_readb(scabase + M_REG(MD1, ch)),
2429 cpc_readb(scabase + M_REG(MD2, ch)),
2430 cpc_readb(scabase + M_REG(MD3, ch)),
2431 cpc_readb(scabase + M_REG(IDL, ch)));
2432 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2433 cpc_readb(scabase + M_REG(CMD, ch)),
2434 cpc_readb(scabase + M_REG(SA0, ch)),
2435 cpc_readb(scabase + M_REG(SA1, ch)),
2436 cpc_readb(scabase + M_REG(TFN, ch)),
2437 cpc_readb(scabase + M_REG(CTL, ch)));
2438 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2439 cpc_readb(scabase + M_REG(ST0, ch)),
2440 cpc_readb(scabase + M_REG(ST1, ch)),
2441 cpc_readb(scabase + M_REG(ST2, ch)),
2442 cpc_readb(scabase + M_REG(ST3, ch)),
2443 cpc_readb(scabase + M_REG(ST4, ch)));
2444 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2445 cpc_readb(scabase + M_REG(CST0, ch)),
2446 cpc_readb(scabase + M_REG(CST1, ch)),
2447 cpc_readb(scabase + M_REG(CST2, ch)),
2448 cpc_readb(scabase + M_REG(CST3, ch)),
2449 cpc_readb(scabase + M_REG(FST, ch)));
2450 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2451 cpc_readb(scabase + M_REG(TRC0, ch)),
2452 cpc_readb(scabase + M_REG(TRC1, ch)),
2453 cpc_readb(scabase + M_REG(RRC, ch)),
2454 cpc_readb(scabase + M_REG(TBN, ch)),
2455 cpc_readb(scabase + M_REG(RBN, ch)));
2456 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2457 cpc_readb(scabase + M_REG(TFS, ch)),
2458 cpc_readb(scabase + M_REG(TNR0, ch)),
2459 cpc_readb(scabase + M_REG(TNR1, ch)),
2460 cpc_readb(scabase + M_REG(RNR, ch)));
2461 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2462 cpc_readb(scabase + M_REG(TCR, ch)),
2463 cpc_readb(scabase + M_REG(RCR, ch)),
2464 cpc_readb(scabase + M_REG(TNR1, ch)),
2465 cpc_readb(scabase + M_REG(RNR, ch)));
2466 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2467 cpc_readb(scabase + M_REG(TXS, ch)),
2468 cpc_readb(scabase + M_REG(RXS, ch)),
2469 cpc_readb(scabase + M_REG(EXS, ch)),
2470 cpc_readb(scabase + M_REG(TMCT, ch)),
2471 cpc_readb(scabase + M_REG(TMCR, ch)));
2472 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2473 cpc_readb(scabase + M_REG(IE0, ch)),
2474 cpc_readb(scabase + M_REG(IE1, ch)),
2475 cpc_readb(scabase + M_REG(IE2, ch)),
2476 cpc_readb(scabase + M_REG(IE4, ch)),
2477 cpc_readb(scabase + M_REG(FIE, ch)));
2478 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2479
2480 if (ilar != 0) {
2481 CPC_LOCK(card, flags);
2482 cpc_writeb(scabase + ILAR, ilar);
2483 cpc_writeb(scabase + DMER, 0x80);
2484 CPC_UNLOCK(card, flags);
2485 }
2486 }
2487
2488 static void cpc_falc_status(pc300_t * card, int ch)
2489 {
2490 pc300ch_t *chan = &card->chan[ch];
2491 falc_t *pfalc = (falc_t *) & chan->falc;
2492 unsigned long flags;
2493
2494 CPC_LOCK(card, flags);
2495 printk("CH%d: %s %s %d channels\n",
2496 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2497 pfalc->num_channels);
2498
2499 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2500 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2501 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2502 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2503 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2504 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2505
2506 printk("\n");
2507 printk(" STATUS: %s %s %s %s %s %s\n",
2508 (pfalc->red_alarm ? "RED" : ""),
2509 (pfalc->blue_alarm ? "BLU" : ""),
2510 (pfalc->yellow_alarm ? "YEL" : ""),
2511 (pfalc->loss_fa ? "LFA" : ""),
2512 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2513 CPC_UNLOCK(card, flags);
2514 }
2515
2516 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2517 {
2518 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2519 return -EINVAL;
2520 dev->mtu = new_mtu;
2521 return 0;
2522 }
2523
2524 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2525 {
2526 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
2527 pc300ch_t *chan = (pc300ch_t *) d->chan;
2528 pc300_t *card = (pc300_t *) chan->card;
2529 pc300conf_t conf_aux;
2530 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2531 int ch = chan->channel;
2532 void __user *arg = ifr->ifr_data;
2533 struct if_settings *settings = &ifr->ifr_settings;
2534 void __iomem *scabase = card->hw.scabase;
2535
2536 if (!capable(CAP_NET_ADMIN))
2537 return -EPERM;
2538
2539 switch (cmd) {
2540 case SIOCGPC300CONF:
2541 #ifdef CONFIG_PC300_MLPPP
2542 if (conf->proto != PC300_PROTO_MLPPP) {
2543 conf->proto = /* FIXME hdlc->proto.id */ 0;
2544 }
2545 #else
2546 conf->proto = /* FIXME hdlc->proto.id */ 0;
2547 #endif
2548 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2549 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2550 if (!arg ||
2551 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2552 return -EINVAL;
2553 return 0;
2554 case SIOCSPC300CONF:
2555 if (!capable(CAP_NET_ADMIN))
2556 return -EPERM;
2557 if (!arg ||
2558 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2559 return -EINVAL;
2560 if (card->hw.cpld_id < 0x02 &&
2561 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2562 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2563 return -EINVAL;
2564 }
2565 #ifdef CONFIG_PC300_MLPPP
2566 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2567 if (conf->proto != PC300_PROTO_MLPPP) {
2568 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2569 cpc_tty_init(d); /* init TTY driver */
2570 }
2571 } else {
2572 if (conf_aux.conf.proto == 0xffff) {
2573 if (conf->proto == PC300_PROTO_MLPPP){
2574 /* ifdown interface */
2575 cpc_close(dev);
2576 }
2577 } else {
2578 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2579 /* FIXME hdlc->proto.id = conf->proto; */
2580 }
2581 }
2582 #else
2583 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2584 /* FIXME hdlc->proto.id = conf->proto; */
2585 #endif
2586 return 0;
2587 case SIOCGPC300STATUS:
2588 cpc_sca_status(card, ch);
2589 return 0;
2590 case SIOCGPC300FALCSTATUS:
2591 cpc_falc_status(card, ch);
2592 return 0;
2593
2594 case SIOCGPC300UTILSTATS:
2595 {
2596 if (!arg) { /* clear statistics */
2597 memset(&dev->stats, 0, sizeof(dev->stats));
2598 if (card->hw.type == PC300_TE) {
2599 memset(&chan->falc, 0, sizeof(falc_t));
2600 }
2601 } else {
2602 pc300stats_t pc300stats;
2603
2604 memset(&pc300stats, 0, sizeof(pc300stats_t));
2605 pc300stats.hw_type = card->hw.type;
2606 pc300stats.line_on = card->chan[ch].d.line_on;
2607 pc300stats.line_off = card->chan[ch].d.line_off;
2608 memcpy(&pc300stats.gen_stats, &dev->stats,
2609 sizeof(dev->stats));
2610 if (card->hw.type == PC300_TE)
2611 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2612 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2613 return -EFAULT;
2614 }
2615 return 0;
2616 }
2617
2618 case SIOCGPC300UTILSTATUS:
2619 {
2620 struct pc300status pc300status;
2621
2622 pc300status.hw_type = card->hw.type;
2623 if (card->hw.type == PC300_TE) {
2624 pc300status.te_status.sync = chan->falc.sync;
2625 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2626 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2627 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2628 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2629 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2630 pc300status.te_status.prbs = chan->falc.prbs;
2631 } else {
2632 pc300status.gen_status.dcd =
2633 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2634 pc300status.gen_status.cts =
2635 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2636 pc300status.gen_status.rts =
2637 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2638 pc300status.gen_status.dtr =
2639 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2640 /* There is no DSR in HD64572 */
2641 }
2642 if (!arg
2643 || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2644 return -EINVAL;
2645 return 0;
2646 }
2647
2648 case SIOCSPC300TRACE:
2649 /* Sets/resets a trace_flag for the respective device */
2650 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2651 return -EINVAL;
2652 return 0;
2653
2654 case SIOCSPC300LOOPBACK:
2655 {
2656 struct pc300loopback pc300loop;
2657
2658 /* TE boards only */
2659 if (card->hw.type != PC300_TE)
2660 return -EINVAL;
2661
2662 if (!arg ||
2663 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2664 return -EINVAL;
2665 switch (pc300loop.loop_type) {
2666 case PC300LOCLOOP: /* Turn the local loop on/off */
2667 falc_local_loop(card, ch, pc300loop.loop_on);
2668 return 0;
2669
2670 case PC300REMLOOP: /* Turn the remote loop on/off */
2671 falc_remote_loop(card, ch, pc300loop.loop_on);
2672 return 0;
2673
2674 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2675 falc_payload_loop(card, ch, pc300loop.loop_on);
2676 return 0;
2677
2678 case PC300GENLOOPUP: /* Generate loop UP */
2679 if (pc300loop.loop_on) {
2680 falc_generate_loop_up_code (card, ch);
2681 } else {
2682 turn_off_xlu(card, ch);
2683 }
2684 return 0;
2685
2686 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2687 if (pc300loop.loop_on) {
2688 falc_generate_loop_down_code (card, ch);
2689 } else {
2690 turn_off_xld(card, ch);
2691 }
2692 return 0;
2693
2694 default:
2695 return -EINVAL;
2696 }
2697 }
2698
2699 case SIOCSPC300PATTERNTEST:
2700 /* Turn the pattern test on/off and show the errors counter */
2701 {
2702 struct pc300patterntst pc300patrntst;
2703
2704 /* TE boards only */
2705 if (card->hw.type != PC300_TE)
2706 return -EINVAL;
2707
2708 if (card->hw.cpld_id < 0x02) {
2709 /* CPLD_ID < 0x02 doesn't support pattern test */
2710 return -EINVAL;
2711 }
2712
2713 if (!arg ||
2714 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2715 return -EINVAL;
2716 if (pc300patrntst.patrntst_on == 2) {
2717 if (chan->falc.prbs == 0) {
2718 falc_pattern_test(card, ch, 1);
2719 }
2720 pc300patrntst.num_errors =
2721 falc_pattern_test_error(card, ch);
2722 if (copy_to_user(arg, &pc300patrntst,
2723 sizeof(pc300patterntst_t)))
2724 return -EINVAL;
2725 } else {
2726 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2727 }
2728 return 0;
2729 }
2730
2731 case SIOCWANDEV:
2732 switch (ifr->ifr_settings.type) {
2733 case IF_GET_IFACE:
2734 {
2735 const size_t size = sizeof(sync_serial_settings);
2736 ifr->ifr_settings.type = conf->media;
2737 if (ifr->ifr_settings.size < size) {
2738 /* data size wanted */
2739 ifr->ifr_settings.size = size;
2740 return -ENOBUFS;
2741 }
2742
2743 if (copy_to_user(settings->ifs_ifsu.sync,
2744 &conf->phys_settings, size)) {
2745 return -EFAULT;
2746 }
2747 return 0;
2748 }
2749
2750 case IF_IFACE_V35:
2751 case IF_IFACE_V24:
2752 case IF_IFACE_X21:
2753 {
2754 const size_t size = sizeof(sync_serial_settings);
2755
2756 if (!capable(CAP_NET_ADMIN)) {
2757 return -EPERM;
2758 }
2759 /* incorrect data len? */
2760 if (ifr->ifr_settings.size != size) {
2761 return -ENOBUFS;
2762 }
2763
2764 if (copy_from_user(&conf->phys_settings,
2765 settings->ifs_ifsu.sync, size)) {
2766 return -EFAULT;
2767 }
2768
2769 if (conf->phys_settings.loopback) {
2770 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2771 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2772 MD2_LOOP_MIR);
2773 }
2774 conf->media = ifr->ifr_settings.type;
2775 return 0;
2776 }
2777
2778 case IF_IFACE_T1:
2779 case IF_IFACE_E1:
2780 {
2781 const size_t te_size = sizeof(te1_settings);
2782 const size_t size = sizeof(sync_serial_settings);
2783
2784 if (!capable(CAP_NET_ADMIN)) {
2785 return -EPERM;
2786 }
2787
2788 /* incorrect data len? */
2789 if (ifr->ifr_settings.size != te_size) {
2790 return -ENOBUFS;
2791 }
2792
2793 if (copy_from_user(&conf->phys_settings,
2794 settings->ifs_ifsu.te1, size)) {
2795 return -EFAULT;
2796 }/* Ignoring HDLC slot_map for a while */
2797
2798 if (conf->phys_settings.loopback) {
2799 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2800 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2801 MD2_LOOP_MIR);
2802 }
2803 conf->media = ifr->ifr_settings.type;
2804 return 0;
2805 }
2806 default:
2807 return hdlc_ioctl(dev, ifr, cmd);
2808 }
2809
2810 default:
2811 return hdlc_ioctl(dev, ifr, cmd);
2812 }
2813 }
2814
2815 static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
2816 {
2817 int br, tc;
2818 int br_pwr, error;
2819
2820 *br_io = 0;
2821
2822 if (rate == 0)
2823 return (0);
2824
2825 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2826 if ((tc = clock / br_pwr / rate) <= 0xff) {
2827 *br_io = br;
2828 break;
2829 }
2830 }
2831
2832 if (tc <= 0xff) {
2833 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2834 /* Errors bigger than +/- 1% won't be tolerated */
2835 if (error < -10 || error > 10)
2836 return (-1);
2837 else
2838 return (tc);
2839 } else {
2840 return (-1);
2841 }
2842 }
2843
2844 static int ch_config(pc300dev_t * d)
2845 {
2846 pc300ch_t *chan = (pc300ch_t *) d->chan;
2847 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2848 pc300_t *card = (pc300_t *) chan->card;
2849 void __iomem *scabase = card->hw.scabase;
2850 void __iomem *plxbase = card->hw.plxbase;
2851 int ch = chan->channel;
2852 u32 clkrate = chan->conf.phys_settings.clock_rate;
2853 u32 clktype = chan->conf.phys_settings.clock_type;
2854 u16 encoding = chan->conf.proto_settings.encoding;
2855 u16 parity = chan->conf.proto_settings.parity;
2856 u8 md0, md2;
2857
2858 /* Reset the channel */
2859 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2860
2861 /* Configure the SCA registers */
2862 switch (parity) {
2863 case PARITY_NONE:
2864 md0 = MD0_BIT_SYNC;
2865 break;
2866 case PARITY_CRC16_PR0:
2867 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2868 break;
2869 case PARITY_CRC16_PR1:
2870 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2871 break;
2872 case PARITY_CRC32_PR1_CCITT:
2873 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2874 break;
2875 case PARITY_CRC16_PR1_CCITT:
2876 default:
2877 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2878 break;
2879 }
2880 switch (encoding) {
2881 case ENCODING_NRZI:
2882 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2883 break;
2884 case ENCODING_FM_MARK: /* FM1 */
2885 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2886 break;
2887 case ENCODING_FM_SPACE: /* FM0 */
2888 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2889 break;
2890 case ENCODING_MANCHESTER: /* It's not working... */
2891 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2892 break;
2893 case ENCODING_NRZ:
2894 default:
2895 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2896 break;
2897 }
2898 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2899 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2900 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2901 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2902 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2903
2904 /* Configure HW media */
2905 switch (card->hw.type) {
2906 case PC300_RSV:
2907 if (conf->media == IF_IFACE_V35) {
2908 cpc_writel((plxbase + card->hw.gpioc_reg),
2909 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2910 } else {
2911 cpc_writel((plxbase + card->hw.gpioc_reg),
2912 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2913 }
2914 break;
2915
2916 case PC300_X21:
2917 break;
2918
2919 case PC300_TE:
2920 te_config(card, ch);
2921 break;
2922 }
2923
2924 switch (card->hw.type) {
2925 case PC300_RSV:
2926 case PC300_X21:
2927 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2928 int tmc, br;
2929
2930 /* Calculate the clkrate parameters */
2931 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2932 if (tmc < 0)
2933 return -EIO;
2934 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2935 cpc_writeb(scabase + M_REG(TXS, ch),
2936 (TXS_DTRXC | TXS_IBRG | br));
2937 if (clktype == CLOCK_INT) {
2938 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2939 cpc_writeb(scabase + M_REG(RXS, ch),
2940 (RXS_IBRG | br));
2941 } else {
2942 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2943 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2944 }
2945 if (card->hw.type == PC300_X21) {
2946 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2947 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2948 } else {
2949 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2950 }
2951 } else {
2952 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2953 if (clktype == CLOCK_EXT) {
2954 cpc_writeb(scabase + M_REG(TXS, ch),
2955 TXS_DTRXC);
2956 } else {
2957 cpc_writeb(scabase + M_REG(TXS, ch),
2958 TXS_DTRXC|TXS_RCLK);
2959 }
2960 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2961 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2962 if (card->hw.type == PC300_X21) {
2963 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2964 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2965 } else {
2966 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2967 }
2968 }
2969 break;
2970
2971 case PC300_TE:
2972 /* SCA always receives clock from the FALC chip */
2973 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2974 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2975 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2976 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2977 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2978 break;
2979 }
2980
2981 /* Enable Interrupts */
2982 cpc_writel(scabase + IER0,
2983 cpc_readl(scabase + IER0) |
2984 IR0_M(IR0_RXINTA, ch) |
2985 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2986 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2987 cpc_writeb(scabase + M_REG(IE0, ch),
2988 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2989 cpc_writeb(scabase + M_REG(IE1, ch),
2990 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2991
2992 return 0;
2993 }
2994
2995 static int rx_config(pc300dev_t * d)
2996 {
2997 pc300ch_t *chan = (pc300ch_t *) d->chan;
2998 pc300_t *card = (pc300_t *) chan->card;
2999 void __iomem *scabase = card->hw.scabase;
3000 int ch = chan->channel;
3001
3002 cpc_writeb(scabase + DSR_RX(ch), 0);
3003
3004 /* General RX settings */
3005 cpc_writeb(scabase + M_REG(RRC, ch), 0);
3006 cpc_writeb(scabase + M_REG(RNR, ch), 16);
3007
3008 /* Enable reception */
3009 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3010 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3011
3012 /* Initialize DMA stuff */
3013 chan->rx_first_bd = 0;
3014 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3015 rx_dma_buf_init(card, ch);
3016 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3017 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3018 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3019
3020 /* Start DMA */
3021 rx_dma_start(card, ch);
3022
3023 return 0;
3024 }
3025
3026 static int tx_config(pc300dev_t * d)
3027 {
3028 pc300ch_t *chan = (pc300ch_t *) d->chan;
3029 pc300_t *card = (pc300_t *) chan->card;
3030 void __iomem *scabase = card->hw.scabase;
3031 int ch = chan->channel;
3032
3033 cpc_writeb(scabase + DSR_TX(ch), 0);
3034
3035 /* General TX settings */
3036 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3037 cpc_writeb(scabase + M_REG(TFS, ch), 32);
3038 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3039 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3040 cpc_writeb(scabase + M_REG(TCR, ch), 8);
3041
3042 /* Enable transmission */
3043 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3044
3045 /* Initialize DMA stuff */
3046 chan->tx_first_bd = 0;
3047 chan->tx_next_bd = 0;
3048 tx_dma_buf_init(card, ch);
3049 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3050 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3051 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3052 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3053 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3054
3055 return 0;
3056 }
3057
3058 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3059 unsigned short parity)
3060 {
3061 pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
3062 pc300ch_t *chan = (pc300ch_t *)d->chan;
3063 pc300_t *card = (pc300_t *)chan->card;
3064 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3065
3066 if (card->hw.type == PC300_TE) {
3067 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3068 return -EINVAL;
3069 }
3070 } else {
3071 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3072 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3073 /* Driver doesn't support ENCODING_MANCHESTER yet */
3074 return -EINVAL;
3075 }
3076 }
3077
3078 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3079 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3080 parity != PARITY_CRC16_PR1_CCITT) {
3081 return -EINVAL;
3082 }
3083
3084 conf->proto_settings.encoding = encoding;
3085 conf->proto_settings.parity = parity;
3086 return 0;
3087 }
3088
3089 static int cpc_opench(pc300dev_t * d)
3090 {
3091 pc300ch_t *chan = (pc300ch_t *) d->chan;
3092 pc300_t *card = (pc300_t *) chan->card;
3093 int ch = chan->channel, rc;
3094 void __iomem *scabase = card->hw.scabase;
3095
3096 rc = ch_config(d);
3097 if (rc)
3098 return rc;
3099
3100 rx_config(d);
3101
3102 tx_config(d);
3103
3104 /* Assert RTS and DTR */
3105 cpc_writeb(scabase + M_REG(CTL, ch),
3106 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3107
3108 return 0;
3109 }
3110
3111 static void cpc_closech(pc300dev_t * d)
3112 {
3113 pc300ch_t *chan = (pc300ch_t *) d->chan;
3114 pc300_t *card = (pc300_t *) chan->card;
3115 falc_t *pfalc = (falc_t *) & chan->falc;
3116 int ch = chan->channel;
3117
3118 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3119 rx_dma_stop(card, ch);
3120 tx_dma_stop(card, ch);
3121
3122 if (card->hw.type == PC300_TE) {
3123 memset(pfalc, 0, sizeof(falc_t));
3124 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3125 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3126 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3127 CPLD_REG2_FALC_LED2) << (2 * ch)));
3128 /* Reset the FALC chip */
3129 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3130 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3131 (CPLD_REG1_FALC_RESET << (2 * ch)));
3132 udelay(10000);
3133 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3134 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3135 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3136 }
3137 }
3138
3139 int cpc_open(struct net_device *dev)
3140 {
3141 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3142 struct ifreq ifr;
3143 int result;
3144
3145 #ifdef PC300_DEBUG_OTHER
3146 printk("pc300: cpc_open");
3147 #endif
3148
3149 result = hdlc_open(dev);
3150
3151 if (result)
3152 return result;
3153
3154 sprintf(ifr.ifr_name, "%s", dev->name);
3155 result = cpc_opench(d);
3156 if (result)
3157 goto err_out;
3158
3159 netif_start_queue(dev);
3160 return 0;
3161
3162 err_out:
3163 hdlc_close(dev);
3164 return result;
3165 }
3166
3167 static int cpc_close(struct net_device *dev)
3168 {
3169 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3170 pc300ch_t *chan = (pc300ch_t *) d->chan;
3171 pc300_t *card = (pc300_t *) chan->card;
3172 unsigned long flags;
3173
3174 #ifdef PC300_DEBUG_OTHER
3175 printk("pc300: cpc_close");
3176 #endif
3177
3178 netif_stop_queue(dev);
3179
3180 CPC_LOCK(card, flags);
3181 cpc_closech(d);
3182 CPC_UNLOCK(card, flags);
3183
3184 hdlc_close(dev);
3185
3186 #ifdef CONFIG_PC300_MLPPP
3187 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3188 cpc_tty_unregister_service(d);
3189 chan->conf.proto = 0xffff;
3190 }
3191 #endif
3192
3193 return 0;
3194 }
3195
3196 static u32 detect_ram(pc300_t * card)
3197 {
3198 u32 i;
3199 u8 data;
3200 void __iomem *rambase = card->hw.rambase;
3201
3202 card->hw.ramsize = PC300_RAMSIZE;
3203 /* Let's find out how much RAM is present on this board */
3204 for (i = 0; i < card->hw.ramsize; i++) {
3205 data = (u8)(i & 0xff);
3206 cpc_writeb(rambase + i, data);
3207 if (cpc_readb(rambase + i) != data) {
3208 break;
3209 }
3210 }
3211 return (i);
3212 }
3213
3214 static void plx_init(pc300_t * card)
3215 {
3216 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3217
3218 /* Reset PLX */
3219 cpc_writel(&plx_ctl->init_ctrl,
3220 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3221 udelay(10000L);
3222 cpc_writel(&plx_ctl->init_ctrl,
3223 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3224
3225 /* Reload Config. Registers from EEPROM */
3226 cpc_writel(&plx_ctl->init_ctrl,
3227 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3228 udelay(10000L);
3229 cpc_writel(&plx_ctl->init_ctrl,
3230 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3231
3232 }
3233
3234 static inline void show_version(void)
3235 {
3236 char *rcsvers, *rcsdate, *tmp;
3237
3238 rcsvers = strchr(rcsid, ' ');
3239 rcsvers++;
3240 tmp = strchr(rcsvers, ' ');
3241 *tmp++ = '\0';
3242 rcsdate = strchr(tmp, ' ');
3243 rcsdate++;
3244 tmp = strrchr(rcsdate, ' ');
3245 *tmp = '\0';
3246 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3247 rcsvers, rcsdate, __DATE__, __TIME__);
3248 } /* show_version */
3249
3250 static const struct net_device_ops cpc_netdev_ops = {
3251 .ndo_open = cpc_open,
3252 .ndo_stop = cpc_close,
3253 .ndo_tx_timeout = cpc_tx_timeout,
3254 .ndo_set_mac_address = NULL,
3255 .ndo_change_mtu = cpc_change_mtu,
3256 .ndo_do_ioctl = cpc_ioctl,
3257 .ndo_validate_addr = eth_validate_addr,
3258 };
3259
3260 static void cpc_init_card(pc300_t * card)
3261 {
3262 int i, devcount = 0;
3263 static int board_nbr = 1;
3264
3265 /* Enable interrupts on the PCI bridge */
3266 plx_init(card);
3267 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3268 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3269
3270 #ifdef USE_PCI_CLOCK
3271 /* Set board clock to PCI clock */
3272 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3273 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3274 card->hw.clock = PC300_PCI_CLOCK;
3275 #else
3276 /* Set board clock to internal oscillator clock */
3277 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3278 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3279 card->hw.clock = PC300_OSC_CLOCK;
3280 #endif
3281
3282 /* Detect actual on-board RAM size */
3283 card->hw.ramsize = detect_ram(card);
3284
3285 /* Set Global SCA-II registers */
3286 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3287 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3288 cpc_writeb(card->hw.scabase + WCRL, 0);
3289 cpc_writeb(card->hw.scabase + DMER, 0x80);
3290
3291 if (card->hw.type == PC300_TE) {
3292 u8 reg1;
3293
3294 /* Check CPLD version */
3295 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3296 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3297 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3298 /* New CPLD */
3299 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3300 card->hw.cpld_reg1 = CPLD_V2_REG1;
3301 card->hw.cpld_reg2 = CPLD_V2_REG2;
3302 } else {
3303 /* old CPLD */
3304 card->hw.cpld_id = 0;
3305 card->hw.cpld_reg1 = CPLD_REG1;
3306 card->hw.cpld_reg2 = CPLD_REG2;
3307 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3308 }
3309
3310 /* Enable the board's global clock */
3311 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3312 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3313 CPLD_REG1_GLOBAL_CLK);
3314
3315 }
3316
3317 for (i = 0; i < card->hw.nchan; i++) {
3318 pc300ch_t *chan = &card->chan[i];
3319 pc300dev_t *d = &chan->d;
3320 hdlc_device *hdlc;
3321 struct net_device *dev;
3322
3323 chan->card = card;
3324 chan->channel = i;
3325 chan->conf.phys_settings.clock_rate = 0;
3326 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3327 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3328 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3329 switch (card->hw.type) {
3330 case PC300_TE:
3331 chan->conf.media = IF_IFACE_T1;
3332 chan->conf.lcode = PC300_LC_B8ZS;
3333 chan->conf.fr_mode = PC300_FR_ESF;
3334 chan->conf.lbo = PC300_LBO_0_DB;
3335 chan->conf.rx_sens = PC300_RX_SENS_SH;
3336 chan->conf.tslot_bitmap = 0xffffffffUL;
3337 break;
3338
3339 case PC300_X21:
3340 chan->conf.media = IF_IFACE_X21;
3341 break;
3342
3343 case PC300_RSV:
3344 default:
3345 chan->conf.media = IF_IFACE_V35;
3346 break;
3347 }
3348 chan->conf.proto = IF_PROTO_PPP;
3349 chan->tx_first_bd = 0;
3350 chan->tx_next_bd = 0;
3351 chan->rx_first_bd = 0;
3352 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3353 chan->nfree_tx_bd = N_DMA_TX_BUF;
3354
3355 d->chan = chan;
3356 d->trace_on = 0;
3357 d->line_on = 0;
3358 d->line_off = 0;
3359
3360 dev = alloc_hdlcdev(d);
3361 if (dev == NULL)
3362 continue;
3363
3364 hdlc = dev_to_hdlc(dev);
3365 hdlc->xmit = cpc_queue_xmit;
3366 hdlc->attach = cpc_attach;
3367 d->dev = dev;
3368 dev->mem_start = card->hw.ramphys;
3369 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3370 dev->irq = card->hw.irq;
3371 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3372 dev->mtu = PC300_DEF_MTU;
3373
3374 dev->netdev_ops = &cpc_netdev_ops;
3375 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3376
3377 if (register_hdlc_device(dev) == 0) {
3378 printk("%s: Cyclades-PC300/", dev->name);
3379 switch (card->hw.type) {
3380 case PC300_TE:
3381 if (card->hw.bus == PC300_PMC) {
3382 printk("TE-M");
3383 } else {
3384 printk("TE ");
3385 }
3386 break;
3387
3388 case PC300_X21:
3389 printk("X21 ");
3390 break;
3391
3392 case PC300_RSV:
3393 default:
3394 printk("RSV ");
3395 break;
3396 }
3397 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3398 board_nbr, card->hw.ramsize / 1024,
3399 card->hw.ramphys, card->hw.irq, i + 1);
3400 devcount++;
3401 } else {
3402 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3403 i + 1, card->hw.ramphys);
3404 free_netdev(dev);
3405 continue;
3406 }
3407 }
3408 spin_lock_init(&card->card_lock);
3409
3410 board_nbr++;
3411 }
3412
3413 static int __devinit
3414 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3415 {
3416 static int first_time = 1;
3417 int err, eeprom_outdated = 0;
3418 u16 device_id;
3419 pc300_t *card;
3420
3421 if (first_time) {
3422 first_time = 0;
3423 show_version();
3424 #ifdef CONFIG_PC300_MLPPP
3425 cpc_tty_reset_var();
3426 #endif
3427 }
3428
3429 if ((err = pci_enable_device(pdev)) < 0)
3430 return err;
3431
3432 card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3433 if (card == NULL) {
3434 printk("PC300 found at RAM 0x%016llx, "
3435 "but could not allocate card structure.\n",
3436 (unsigned long long)pci_resource_start(pdev, 3));
3437 err = -ENOMEM;
3438 goto err_disable_dev;
3439 }
3440
3441 err = -ENODEV;
3442
3443 /* read PCI configuration area */
3444 device_id = ent->device;
3445 card->hw.irq = pdev->irq;
3446 card->hw.iophys = pci_resource_start(pdev, 1);
3447 card->hw.iosize = pci_resource_len(pdev, 1);
3448 card->hw.scaphys = pci_resource_start(pdev, 2);
3449 card->hw.scasize = pci_resource_len(pdev, 2);
3450 card->hw.ramphys = pci_resource_start(pdev, 3);
3451 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3452 card->hw.falcphys = pci_resource_start(pdev, 4);
3453 card->hw.falcsize = pci_resource_len(pdev, 4);
3454 card->hw.plxphys = pci_resource_start(pdev, 5);
3455 card->hw.plxsize = pci_resource_len(pdev, 5);
3456
3457 switch (device_id) {
3458 case PCI_DEVICE_ID_PC300_RX_1:
3459 case PCI_DEVICE_ID_PC300_TE_1:
3460 case PCI_DEVICE_ID_PC300_TE_M_1:
3461 card->hw.nchan = 1;
3462 break;
3463
3464 case PCI_DEVICE_ID_PC300_RX_2:
3465 case PCI_DEVICE_ID_PC300_TE_2:
3466 case PCI_DEVICE_ID_PC300_TE_M_2:
3467 default:
3468 card->hw.nchan = PC300_MAXCHAN;
3469 break;
3470 }
3471 #ifdef PC300_DEBUG_PCI
3472 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3473 printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3474 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3475 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3476 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3477 card->hw.falcphys);
3478 #endif
3479 /* Although we don't use this I/O region, we should
3480 * request it from the kernel anyway, to avoid problems
3481 * with other drivers accessing it. */
3482 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3483 /* In case we can't allocate it, warn user */
3484 printk("WARNING: couldn't allocate I/O region for PC300 board "
3485 "at 0x%08x!\n", card->hw.ramphys);
3486 }
3487
3488 if (card->hw.plxphys) {
3489 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3490 } else {
3491 eeprom_outdated = 1;
3492 card->hw.plxphys = pci_resource_start(pdev, 0);
3493 card->hw.plxsize = pci_resource_len(pdev, 0);
3494 }
3495
3496 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3497 "PLX Registers")) {
3498 printk("PC300 found at RAM 0x%08x, "
3499 "but could not allocate PLX mem region.\n",
3500 card->hw.ramphys);
3501 goto err_release_io;
3502 }
3503 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3504 "On-board RAM")) {
3505 printk("PC300 found at RAM 0x%08x, "
3506 "but could not allocate RAM mem region.\n",
3507 card->hw.ramphys);
3508 goto err_release_plx;
3509 }
3510 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3511 "SCA-II Registers")) {
3512 printk("PC300 found at RAM 0x%08x, "
3513 "but could not allocate SCA mem region.\n",
3514 card->hw.ramphys);
3515 goto err_release_ram;
3516 }
3517
3518 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3519 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3520 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3521 switch (device_id) {
3522 case PCI_DEVICE_ID_PC300_TE_1:
3523 case PCI_DEVICE_ID_PC300_TE_2:
3524 case PCI_DEVICE_ID_PC300_TE_M_1:
3525 case PCI_DEVICE_ID_PC300_TE_M_2:
3526 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3527 "FALC Registers");
3528 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3529 break;
3530
3531 case PCI_DEVICE_ID_PC300_RX_1:
3532 case PCI_DEVICE_ID_PC300_RX_2:
3533 default:
3534 card->hw.falcbase = NULL;
3535 break;
3536 }
3537
3538 #ifdef PC300_DEBUG_PCI
3539 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3540 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3541 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3542 card->hw.falcbase);
3543 #endif
3544
3545 /* Set PCI drv pointer to the card structure */
3546 pci_set_drvdata(pdev, card);
3547
3548 /* Set board type */
3549 switch (device_id) {
3550 case PCI_DEVICE_ID_PC300_TE_1:
3551 case PCI_DEVICE_ID_PC300_TE_2:
3552 case PCI_DEVICE_ID_PC300_TE_M_1:
3553 case PCI_DEVICE_ID_PC300_TE_M_2:
3554 card->hw.type = PC300_TE;
3555
3556 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3557 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3558 card->hw.bus = PC300_PMC;
3559 /* Set PLX register offsets */
3560 card->hw.gpioc_reg = 0x54;
3561 card->hw.intctl_reg = 0x4c;
3562 } else {
3563 card->hw.bus = PC300_PCI;
3564 /* Set PLX register offsets */
3565 card->hw.gpioc_reg = 0x50;
3566 card->hw.intctl_reg = 0x4c;
3567 }
3568 break;
3569
3570 case PCI_DEVICE_ID_PC300_RX_1:
3571 case PCI_DEVICE_ID_PC300_RX_2:
3572 default:
3573 card->hw.bus = PC300_PCI;
3574 /* Set PLX register offsets */
3575 card->hw.gpioc_reg = 0x50;
3576 card->hw.intctl_reg = 0x4c;
3577
3578 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3579 card->hw.type = PC300_X21;
3580 } else {
3581 card->hw.type = PC300_RSV;
3582 }
3583 break;
3584 }
3585
3586 /* Allocate IRQ */
3587 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3588 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3589 card->hw.ramphys, card->hw.irq);
3590 goto err_io_unmap;
3591 }
3592
3593 cpc_init_card(card);
3594
3595 if (eeprom_outdated)
3596 printk("WARNING: PC300 with outdated EEPROM.\n");
3597 return 0;
3598
3599 err_io_unmap:
3600 iounmap(card->hw.plxbase);
3601 iounmap(card->hw.scabase);
3602 iounmap(card->hw.rambase);
3603 if (card->hw.type == PC300_TE) {
3604 iounmap(card->hw.falcbase);
3605 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3606 }
3607 release_mem_region(card->hw.scaphys, card->hw.scasize);
3608 err_release_ram:
3609 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3610 err_release_plx:
3611 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3612 err_release_io:
3613 release_region(card->hw.iophys, card->hw.iosize);
3614 kfree(card);
3615 err_disable_dev:
3616 pci_disable_device(pdev);
3617 return err;
3618 }
3619
3620 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3621 {
3622 pc300_t *card = pci_get_drvdata(pdev);
3623
3624 if (card->hw.rambase) {
3625 int i;
3626
3627 /* Disable interrupts on the PCI bridge */
3628 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3629 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3630
3631 for (i = 0; i < card->hw.nchan; i++) {
3632 unregister_hdlc_device(card->chan[i].d.dev);
3633 }
3634 iounmap(card->hw.plxbase);
3635 iounmap(card->hw.scabase);
3636 iounmap(card->hw.rambase);
3637 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3638 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3639 release_mem_region(card->hw.scaphys, card->hw.scasize);
3640 release_region(card->hw.iophys, card->hw.iosize);
3641 if (card->hw.type == PC300_TE) {
3642 iounmap(card->hw.falcbase);
3643 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3644 }
3645 for (i = 0; i < card->hw.nchan; i++)
3646 if (card->chan[i].d.dev)
3647 free_netdev(card->chan[i].d.dev);
3648 if (card->hw.irq)
3649 free_irq(card->hw.irq, card);
3650 kfree(card);
3651 pci_disable_device(pdev);
3652 }
3653 }
3654
3655 static struct pci_driver cpc_driver = {
3656 .name = "pc300",
3657 .id_table = cpc_pci_dev_id,
3658 .probe = cpc_init_one,
3659 .remove = __devexit_p(cpc_remove_one),
3660 };
3661
3662 static int __init cpc_init(void)
3663 {
3664 return pci_register_driver(&cpc_driver);
3665 }
3666
3667 static void __exit cpc_cleanup_module(void)
3668 {
3669 pci_unregister_driver(&cpc_driver);
3670 }
3671
3672 module_init(cpc_init);
3673 module_exit(cpc_cleanup_module);
3674
3675 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3676 MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3677 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3678 MODULE_LICENSE("GPL");
3679
Verdex Pro support