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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / net / wireless / wl12xx / wl1271_reg.h
blobf8ed4a4fc691a47a6abe43142d3b670fa966205d
1 /*
2 * This file is part of wl12xx
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #ifndef __REG_H__
26 #define __REG_H__
27
28 #include <linux/bitops.h>
29
30 #define REGISTERS_BASE 0x00300000
31 #define DRPW_BASE 0x00310000
32
33 #define REGISTERS_DOWN_SIZE 0x00008800
34 #define REGISTERS_WORK_SIZE 0x0000b000
35
36 #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
37 #define STATUS_MEM_ADDRESS 0x40400
38
39 /* ELP register commands */
40 #define ELPCTRL_WAKE_UP 0x1
41 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
42 #define ELPCTRL_SLEEP 0x0
43 /* ELP WLAN_READY bit */
44 #define ELPCTRL_WLAN_READY 0x2
45
46 /*===============================================
47 Host Software Reset - 32bit RW
48 ------------------------------------------
49 [31:1] Reserved
50 0 SOFT_RESET Soft Reset - When this bit is set,
51 it holds the Wlan hardware in a soft reset state.
52 This reset disables all MAC and baseband processor
53 clocks except the CardBus/PCI interface clock.
54 It also initializes all MAC state machines except
55 the host interface. It does not reload the
56 contents of the EEPROM. When this bit is cleared
57 (not self-clearing), the Wlan hardware
58 exits the software reset state.
59 ===============================================*/
60 #define ACX_REG_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
61
62 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
63 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
64 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
65 /*
66 * Interrupt registers.
67 * 64 bit interrupt sources registers ws ced.
68 * sme interupts were removed and new ones were added.
69 * Order was changed.
70 */
71 #define FIQ_MASK (REGISTERS_BASE + 0x0400)
72 #define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
73 #define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
74 #define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
75 #define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
76 #define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
77 #define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
78 #define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
79 #define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
80 #define IRQ_MASK (REGISTERS_BASE + 0x0418)
81 #define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
82 #define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
83 #define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
84 #define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
85 #define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
86 #define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
87 #define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
88 #define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
89 #define ECPU_MASK (REGISTERS_BASE + 0x0448)
90 #define FIQ_STS_L (REGISTERS_BASE + 0x044C)
91 #define FIQ_STS_H (REGISTERS_BASE + 0x0450)
92 #define IRQ_STS_L (REGISTERS_BASE + 0x0454)
93 #define IRQ_STS_H (REGISTERS_BASE + 0x0458)
94 #define INT_STS_ND (REGISTERS_BASE + 0x0464)
95 #define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
96 #define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
97 #define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
98 #define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
99 #define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
100 #define INT_ACK (REGISTERS_BASE + 0x046C)
101 #define INT_ACK_L (REGISTERS_BASE + 0x046C)
102 #define INT_ACK_H (REGISTERS_BASE + 0x0470)
103 #define INT_TRIG (REGISTERS_BASE + 0x0474)
104 #define INT_TRIG_L (REGISTERS_BASE + 0x0474)
105 #define INT_TRIG_H (REGISTERS_BASE + 0x0478)
106 #define HOST_STS_L (REGISTERS_BASE + 0x045C)
107 #define HOST_STS_H (REGISTERS_BASE + 0x0460)
108 #define HOST_MASK (REGISTERS_BASE + 0x0430)
109 #define HOST_MASK_L (REGISTERS_BASE + 0x0430)
110 #define HOST_MASK_H (REGISTERS_BASE + 0x0434)
111 #define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
112 #define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
113 #define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
114 #define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
115 #define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
116 #define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
117
118 #define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
119 #define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
120
121 /* Host Interrupts*/
122 #define HINT_MASK (REGISTERS_BASE + 0x0494)
123 #define HINT_MASK_SET (REGISTERS_BASE + 0x0498)
124 #define HINT_MASK_CLR (REGISTERS_BASE + 0x049C)
125 #define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04A0)
126 /*1150 spec calls this HINT_STS_RAW*/
127 #define HINT_STS_ND (REGISTERS_BASE + 0x04B0)
128 #define HINT_STS_CLR (REGISTERS_BASE + 0x04A4)
129 #define HINT_ACK (REGISTERS_BASE + 0x04A8)
130 #define HINT_TRIG (REGISTERS_BASE + 0x04AC)
131
132 /*=============================================
133 Host Interrupt Mask Register - 32bit (RW)
134 ------------------------------------------
135 Setting a bit in this register masks the
136 corresponding interrupt to the host.
137 0 - RX0 - Rx first dubble buffer Data Interrupt
138 1 - TXD - Tx Data Interrupt
139 2 - TXXFR - Tx Transfer Interrupt
140 3 - RX1 - Rx second dubble buffer Data Interrupt
141 4 - RXXFR - Rx Transfer Interrupt
142 5 - EVENT_A - Event Mailbox interrupt
143 6 - EVENT_B - Event Mailbox interrupt
144 7 - WNONHST - Wake On Host Interrupt
145 8 - TRACE_A - Debug Trace interrupt
146 9 - TRACE_B - Debug Trace interrupt
147 10 - CDCMP - Command Complete Interrupt
148 11 -
149 12 -
150 13 -
151 14 - ICOMP - Initialization Complete Interrupt
152 16 - SG SE - Soft Gemini - Sense enable interrupt
153 17 - SG SD - Soft Gemini - Sense disable interrupt
154 18 - -
155 19 - -
156 20 - -
157 21- -
158 Default: 0x0001
159 *==============================================*/
160 #define ACX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
161
162 /*=============================================
163 Host Interrupt Mask Set 16bit, (Write only)
164 ------------------------------------------
165 Setting a bit in this register sets
166 the corresponding bin in ACX_HINT_MASK register
167 without effecting the mask
168 state of other bits (0 = no effect).
169 ==============================================*/
170 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
171
172 /*=============================================
173 Host Interrupt Mask Clear 16bit,(Write only)
174 ------------------------------------------
175 Setting a bit in this register clears
176 the corresponding bin in ACX_HINT_MASK register
177 without effecting the mask
178 state of other bits (0 = no effect).
179 =============================================*/
180 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
181
182 /*=============================================
183 Host Interrupt Status Nondestructive Read
184 16bit,(Read only)
185 ------------------------------------------
186 The host can read this register to determine
187 which interrupts are active.
188 Reading this register doesn't
189 effect its content.
190 =============================================*/
191 #define ACX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
192
193 /*=============================================
194 Host Interrupt Status Clear on Read Register
195 16bit,(Read only)
196 ------------------------------------------
197 The host can read this register to determine
198 which interrupts are active.
199 Reading this register clears it,
200 thus making all interrupts inactive.
201 ==============================================*/
202 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
203
204 /*=============================================
205 Host Interrupt Acknowledge Register
206 16bit,(Write only)
207 ------------------------------------------
208 The host can set individual bits in this
209 register to clear (acknowledge) the corresp.
210 interrupt status bits in the HINT_STS_CLR and
211 HINT_STS_ND registers, thus making the
212 assotiated interrupt inactive. (0-no effect)
213 ==============================================*/
214 #define ACX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
215
216 #define RX_DRIVER_DUMMY_WRITE_ADDRESS (REGISTERS_BASE + 0x0534)
217 #define RX_DRIVER_COUNTER_ADDRESS (REGISTERS_BASE + 0x0538)
218
219 /* Device Configuration registers*/
220 #define SOR_CFG (REGISTERS_BASE + 0x0800)
221
222 /* Embedded ARM CPU Control */
223
224 /*===============================================
225 Halt eCPU - 32bit RW
226 ------------------------------------------
227 0 HALT_ECPU Halt Embedded CPU - This bit is the
228 compliment of bit 1 (MDATA2) in the SOR_CFG register.
229 During a hardware reset, this bit holds
230 the inverse of MDATA2.
231 When downloading firmware from the host,
232 set this bit (pull down MDATA2).
233 The host clears this bit after downloading the firmware into
234 zero-wait-state SSRAM.
235 When loading firmware from Flash, clear this bit (pull up MDATA2)
236 so that the eCPU can run the bootloader code in Flash
237 HALT_ECPU eCPU State
238 --------------------
239 1 halt eCPU
240 0 enable eCPU
241 ===============================================*/
242 #define ACX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
243
244 #define HI_CFG (REGISTERS_BASE + 0x0808)
245
246 /*===============================================
247 EEPROM Burst Read Start - 32bit RW
248 ------------------------------------------
249 [31:1] Reserved
250 0 ACX_EE_START - EEPROM Burst Read Start 0
251 Setting this bit starts a burst read from
252 the external EEPROM.
253 If this bit is set (after reset) before an EEPROM read/write,
254 the burst read starts at EEPROM address 0.
255 Otherwise, it starts at the address
256 following the address of the previous access.
257 TheWlan hardware hardware clears this bit automatically.
258
259 Default: 0x00000000
260 *================================================*/
261 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
262
263 #define OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
264 #define OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
265 #define OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
266 #define OCP_CMD (REGISTERS_BASE + 0x09C0)
267
268 #define WL1271_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
269
270 #define CHIP_ID_B (REGISTERS_BASE + 0x5674)
271
272 #define CHIP_ID_1271_PG10 (0x4030101)
273 #define CHIP_ID_1271_PG20 (0x4030111)
274
275 #define ENABLE (REGISTERS_BASE + 0x5450)
276
277 /* Power Management registers */
278 #define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
279 #define ELP_CMD (REGISTERS_BASE + 0x5808)
280 #define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
281 #define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
282 #define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
283
284 #define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
285
286 /* Scratch Pad registers*/
287 #define SCR_PAD0 (REGISTERS_BASE + 0x5608)
288 #define SCR_PAD1 (REGISTERS_BASE + 0x560C)
289 #define SCR_PAD2 (REGISTERS_BASE + 0x5610)
290 #define SCR_PAD3 (REGISTERS_BASE + 0x5614)
291 #define SCR_PAD4 (REGISTERS_BASE + 0x5618)
292 #define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
293 #define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
294 #define SCR_PAD5 (REGISTERS_BASE + 0x5624)
295 #define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
296 #define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
297 #define SCR_PAD6 (REGISTERS_BASE + 0x5630)
298 #define SCR_PAD7 (REGISTERS_BASE + 0x5634)
299 #define SCR_PAD8 (REGISTERS_BASE + 0x5638)
300 #define SCR_PAD9 (REGISTERS_BASE + 0x563C)
301
302 /* Spare registers*/
303 #define SPARE_A1 (REGISTERS_BASE + 0x0994)
304 #define SPARE_A2 (REGISTERS_BASE + 0x0998)
305 #define SPARE_A3 (REGISTERS_BASE + 0x099C)
306 #define SPARE_A4 (REGISTERS_BASE + 0x09A0)
307 #define SPARE_A5 (REGISTERS_BASE + 0x09A4)
308 #define SPARE_A6 (REGISTERS_BASE + 0x09A8)
309 #define SPARE_A7 (REGISTERS_BASE + 0x09AC)
310 #define SPARE_A8 (REGISTERS_BASE + 0x09B0)
311 #define SPARE_B1 (REGISTERS_BASE + 0x5420)
312 #define SPARE_B2 (REGISTERS_BASE + 0x5424)
313 #define SPARE_B3 (REGISTERS_BASE + 0x5428)
314 #define SPARE_B4 (REGISTERS_BASE + 0x542C)
315 #define SPARE_B5 (REGISTERS_BASE + 0x5430)
316 #define SPARE_B6 (REGISTERS_BASE + 0x5434)
317 #define SPARE_B7 (REGISTERS_BASE + 0x5438)
318 #define SPARE_B8 (REGISTERS_BASE + 0x543C)
319
320 #define PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
321 #define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
322 #define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
323 #define DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
324
325
326 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
327 #define ACX_REG_EEPROM_START_BIT BIT(1)
328
329 /* Command/Information Mailbox Pointers */
330
331 /*===============================================
332 Command Mailbox Pointer - 32bit RW
333 ------------------------------------------
334 This register holds the start address of
335 the command mailbox located in the Wlan hardware memory.
336 The host must read this pointer after a reset to
337 find the location of the command mailbox.
338 The Wlan hardware initializes the command mailbox
339 pointer with the default address of the command mailbox.
340 The command mailbox pointer is not valid until after
341 the host receives the Init Complete interrupt from
342 the Wlan hardware.
343 ===============================================*/
344 #define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
345
346 /*===============================================
347 Information Mailbox Pointer - 32bit RW
348 ------------------------------------------
349 This register holds the start address of
350 the information mailbox located in the Wlan hardware memory.
351 The host must read this pointer after a reset to find
352 the location of the information mailbox.
353 The Wlan hardware initializes the information mailbox pointer
354 with the default address of the information mailbox.
355 The information mailbox pointer is not valid
356 until after the host receives the Init Complete interrupt from
357 the Wlan hardware.
358 ===============================================*/
359 #define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
360
361
362 /* Misc */
363
364 #define REG_ENABLE_TX_RX (ENABLE)
365 /*
366 * Rx configuration (filter) information element
367 * ---------------------------------------------
368 */
369 #define REG_RX_CONFIG (RX_CFG)
370 #define REG_RX_FILTER (RX_FILTER_CFG)
371
372
373 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
374
375 /* promiscuous - receives all valid frames */
376 #define RX_CFG_PROMISCUOUS 0x0008
377
378 /* receives frames from any BSSID */
379 #define RX_CFG_BSSID 0x0020
380
381 /* receives frames destined to any MAC address */
382 #define RX_CFG_MAC 0x0010
383
384 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
385 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
386 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
387 #define RX_CFG_ENABLE_ANY_BSSID 0x0000
388
389 /* discards all broadcast frames */
390 #define RX_CFG_DISABLE_BCAST 0x0200
391
392 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
393 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
394 #define RX_CFG_COPY_RX_STATUS 0x2000
395 #define RX_CFG_TSF 0x10000
396
397 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
398 RX_CFG_ENABLE_ONLY_MY_BSSID)
399
400 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
401 | RX_CFG_ENABLE_ANY_BSSID)
402
403 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
404 RX_CFG_ENABLE_ANY_BSSID)
405
406 #define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
407 | RX_CFG_ENABLE_ONLY_MY_BSSID)
408
409 #define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \
410 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
411 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
412
413 #define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
414
415 #define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \
416 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
417
418 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \
419 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
420
421 #define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
422 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
423 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
424
425 #define RX_FILTER_OPTION_FILTER_ALL 0
426
427 #define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
428 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
429
430 #define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
431 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
432 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
433 | CFG_RX_PRSP_EN)
434
435
436 /*===============================================
437 Phy regs
438 ===============================================*/
439 #define ACX_PHY_ADDR_REG SBB_ADDR
440 #define ACX_PHY_DATA_REG SBB_DATA
441 #define ACX_PHY_CTRL_REG SBB_CTL
442 #define ACX_PHY_REG_WR_MASK 0x00000001ul
443 #define ACX_PHY_REG_RD_MASK 0x00000002ul
444
445
446 /*===============================================
447 EEPROM Read/Write Request 32bit RW
448 ------------------------------------------
449 1 EE_READ - EEPROM Read Request 1 - Setting this bit
450 loads a single byte of data into the EE_DATA
451 register from the EEPROM location specified in
452 the EE_ADDR register.
453 The Wlan hardware hardware clears this bit automatically.
454 EE_DATA is valid when this bit is cleared.
455
456 0 EE_WRITE - EEPROM Write Request - Setting this bit
457 writes a single byte of data from the EE_DATA register into the
458 EEPROM location specified in the EE_ADDR register.
459 The Wlan hardware hardware clears this bit automatically.
460 *===============================================*/
461 #define ACX_EE_CTL_REG EE_CTL
462 #define EE_WRITE 0x00000001ul
463 #define EE_READ 0x00000002ul
464
465 /*===============================================
466 EEPROM Address - 32bit RW
467 ------------------------------------------
468 This register specifies the address
469 within the EEPROM from/to which to read/write data.
470 ===============================================*/
471 #define ACX_EE_ADDR_REG EE_ADDR
472
473 /*===============================================
474 EEPROM Data - 32bit RW
475 ------------------------------------------
476 This register either holds the read 8 bits of
477 data from the EEPROM or the write data
478 to be written to the EEPROM.
479 ===============================================*/
480 #define ACX_EE_DATA_REG EE_DATA
481
482 /*===============================================
483 EEPROM Base Address - 32bit RW
484 ------------------------------------------
485 This register holds the upper nine bits
486 [23:15] of the 24-bit Wlan hardware memory
487 address for burst reads from EEPROM accesses.
488 The EEPROM provides the lower 15 bits of this address.
489 The MSB of the address from the EEPROM is ignored.
490 ===============================================*/
491 #define ACX_EE_CFG EE_CFG
492
493 /*===============================================
494 GPIO Output Values -32bit, RW
495 ------------------------------------------
496 [31:16] Reserved
497 [15: 0] Specify the output values (at the output driver inputs) for
498 GPIO[15:0], respectively.
499 ===============================================*/
500 #define ACX_GPIO_OUT_REG GPIO_OUT
501 #define ACX_MAX_GPIO_LINES 15
502
503 /*===============================================
504 Contention window -32bit, RW
505 ------------------------------------------
506 [31:26] Reserved
507 [25:16] Max (0x3ff)
508 [15:07] Reserved
509 [06:00] Current contention window value - default is 0x1F
510 ===============================================*/
511 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
512 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
513 #define ACX_CONT_WIND_MAX 0x03ff0000
514
515 /*
516 * Indirect slave register/memory registers
517 * ----------------------------------------
518 */
519 #define HW_SLAVE_REG_ADDR_REG 0x00000004
520 #define HW_SLAVE_REG_DATA_REG 0x00000008
521 #define HW_SLAVE_REG_CTRL_REG 0x0000000c
522
523 #define SLAVE_AUTO_INC 0x00010000
524 #define SLAVE_NO_AUTO_INC 0x00000000
525 #define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
526
527 #define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
528 #define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
529 #define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
530 #define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
531
532 #define HW_FUNC_EVENT_INT_EN 0x8000
533 #define HW_FUNC_EVENT_MASK_REG 0x00000034
534
535 #define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
536
537 /*===============================================
538 HI_CFG Interface Configuration Register Values
539 ------------------------------------------
540 ===============================================*/
541 #define HI_CFG_UART_ENABLE 0x00000004
542 #define HI_CFG_RST232_ENABLE 0x00000008
543 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
544 #define HI_CFG_HOST_INT_ENABLE 0x00000020
545 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
546 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
547 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
548 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
549 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
550
551 /*
552 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
553 * for platforms using active high interrupt level
554 */
555 #ifdef USE_ACTIVE_HIGH
556 #define HI_CFG_DEF_VAL \
557 (HI_CFG_UART_ENABLE | \
558 HI_CFG_RST232_ENABLE | \
559 HI_CFG_CLOCK_REQ_SELECT | \
560 HI_CFG_HOST_INT_ENABLE)
561 #else
562 #define HI_CFG_DEF_VAL \
563 (HI_CFG_UART_ENABLE | \
564 HI_CFG_RST232_ENABLE | \
565 HI_CFG_CLOCK_REQ_SELECT | \
566 HI_CFG_HOST_INT_ENABLE)
567
568 #endif
569
570 #define REF_FREQ_19_2 0
571 #define REF_FREQ_26_0 1
572 #define REF_FREQ_38_4 2
573 #define REF_FREQ_40_0 3
574 #define REF_FREQ_33_6 4
575 #define REF_FREQ_NUM 5
576
577 #define LUT_PARAM_INTEGER_DIVIDER 0
578 #define LUT_PARAM_FRACTIONAL_DIVIDER 1
579 #define LUT_PARAM_ATTN_BB 2
580 #define LUT_PARAM_ALPHA_BB 3
581 #define LUT_PARAM_STOP_TIME_BB 4
582 #define LUT_PARAM_BB_PLL_LOOP_FILTER 5
583 #define LUT_PARAM_NUM 6
584
585 #define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
586 #define USE_EEPROM 0
587 #define SOFT_RESET_MAX_TIME 1000000
588 #define SOFT_RESET_STALL_TIME 1000
589 #define NVS_DATA_BUNDARY_ALIGNMENT 4
590
591
592 /* Firmware image load chunk size */
593 #define CHUNK_SIZE 512
594
595 /* Firmware image header size */
596 #define FW_HDR_SIZE 8
597
598 #define ECPU_CONTROL_HALT 0x00000101
599
600
601 /******************************************************************************
602
603 CHANNELS, BAND & REG DOMAINS definitions
604
605 ******************************************************************************/
606
607
608 enum {
609 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */
610 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */
611 RADIO_BAND_JAPAN_4_9_GHZ = 2,
612 DEFAULT_BAND = RADIO_BAND_2_4GHZ,
613 INVALID_BAND = 0xFE,
614 MAX_RADIO_BANDS = 0xFF
615 };
616
617 enum {
618 NO_RATE = 0,
619 RATE_1MBPS = 0x0A,
620 RATE_2MBPS = 0x14,
621 RATE_5_5MBPS = 0x37,
622 RATE_6MBPS = 0x0B,
623 RATE_9MBPS = 0x0F,
624 RATE_11MBPS = 0x6E,
625 RATE_12MBPS = 0x0A,
626 RATE_18MBPS = 0x0E,
627 RATE_22MBPS = 0xDC,
628 RATE_24MBPS = 0x09,
629 RATE_36MBPS = 0x0D,
630 RATE_48MBPS = 0x08,
631 RATE_54MBPS = 0x0C
632 };
633
634 enum {
635 RATE_INDEX_1MBPS = 0,
636 RATE_INDEX_2MBPS = 1,
637 RATE_INDEX_5_5MBPS = 2,
638 RATE_INDEX_6MBPS = 3,
639 RATE_INDEX_9MBPS = 4,
640 RATE_INDEX_11MBPS = 5,
641 RATE_INDEX_12MBPS = 6,
642 RATE_INDEX_18MBPS = 7,
643 RATE_INDEX_22MBPS = 8,
644 RATE_INDEX_24MBPS = 9,
645 RATE_INDEX_36MBPS = 10,
646 RATE_INDEX_48MBPS = 11,
647 RATE_INDEX_54MBPS = 12,
648 RATE_INDEX_MAX = RATE_INDEX_54MBPS,
649 MAX_RATE_INDEX,
650 INVALID_RATE_INDEX = MAX_RATE_INDEX,
651 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF
652 };
653
654 enum {
655 RATE_MASK_1MBPS = 0x1,
656 RATE_MASK_2MBPS = 0x2,
657 RATE_MASK_5_5MBPS = 0x4,
658 RATE_MASK_11MBPS = 0x20,
659 };
660
661 #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
662 #define OFDM_RATE_BIT BIT(6)
663 #define PBCC_RATE_BIT BIT(7)
664
665 enum {
666 CCK_LONG = 0,
667 CCK_SHORT = SHORT_PREAMBLE_BIT,
668 PBCC_LONG = PBCC_RATE_BIT,
669 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
670 OFDM = OFDM_RATE_BIT
671 };
672
673 /******************************************************************************
674
675 Transmit-Descriptor RATE-SET field definitions...
676
677 Define a new "Rate-Set" for TX path that incorporates the
678 Rate & Modulation info into a single 16-bit field.
679
680 TxdRateSet_t:
681 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
682 Notes:
683 Must be LONG (0) for 1Mbps rate.
684 Does not apply (set to 0) for RevG-OFDM rates.
685 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
686 Notes:
687 Does not apply (set to 0) for rates 1 and 2 Mbps.
688 Does not apply (set to 0) for RevG-OFDM rates.
689 b13 - Unused (set to 0).
690 b12-b0 - Supported Rate indicator bits as defined below.
691
692 ******************************************************************************/
693
694
695 #define TNETW1251_CHIP_ID_PG1_0 0x07010101
696 #define TNETW1251_CHIP_ID_PG1_1 0x07020101
697 #define TNETW1251_CHIP_ID_PG1_2 0x07030101
698
699 /*************************************************************************
700
701 Interrupt Trigger Register (Host -> WiLink)
702
703 **************************************************************************/
704
705 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
706
707 /*
708 * Host Command Interrupt. Setting this bit masks
709 * the interrupt that the host issues to inform
710 * the FW that it has sent a command
711 * to the Wlan hardware Command Mailbox.
712 */
713 #define INTR_TRIG_CMD BIT(0)
714
715 /*
716 * Host Event Acknowlegde Interrupt. The host
717 * sets this bit to acknowledge that it received
718 * the unsolicited information from the event
719 * mailbox.
720 */
721 #define INTR_TRIG_EVENT_ACK BIT(1)
722
723 /*
724 * The host sets this bit to inform the Wlan
725 * FW that a TX packet is in the XFER
726 * Buffer #0.
727 */
728 #define INTR_TRIG_TX_PROC0 BIT(2)
729
730 /*
731 * The host sets this bit to inform the FW
732 * that it read a packet from RX XFER
733 * Buffer #0.
734 */
735 #define INTR_TRIG_RX_PROC0 BIT(3)
736
737 #define INTR_TRIG_DEBUG_ACK BIT(4)
738
739 #define INTR_TRIG_STATE_CHANGED BIT(5)
740
741
742 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
743
744 /*
745 * The host sets this bit to inform the FW
746 * that it read a packet from RX XFER
747 * Buffer #1.
748 */
749 #define INTR_TRIG_RX_PROC1 BIT(17)
750
751 /*
752 * The host sets this bit to inform the Wlan
753 * hardware that a TX packet is in the XFER
754 * Buffer #1.
755 */
756 #define INTR_TRIG_TX_PROC1 BIT(18)
757
758 #endif
Verdex Pro support