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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / staging / cx25821 / cx25821-video-upstream-ch2.c
blobc8905e0ac509563abfdfb851981e9632ec399db9
1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream-ch2.h"
25
26 #include <linux/fs.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <asm/uaccess.h>
35
36 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
37 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
38 MODULE_LICENSE("GPL");
39
40 static int _intr_msk =
41 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
42
43 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
44 __le32 * rp, unsigned int offset,
45 unsigned int bpl, u32 sync_line,
46 unsigned int lines,
47 int fifo_enable, int field_type)
48 {
49 unsigned int line, i;
50 int dist_betwn_starts = bpl * 2;
51
52 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
53
54 if (USE_RISC_NOOP_VIDEO) {
55 for (i = 0; i < NUM_NO_OPS; i++) {
56 *(rp++) = cpu_to_le32(RISC_NOOP);
57 }
58 }
59
60 /* scan lines */
61 for (line = 0; line < lines; line++) {
62 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
63 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
64 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
65
66 if ((lines <= NTSC_FIELD_HEIGHT)
67 || (line < (NTSC_FIELD_HEIGHT - 1))
68 || !(dev->_isNTSC_ch2)) {
69 offset += dist_betwn_starts;
70 }
71 }
72
73 return rp;
74 }
75
76 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
77 __le32 * rp,
78 dma_addr_t databuf_phys_addr,
79 unsigned int offset,
80 u32 sync_line, unsigned int bpl,
81 unsigned int lines,
82 int fifo_enable, int field_type)
83 {
84 unsigned int line, i;
85 struct sram_channel *sram_ch =
86 &dev->sram_channels[dev->_channel2_upstream_select];
87 int dist_betwn_starts = bpl * 2;
88
89 /* sync instruction */
90 if (sync_line != NO_SYNC_LINE) {
91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
92 }
93
94 if (USE_RISC_NOOP_VIDEO) {
95 for (i = 0; i < NUM_NO_OPS; i++) {
96 *(rp++) = cpu_to_le32(RISC_NOOP);
97 }
98 }
99
100 /* scan lines */
101 for (line = 0; line < lines; line++) {
102 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
103 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
104 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
105
106 if ((lines <= NTSC_FIELD_HEIGHT)
107 || (line < (NTSC_FIELD_HEIGHT - 1))
108 || !(dev->_isNTSC_ch2)) {
109 offset += dist_betwn_starts;
110 }
111
112 // check if we need to enable the FIFO after the first 4 lines
113 // For the upstream video channel, the risc engine will enable the FIFO.
114 if (fifo_enable && line == 3) {
115 *(rp++) = RISC_WRITECR;
116 *(rp++) = sram_ch->dma_ctl;
117 *(rp++) = FLD_VID_FIFO_EN;
118 *(rp++) = 0x00000001;
119 }
120 }
121
122 return rp;
123 }
124
125 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
126 struct pci_dev *pci,
127 unsigned int top_offset, unsigned int bpl,
128 unsigned int lines)
129 {
130 __le32 *rp;
131 int fifo_enable = 0;
132 int singlefield_lines = lines >> 1; //get line count for single field
133 int odd_num_lines = singlefield_lines;
134 int frame = 0;
135 int frame_size = 0;
136 int databuf_offset = 0;
137 int risc_program_size = 0;
138 int risc_flag = RISC_CNT_RESET;
139 unsigned int bottom_offset = bpl;
140 dma_addr_t risc_phys_jump_addr;
141
142 if (dev->_isNTSC_ch2) {
143 odd_num_lines = singlefield_lines + 1;
144 risc_program_size = FRAME1_VID_PROG_SIZE;
145 frame_size =
146 (bpl ==
147 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
148 FRAME_SIZE_NTSC_Y422;
149 } else {
150 risc_program_size = PAL_VID_PROG_SIZE;
151 frame_size =
152 (bpl ==
153 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
154 }
155
156 /* Virtual address of Risc buffer program */
157 rp = dev->_dma_virt_addr_ch2;
158
159 for (frame = 0; frame < NUM_FRAMES; frame++) {
160 databuf_offset = frame_size * frame;
161
162 if (UNSET != top_offset) {
163 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
164 rp = cx25821_risc_field_upstream_ch2(dev, rp,
165 dev->
166 _data_buf_phys_addr_ch2
167 + databuf_offset,
168 top_offset, 0, bpl,
169 odd_num_lines,
170 fifo_enable,
171 ODD_FIELD);
172 }
173
174 fifo_enable = FIFO_DISABLE;
175
176 //Even field
177 rp = cx25821_risc_field_upstream_ch2(dev, rp,
178 dev->
179 _data_buf_phys_addr_ch2 +
180 databuf_offset,
181 bottom_offset, 0x200, bpl,
182 singlefield_lines,
183 fifo_enable, EVEN_FIELD);
184
185 if (frame == 0) {
186 risc_flag = RISC_CNT_RESET;
187 risc_phys_jump_addr =
188 dev->_dma_phys_start_addr_ch2 + risc_program_size;
189 } else {
190 risc_flag = RISC_CNT_INC;
191 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
192 }
193
194 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
195 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
196 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
197 *(rp++) = cpu_to_le32(0);
198 }
199
200 return 0;
201 }
202
203 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
204 {
205 struct sram_channel *sram_ch =
206 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J];
207 u32 tmp = 0;
208
209 if (!dev->_is_running_ch2) {
210 printk
211 ("cx25821: No video file is currently running so return!\n");
212 return;
213 }
214 //Disable RISC interrupts
215 tmp = cx_read(sram_ch->int_msk);
216 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
217
218 //Turn OFF risc and fifo
219 tmp = cx_read(sram_ch->dma_ctl);
220 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
221
222 //Clear data buffer memory
223 if (dev->_data_buf_virt_addr_ch2)
224 memset(dev->_data_buf_virt_addr_ch2, 0,
225 dev->_data_buf_size_ch2);
226
227 dev->_is_running_ch2 = 0;
228 dev->_is_first_frame_ch2 = 0;
229 dev->_frame_count_ch2 = 0;
230 dev->_file_status_ch2 = END_OF_FILE;
231
232 if (dev->_irq_queues_ch2) {
233 kfree(dev->_irq_queues_ch2);
234 dev->_irq_queues_ch2 = NULL;
235 }
236
237 if (dev->_filename_ch2 != NULL)
238 kfree(dev->_filename_ch2);
239
240 tmp = cx_read(VID_CH_MODE_SEL);
241 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
242 }
243
244 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
245 {
246 if (dev->_is_running_ch2) {
247 cx25821_stop_upstream_video_ch2(dev);
248 }
249
250 if (dev->_dma_virt_addr_ch2) {
251 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
252 dev->_dma_virt_addr_ch2,
253 dev->_dma_phys_addr_ch2);
254 dev->_dma_virt_addr_ch2 = NULL;
255 }
256
257 if (dev->_data_buf_virt_addr_ch2) {
258 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
259 dev->_data_buf_virt_addr_ch2,
260 dev->_data_buf_phys_addr_ch2);
261 dev->_data_buf_virt_addr_ch2 = NULL;
262 }
263 }
264
265 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
266 {
267 struct file *myfile;
268 int frame_index_temp = dev->_frame_index_ch2;
269 int i = 0;
270 int line_size =
271 (dev->_pixel_format_ch2 ==
272 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
273 int frame_size = 0;
274 int frame_offset = 0;
275 ssize_t vfs_read_retval = 0;
276 char mybuf[line_size];
277 loff_t file_offset;
278 loff_t pos;
279 mm_segment_t old_fs;
280
281 if (dev->_file_status_ch2 == END_OF_FILE)
282 return 0;
283
284 if (dev->_isNTSC_ch2) {
285 frame_size =
286 (line_size ==
287 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
288 FRAME_SIZE_NTSC_Y422;
289 } else {
290 frame_size =
291 (line_size ==
292 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
293 }
294
295 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
296 file_offset = dev->_frame_count_ch2 * frame_size;
297
298 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
299
300 if (IS_ERR(myfile)) {
301 const int open_errno = -PTR_ERR(myfile);
302 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
303 __func__, dev->_filename_ch2, open_errno);
304 return PTR_ERR(myfile);
305 } else {
306 if (!(myfile->f_op)) {
307 printk("%s: File has no file operations registered!",
308 __func__);
309 filp_close(myfile, NULL);
310 return -EIO;
311 }
312
313 if (!myfile->f_op->read) {
314 printk("%s: File has no READ operations registered!",
315 __func__);
316 filp_close(myfile, NULL);
317 return -EIO;
318 }
319
320 pos = myfile->f_pos;
321 old_fs = get_fs();
322 set_fs(KERNEL_DS);
323
324 for (i = 0; i < dev->_lines_count_ch2; i++) {
325 pos = file_offset;
326
327 vfs_read_retval =
328 vfs_read(myfile, mybuf, line_size, &pos);
329
330 if (vfs_read_retval > 0 && vfs_read_retval == line_size
331 && dev->_data_buf_virt_addr_ch2 != NULL) {
332 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
333 frame_offset / 4), mybuf,
334 vfs_read_retval);
335 }
336
337 file_offset += vfs_read_retval;
338 frame_offset += vfs_read_retval;
339
340 if (vfs_read_retval < line_size) {
341 printk(KERN_INFO
342 "Done: exit %s() since no more bytes to read from Video file.\n",
343 __func__);
344 break;
345 }
346 }
347
348 if (i > 0)
349 dev->_frame_count_ch2++;
350
351 dev->_file_status_ch2 =
352 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
353
354 set_fs(old_fs);
355 filp_close(myfile, NULL);
356 }
357
358 return 0;
359 }
360
361 static void cx25821_vidups_handler_ch2(struct work_struct *work)
362 {
363 struct cx25821_dev *dev =
364 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
365
366 if (!dev) {
367 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
368 __func__);
369 return;
370 }
371
372 cx25821_get_frame_ch2(dev,
373 &dev->sram_channels[dev->
374 _channel2_upstream_select]);
375 }
376
377 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
378 {
379 struct file *myfile;
380 int i = 0, j = 0;
381 int line_size =
382 (dev->_pixel_format_ch2 ==
383 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
384 ssize_t vfs_read_retval = 0;
385 char mybuf[line_size];
386 loff_t pos;
387 loff_t offset = (unsigned long)0;
388 mm_segment_t old_fs;
389
390 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
391
392 if (IS_ERR(myfile)) {
393 const int open_errno = -PTR_ERR(myfile);
394 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
395 __func__, dev->_filename_ch2, open_errno);
396 return PTR_ERR(myfile);
397 } else {
398 if (!(myfile->f_op)) {
399 printk("%s: File has no file operations registered!",
400 __func__);
401 filp_close(myfile, NULL);
402 return -EIO;
403 }
404
405 if (!myfile->f_op->read) {
406 printk
407 ("%s: File has no READ operations registered! Returning.",
408 __func__);
409 filp_close(myfile, NULL);
410 return -EIO;
411 }
412
413 pos = myfile->f_pos;
414 old_fs = get_fs();
415 set_fs(KERNEL_DS);
416
417 for (j = 0; j < NUM_FRAMES; j++) {
418 for (i = 0; i < dev->_lines_count_ch2; i++) {
419 pos = offset;
420
421 vfs_read_retval =
422 vfs_read(myfile, mybuf, line_size, &pos);
423
424 if (vfs_read_retval > 0
425 && vfs_read_retval == line_size
426 && dev->_data_buf_virt_addr_ch2 != NULL) {
427 memcpy((void *)(dev->
428 _data_buf_virt_addr_ch2
429 + offset / 4), mybuf,
430 vfs_read_retval);
431 }
432
433 offset += vfs_read_retval;
434
435 if (vfs_read_retval < line_size) {
436 printk(KERN_INFO
437 "Done: exit %s() since no more bytes to read from Video file.\n",
438 __func__);
439 break;
440 }
441 }
442
443 if (i > 0)
444 dev->_frame_count_ch2++;
445
446 if (vfs_read_retval < line_size) {
447 break;
448 }
449 }
450
451 dev->_file_status_ch2 =
452 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
453
454 set_fs(old_fs);
455 myfile->f_pos = 0;
456 filp_close(myfile, NULL);
457 }
458
459 return 0;
460 }
461
462 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
463 struct sram_channel *sram_ch,
464 int bpl)
465 {
466 int ret = 0;
467 dma_addr_t dma_addr;
468 dma_addr_t data_dma_addr;
469
470 if (dev->_dma_virt_addr_ch2 != NULL) {
471 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
472 dev->_dma_virt_addr_ch2,
473 dev->_dma_phys_addr_ch2);
474 }
475
476 dev->_dma_virt_addr_ch2 =
477 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
478 &dma_addr);
479 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
480 dev->_dma_phys_start_addr_ch2 = dma_addr;
481 dev->_dma_phys_addr_ch2 = dma_addr;
482 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
483
484 if (!dev->_dma_virt_addr_ch2) {
485 printk
486 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
487 return -ENOMEM;
488 }
489
490 //Iniitize at this address until n bytes to 0
491 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
492
493 if (dev->_data_buf_virt_addr_ch2 != NULL) {
494 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
495 dev->_data_buf_virt_addr_ch2,
496 dev->_data_buf_phys_addr_ch2);
497 }
498 //For Video Data buffer allocation
499 dev->_data_buf_virt_addr_ch2 =
500 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
501 &data_dma_addr);
502 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
503 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
504
505 if (!dev->_data_buf_virt_addr_ch2) {
506 printk
507 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
508 return -ENOMEM;
509 }
510
511 //Initialize at this address until n bytes to 0
512 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
513
514 ret = cx25821_openfile_ch2(dev, sram_ch);
515 if (ret < 0)
516 return ret;
517
518 //Creating RISC programs
519 ret =
520 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
521 dev->_lines_count_ch2);
522 if (ret < 0) {
523 printk(KERN_INFO
524 "cx25821: Failed creating Video Upstream Risc programs! \n");
525 goto error;
526 }
527
528 return 0;
529
530 error:
531 return ret;
532 }
533
534 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
535 u32 status)
536 {
537 u32 int_msk_tmp;
538 struct sram_channel *channel = &dev->sram_channels[chan_num];
539 int singlefield_lines = NTSC_FIELD_HEIGHT;
540 int line_size_in_bytes = Y422_LINE_SZ;
541 int odd_risc_prog_size = 0;
542 dma_addr_t risc_phys_jump_addr;
543 __le32 *rp;
544
545 if (status & FLD_VID_SRC_RISC1) {
546 // We should only process one program per call
547 u32 prog_cnt = cx_read(channel->gpcnt);
548
549 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
550 int_msk_tmp = cx_read(channel->int_msk);
551 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
552 cx_write(channel->int_stat, _intr_msk);
553
554 spin_lock(&dev->slock);
555
556 dev->_frame_index_ch2 = prog_cnt;
557
558 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
559
560 if (dev->_is_first_frame_ch2) {
561 dev->_is_first_frame_ch2 = 0;
562
563 if (dev->_isNTSC_ch2) {
564 singlefield_lines += 1;
565 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
566 } else {
567 singlefield_lines = PAL_FIELD_HEIGHT;
568 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
569 }
570
571 if (dev->_dma_virt_start_addr_ch2 != NULL) {
572 line_size_in_bytes =
573 (dev->_pixel_format_ch2 ==
574 PIXEL_FRMT_411) ? Y411_LINE_SZ :
575 Y422_LINE_SZ;
576 risc_phys_jump_addr =
577 dev->_dma_phys_start_addr_ch2 +
578 odd_risc_prog_size;
579
580 rp = cx25821_update_riscprogram_ch2(dev,
581 dev->
582 _dma_virt_start_addr_ch2,
583 TOP_OFFSET,
584 line_size_in_bytes,
585 0x0,
586 singlefield_lines,
587 FIFO_DISABLE,
588 ODD_FIELD);
589
590 // Jump to Even Risc program of 1st Frame
591 *(rp++) = cpu_to_le32(RISC_JUMP);
592 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
593 *(rp++) = cpu_to_le32(0);
594 }
595 }
596
597 spin_unlock(&dev->slock);
598 }
599
600 if (dev->_file_status_ch2 == END_OF_FILE) {
601 printk("cx25821: EOF Channel 2 Framecount = %d\n",
602 dev->_frame_count_ch2);
603 return -1;
604 }
605 //ElSE, set the interrupt mask register, re-enable irq.
606 int_msk_tmp = cx_read(channel->int_msk);
607 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
608
609 return 0;
610 }
611
612 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
613 {
614 struct cx25821_dev *dev = dev_id;
615 u32 msk_stat, vid_status;
616 int handled = 0;
617 int channel_num = 0;
618 struct sram_channel *sram_ch;
619
620 if (!dev)
621 return -1;
622
623 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
624
625 sram_ch = &dev->sram_channels[channel_num];
626
627 msk_stat = cx_read(sram_ch->int_mstat);
628 vid_status = cx_read(sram_ch->int_stat);
629
630 // Only deal with our interrupt
631 if (vid_status) {
632 handled =
633 cx25821_video_upstream_irq_ch2(dev, channel_num,
634 vid_status);
635 }
636
637 if (handled < 0) {
638 cx25821_stop_upstream_video_ch2(dev);
639 } else {
640 handled += handled;
641 }
642
643 return IRQ_RETVAL(handled);
644 }
645
646 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
647 struct sram_channel *ch, int pix_format)
648 {
649 int width = WIDTH_D1;
650 int height = dev->_lines_count_ch2;
651 int num_lines, odd_num_lines;
652 u32 value;
653 int vip_mode = PIXEL_ENGINE_VIP1;
654
655 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
656 value &= 0xFFFFFFEF;
657 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
658 cx_write(ch->vid_fmt_ctl, value);
659
660 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
661 cx_write(ch->vid_active_ctl1, width);
662
663 num_lines = (height / 2) & 0x3FF;
664 odd_num_lines = num_lines;
665
666 if (dev->_isNTSC_ch2) {
667 odd_num_lines += 1;
668 }
669
670 value = (num_lines << 16) | odd_num_lines;
671
672 // set number of active lines in field 0 (top) and field 1 (bottom)
673 cx_write(ch->vid_active_ctl2, value);
674
675 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
676 }
677
678 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
679 struct sram_channel *sram_ch)
680 {
681 u32 tmp = 0;
682 int err = 0;
683
684 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
685 tmp = cx_read(VID_CH_MODE_SEL);
686 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
687
688 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
689 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
690 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
691
692 /* reset counter */
693 cx_write(sram_ch->gpcnt_ctl, 3);
694
695 // Clear our bits from the interrupt status register.
696 cx_write(sram_ch->int_stat, _intr_msk);
697
698 //Set the interrupt mask register, enable irq.
699 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
700 tmp = cx_read(sram_ch->int_msk);
701 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
702
703 err =
704 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
705 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
706 if (err < 0) {
707 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
708 dev->pci->irq);
709 goto fail_irq;
710 }
711 // Start the DMA engine
712 tmp = cx_read(sram_ch->dma_ctl);
713 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
714
715 dev->_is_running_ch2 = 1;
716 dev->_is_first_frame_ch2 = 1;
717
718 return 0;
719
720 fail_irq:
721 cx25821_dev_unregister(dev);
722 return err;
723 }
724
725 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
726 int pixel_format)
727 {
728 struct sram_channel *sram_ch;
729 u32 tmp;
730 int retval = 0;
731 int err = 0;
732 int data_frame_size = 0;
733 int risc_buffer_size = 0;
734 int str_length = 0;
735
736 if (dev->_is_running_ch2) {
737 printk("Video Channel is still running so return!\n");
738 return 0;
739 }
740
741 dev->_channel2_upstream_select = channel_select;
742 sram_ch = &dev->sram_channels[channel_select];
743
744 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
745 dev->_irq_queues_ch2 =
746 create_singlethread_workqueue("cx25821_workqueue2");
747
748 if (!dev->_irq_queues_ch2) {
749 printk
750 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
751 return -ENOMEM;
752 }
753 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
754 tmp = cx_read(VID_CH_MODE_SEL);
755 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
756
757 dev->_is_running_ch2 = 0;
758 dev->_frame_count_ch2 = 0;
759 dev->_file_status_ch2 = RESET_STATUS;
760 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
761 dev->_pixel_format_ch2 = pixel_format;
762 dev->_line_size_ch2 =
763 (dev->_pixel_format_ch2 ==
764 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
765 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
766 risc_buffer_size =
767 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
768
769 if (dev->input_filename_ch2) {
770 str_length = strlen(dev->input_filename_ch2);
771 dev->_filename_ch2 =
772 (char *)kmalloc(str_length + 1, GFP_KERNEL);
773
774 if (!dev->_filename_ch2)
775 goto error;
776
777 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
778 str_length + 1);
779 } else {
780 str_length = strlen(dev->_defaultname_ch2);
781 dev->_filename_ch2 =
782 (char *)kmalloc(str_length + 1, GFP_KERNEL);
783
784 if (!dev->_filename_ch2)
785 goto error;
786
787 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
788 str_length + 1);
789 }
790
791 //Default if filename is empty string
792 if (strcmp(dev->input_filename_ch2, "") == 0) {
793 if (dev->_isNTSC_ch2) {
794 dev->_filename_ch2 =
795 (dev->_pixel_format_ch2 ==
796 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
797 "/root/vidtest.yuv";
798 } else {
799 dev->_filename_ch2 =
800 (dev->_pixel_format_ch2 ==
801 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
802 "/root/pal422.yuv";
803 }
804 }
805
806 retval =
807 cx25821_sram_channel_setup_upstream(dev, sram_ch,
808 dev->_line_size_ch2, 0);
809
810 /* setup fifo + format */
811 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
812
813 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
814 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
815
816 //Allocating buffers and prepare RISC program
817 retval =
818 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
819 dev->_line_size_ch2);
820 if (retval < 0) {
821 printk(KERN_ERR
822 "%s: Failed to set up Video upstream buffers!\n",
823 dev->name);
824 goto error;
825 }
826
827 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
828
829 return 0;
830
831 error:
832 cx25821_dev_unregister(dev);
833
834 return err;
835 }
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