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[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / drivers / staging / rtl8192su / r8192U.h
blob2a11e0113d3a50c494dd9e8186dba256df861aeb
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 //#include <linux/pci.h>
31 #include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
41 #include <asm/io.h>
42
43 #include "ieee80211/ieee80211.h"
44
45 #include "r8192S_firmware.h"
46
47 //#define RTL8192U
48 #define RTL819xU_MODULE_NAME "rtl819xU"
49 //added for HW security, john.0629
50 #define FALSE 0
51 #define TRUE 1
52 #define MAX_KEY_LEN 61
53 #define KEY_BUF_SIZE 5
54
55 #define BIT0 0x00000001
56 #define BIT1 0x00000002
57 #define BIT2 0x00000004
58 #define BIT3 0x00000008
59 #define BIT4 0x00000010
60 #define BIT5 0x00000020
61 #define BIT6 0x00000040
62 #define BIT7 0x00000080
63 #define BIT8 0x00000100
64 #define BIT9 0x00000200
65 #define BIT10 0x00000400
66 #define BIT11 0x00000800
67 #define BIT12 0x00001000
68 #define BIT13 0x00002000
69 #define BIT14 0x00004000
70 #define BIT15 0x00008000
71 #define BIT16 0x00010000
72 #define BIT17 0x00020000
73 #define BIT18 0x00040000
74 #define BIT19 0x00080000
75 #define BIT20 0x00100000
76 #define BIT21 0x00200000
77 #define BIT22 0x00400000
78 #define BIT23 0x00800000
79 #define BIT24 0x01000000
80 #define BIT25 0x02000000
81 #define BIT26 0x04000000
82 #define BIT27 0x08000000
83 #define BIT28 0x10000000
84 #define BIT29 0x20000000
85 #define BIT30 0x40000000
86 #define BIT31 0x80000000
87
88 // Rx smooth factor
89 #define Rx_Smooth_Factor 20
90 #define DMESG(x,a...)
91 #define DMESGW(x,a...)
92 #define DMESGE(x,a...)
93 extern u32 rt_global_debug_component;
94 #define RT_TRACE(component, x, args...) \
95 do { if(rt_global_debug_component & component) \
96 printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
97 ##args);\
98 }while(0);
99 //----------------------------------------------------------------------
100 //// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15.
101 ////----------------------------------------------------------------------
102 #define RX_DESC_SIZE 24
103 #define RX_DRV_INFO_SIZE_UNIT 8
104
105 #define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
106 (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
107
108 #define COMP_TRACE BIT0 // For function call tracing.
109 #define COMP_DBG BIT1 // Only for temporary debug message.
110 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
111
112
113 #define COMP_RECV BIT3 // Reveive part data path.
114 #define COMP_SEND BIT4 // Send part path.
115 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
116 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
117 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
118 #define COMP_SWBW BIT8 // For bandwidth switch.
119 #define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING
120 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
121 #define COMP_QOS BIT11 // For QoS.
122 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
123 #define COMP_LPS BIT13 // For Radio Measurement.
124 #define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko.
125 #define COMP_PHY BIT15
126 #define COMP_CH BIT16 //channel setting debug
127 #define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko.
128 #define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko.
129 #define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko.
130 #define COMP_SEC BIT20 // Event handling
131 #define COMP_LED BIT21 // For LED.
132 #define COMP_RF BIT22 // For RF.
133 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
134 #define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
135 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
136 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
137
138 #define COMP_FIRMWARE BIT24 //for firmware downloading
139 #define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11
140 #define COMP_AMSDU BIT26 // For A-MSDU Debugging
141
142 #define COMP_SCAN BIT27
143 #define COMP_CMD BIT28
144 #define COMP_DOWN BIT29 //for rm driver module
145 #define COMP_RESET BIT30 //for silent reset
146 #define COMP_ERR BIT31 //for error out, always on
147
148 #define RTL819x_DEBUG
149 #ifdef RTL819x_DEBUG
150 #define assert(expr) \
151 if (!(expr)) { \
152 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
153 #expr,__FILE__,__FUNCTION__,__LINE__); \
154 }
155 //wb added to debug out data buf
156 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
157 #define RT_DEBUG_DATA(level, data, datalen) \
158 do{ if ((rt_global_debug_component & (level)) == (level)) \
159 { \
160 int i; \
161 u8* pdata = (u8*) data; \
162 printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
163 for(i=0; i<(int)(datalen); i++) \
164 { \
165 printk("%2x ", pdata[i]); \
166 if ((i+1)%16 == 0) printk("\n"); \
167 } \
168 printk("\n"); \
169 } \
170 } while (0)
171 #else
172 #define assert(expr) do {} while (0)
173 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
174 #endif /* RTL8169_DEBUG */
175
176 //#ifdef RTL8192SU
177 //2TODO: We should define 8192S firmware related macro settings here!!
178 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
179 #define RTL819X_TOTAL_RF_PATH 2
180
181 //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray
182 //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray
183 //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray
184
185 #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
186 #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
187 #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray
188 #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
189 //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array
190 //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array
191 #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array
192 #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array
193
194 //2008.11.06 Add.
195 #define Rtl819XFwImageArray Rtl8192SUFwImgArray
196 #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array
197 #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array
198 #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray
199 #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray
200 #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray
201 #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray
202 #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG
203 #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array
204 #define Rtl819XRadioB_Array Rtl8192SURadioB_Array
205 #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array
206 #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array
207 #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array
208 //#endif
209
210 //
211 // Queue Select Value in TxDesc
212 //
213 #define QSLT_BK 0x1
214 #define QSLT_BE 0x0
215 #define QSLT_VI 0x4
216 #define QSLT_VO 0x6
217 #define QSLT_BEACON 0x10
218 #define QSLT_HIGH 0x11
219 #define QSLT_MGNT 0x12
220 #define QSLT_CMD 0x13
221
222 #define DESC90_RATE1M 0x00
223 #define DESC90_RATE2M 0x01
224 #define DESC90_RATE5_5M 0x02
225 #define DESC90_RATE11M 0x03
226 #define DESC90_RATE6M 0x04
227 #define DESC90_RATE9M 0x05
228 #define DESC90_RATE12M 0x06
229 #define DESC90_RATE18M 0x07
230 #define DESC90_RATE24M 0x08
231 #define DESC90_RATE36M 0x09
232 #define DESC90_RATE48M 0x0a
233 #define DESC90_RATE54M 0x0b
234 #define DESC90_RATEMCS0 0x00
235 #define DESC90_RATEMCS1 0x01
236 #define DESC90_RATEMCS2 0x02
237 #define DESC90_RATEMCS3 0x03
238 #define DESC90_RATEMCS4 0x04
239 #define DESC90_RATEMCS5 0x05
240 #define DESC90_RATEMCS6 0x06
241 #define DESC90_RATEMCS7 0x07
242 #define DESC90_RATEMCS8 0x08
243 #define DESC90_RATEMCS9 0x09
244 #define DESC90_RATEMCS10 0x0a
245 #define DESC90_RATEMCS11 0x0b
246 #define DESC90_RATEMCS12 0x0c
247 #define DESC90_RATEMCS13 0x0d
248 #define DESC90_RATEMCS14 0x0e
249 #define DESC90_RATEMCS15 0x0f
250 #define DESC90_RATEMCS32 0x20
251
252 //#ifdef RTL8192SU
253 // CCK Rates, TxHT = 0
254 #define DESC92S_RATE1M 0x00
255 #define DESC92S_RATE2M 0x01
256 #define DESC92S_RATE5_5M 0x02
257 #define DESC92S_RATE11M 0x03
258
259 // OFDM Rates, TxHT = 0
260 #define DESC92S_RATE6M 0x04
261 #define DESC92S_RATE9M 0x05
262 #define DESC92S_RATE12M 0x06
263 #define DESC92S_RATE18M 0x07
264 #define DESC92S_RATE24M 0x08
265 #define DESC92S_RATE36M 0x09
266 #define DESC92S_RATE48M 0x0a
267 #define DESC92S_RATE54M 0x0b
268
269 // MCS Rates, TxHT = 1
270 #define DESC92S_RATEMCS0 0x0c
271 #define DESC92S_RATEMCS1 0x0d
272 #define DESC92S_RATEMCS2 0x0e
273 #define DESC92S_RATEMCS3 0x0f
274 #define DESC92S_RATEMCS4 0x10
275 #define DESC92S_RATEMCS5 0x11
276 #define DESC92S_RATEMCS6 0x12
277 #define DESC92S_RATEMCS7 0x13
278 #define DESC92S_RATEMCS8 0x14
279 #define DESC92S_RATEMCS9 0x15
280 #define DESC92S_RATEMCS10 0x16
281 #define DESC92S_RATEMCS11 0x17
282 #define DESC92S_RATEMCS12 0x18
283 #define DESC92S_RATEMCS13 0x19
284 #define DESC92S_RATEMCS14 0x1a
285 #define DESC92S_RATEMCS15 0x1b
286 #define DESC92S_RATEMCS15_SG 0x1c
287 #define DESC92S_RATEMCS32 0x20
288 //#endif
289
290 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
291
292 #define IEEE80211_WATCH_DOG_TIME 2000
293 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
294 //for txpowertracking by amy
295 #define OFDM_Table_Length 19
296 #define CCK_Table_length 12
297
298 //
299 //Tx Descriptor for RLT8192SU(Normal mode)
300 //
301 typedef struct _tx_desc_819x_usb {
302 // DWORD 0
303 u16 PktSize;//:16;
304 u8 Offset;//:8;
305 u8 Type:2; // Reserved for MAC header Frame Type subfield.
306 u8 LastSeg:1;
307 u8 FirstSeg:1;
308 u8 LINIP:1;
309 u8 AMSDU:1;
310 u8 GF:1;
311 u8 OWN:1;
312
313 // DWORD 1
314 u8 MacID:5;
315 u8 MoreData:1;
316 u8 MOREFRAG:1;
317 u8 PIFS:1;
318 u8 QueueSelect:5;
319 u8 AckPolicy:2;
320 u8 NoACM:1;
321 u8 NonQos:1;
322 u8 KeyID:2;
323 u8 OUI:1;
324 u8 PktType:1;
325 u8 EnDescID:1;
326 u8 SecType:2;
327 u8 HTC:1; //padding0
328 u8 WDS:1; //padding1
329 u8 PktOffset:5; //padding_len (hw)
330 u8 HWPC:1;
331
332 // DWORD 2
333 u32 DataRetryLmt:6;
334 u32 RetryLmtEn:1;
335 u32 TSFL:5;
336 u32 RTSRC:6; // Reserved for HW RTS Retry Count.
337 u32 DATARC:6; // Reserved for HW DATA Retry Count.
338 u32 Rsvd1:5;
339 u32 AllowAggregation:1;
340 u32 BK:1; //Aggregation break.
341 u32 OwnMAC:1;
342
343 // DWORD 3
344 u8 NextHeadPage;//:8;
345 u8 TailPage;//:8;
346 u16 Seq:12;
347 u16 Frag:4;
348
349 // DWORD 4
350 u32 RTSRate:6;
351 u32 DisRTSFB:1;
352 u32 RTSRateFBLmt:4;
353 u32 CTS2Self:1;
354 u32 RTSEn:1;
355 u32 RaBRSRID:3; //Rate adaptive BRSR ID.
356 u32 TxHT:1;
357 u32 TxShort:1;//for data
358 u32 TxBandwidth:1;
359 u32 TxSubCarrier:2;
360 u32 STBC:2;
361 u32 RD:1;
362 u32 RTSHT:1;
363 u32 RTSShort:1;
364 u32 RTSBW:1;
365 u32 RTSSubcarrier:2;
366 u32 RTSSTBC:2;
367 u32 USERATE:1;
368 // DWORD 5
369 u32 PktID:9;
370 u32 TxRate:6;
371 u32 DISFB:1;
372 u32 DataRateFBLmt:5;
373 u32 TxAGC:11;
374
375 // DWORD 6
376 u16 IPChkSum;//:16;
377 u16 TCPChkSum;//:16;
378
379 // DWORD 7
380 //u16 TxBuffSize;//:16;//pcie
381 u16 TxBufferSize;
382 u16 IPHdrOffset:8;
383 u16 Rsvd2:7;
384 u16 TCPEn:1;
385 }tx_desc_819x_usb, *ptx_desc_819x_usb;
386 typedef struct _tx_status_desc_8192s_usb{
387
388 //DWORD 0
389 u8 TxRate:6;
390 u8 Rsvd1:1;
391 u8 BandWidth:1;
392 u8 RTSRate:6;
393 u8 AGGLS:1;
394 u8 AGG:1;
395 u8 RTSRC:6;
396 u8 DataRC:6;
397 u8 FailCause:2;
398 u8 TxOK:1;
399 u8 Own:1;
400
401 //DWORD 1
402 u16 Seq:12;
403 u8 QueueSel:5;
404 u8 MACID:5;
405 u8 PwrMgt:1;
406 u8 MoreData:1;
407 u8 Rsvd2;
408
409 //DWORD 2
410 u8 RxAGC1;
411 u8 RxAGC2;
412 u8 RxAGC3;
413 u8 RxAGC4;
414 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
415
416
417
418 //
419 //Tx Descriptor for RLT8192SU(Load FW mode)
420 //
421 typedef struct _tx_desc_cmd_819x_usb{
422 // DWORD 0
423 u16 PktSize;
424 u8 Offset;
425 u8 Rsvd0:4;
426 u8 LINIP:1;
427 u8 Rsvd1:2;
428 u8 OWN:1;
429
430 // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
431 u32 Rsvd2;
432 u32 Rsvd3;
433 u32 Rsvd4;
434 u32 Rsvd5;
435 u32 Rsvd6;
436 u32 Rsvd7;
437
438 // DWORD 7
439 u16 TxBuffSize;//pcie
440 u16 Rsvd8;
441 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
442 //
443 //H2C Command for RLT8192SU(Host TxCmd)
444 //
445 typedef struct _tx_h2c_desc_cmd_8192s_usb{
446 // DWORD 0
447 u32 PktSize:16;
448 u32 Offset:8;
449 u32 Rsvd0:7;
450 u32 OWN:1;
451
452 // DWORD 1
453 u32 Rsvd1:8;
454 u32 QSEL:5;
455 u32 Rsvd2:19;
456
457 // DWORD 2
458 u32 Rsvd3;
459
460 // DWORD 3
461 u32 NextHeadPage:8;
462 u32 TailPage:8;
463 u32 Rsvd4:16;
464
465 // DWORD 4, 5, 6, 7
466 u32 Rsvd5;
467 u32 Rsvd6;
468 u32 Rsvd7;
469 u32 Rsvd8;
470 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
471
472
473 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
474 // DWORD 0
475 u32 CmdLen:16;
476 u32 ElementID:8;
477 u32 CmdSeq:8;
478
479 // DWORD 1
480 u32 Rsvd0;
481 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
482
483 typedef struct _tx_fwinfo_819x_usb{
484 //DWORD 0
485 u8 TxRate:7;
486 u8 CtsEnable:1;
487 u8 RtsRate:7;
488 u8 RtsEnable:1;
489 u8 TxHT:1;
490 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
491 u8 TxBandwidth:1; // This is used for HT MCS rate only.
492 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
493 u8 STBC:2;
494 u8 AllowAggregation:1;
495 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
496 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
497 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
498 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
499 u8 RtsSTBC:2;
500 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
501
502 //DWORD 1
503 u32 RxMF:2;
504 u32 RxAMD:3;
505 u32 Reserved1:3;
506 u32 TxAGCOffSet:4;//TxAGCOffset:4;
507 u32 TxAGCSign:1;
508 u32 Tx_INFO_RSVD:6;
509 u32 PacketID:13;
510 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
511
512 typedef struct rtl8192_rx_info {
513 struct urb *urb;
514 struct net_device *dev;
515 u8 out_pipe;
516 }rtl8192_rx_info ;
517
518 //typedef struct _RX_DESC_STATUS_8192SU{
519 typedef struct rx_desc_819x_usb{
520 //DWORD 0
521 u16 Length:14;
522 u16 CRC32:1;
523 u16 ICV:1;
524 u8 RxDrvInfoSize:4;
525 u8 Security:3;
526 u8 Qos:1;
527 u8 Shift:2;
528 u8 PHYStatus:1;
529 u8 SWDec:1;
530 u8 LastSeg:1;
531 u8 FirstSeg:1;
532 u8 EOR:1;
533 u8 Own:1;
534
535 //DWORD 1
536 u16 MACID:5;
537 u16 TID:4;
538 u16 HwRsvd:5;
539 u16 PAGGR:1;
540 u16 FAGGR:1;
541 u8 A1_FIT:4;
542 u8 A2_FIT:4;
543 u8 PAM:1;
544 u8 PWR:1;
545 u8 MoreData:1;
546 u8 MoreFrag:1;
547 u8 Type:2;
548 u8 MC:1;
549 u8 BC:1;
550
551 //DWORD 2
552 u16 Seq:12;
553 u16 Frag:4;
554 u8 NextPktLen;//:8;
555 u8 Rsvd0:6;
556 u8 NextIND:1;
557 u8 Rsvd1:1;
558
559 //DWORD 3
560 u8 RxMCS:6;
561 u8 RxHT:1;
562 u8 AMSDU:1;
563 u8 SPLCP:1;
564 u8 BW:1;
565 u8 HTC:1;
566 u8 TCPChkRpt:1;
567 u8 IPChkRpt:1;
568 u8 TCPChkValID:1;
569 u8 HwPCErr:1;
570 u8 HwPCInd:1;
571 u16 IV0;//:16;
572
573 //DWORD 4
574 u32 IV1;
575
576 //DWORD 5
577 u32 TSFL;
578 //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
579 }rx_desc_819x_usb, *prx_desc_819x_usb;
580
581
582 //
583 // Driver info are written to the begining of the RxBuffer
584 //
585 //typedef struct _RX_DRIVER_INFO_8192S{
586 typedef struct rx_drvinfo_819x_usb{
587 //
588 // Driver info contain PHY status and other variabel size info
589 // PHY Status content as below
590 //
591
592 //DWORD 0
593 /*u4Byte gain_0:7;
594 u4Byte trsw_0:1;
595 u4Byte gain_1:7;
596 u4Byte trsw_1:1;
597 u4Byte gain_2:7;
598 u4Byte trsw_2:1;
599 u4Byte gain_3:7;
600 u4Byte trsw_3:1; */
601 u8 gain_trsw[4];
602
603 //DWORD 1
604 /*u4Byte pwdb_all:8;
605 u4Byte cfosho_0:8;
606 u4Byte cfosho_1:8;
607 u4Byte cfosho_2:8;*/
608 u8 pwdb_all;
609 u8 cfosho[4];
610
611 //DWORD 2
612 /*u4Byte cfosho_3:8;
613 u4Byte cfotail_0:8;
614 u4Byte cfotail_1:8;
615 u4Byte cfotail_2:8;*/
616 u8 cfotail[4];
617
618 //DWORD 3
619 /*u4Byte cfotail_3:8;
620 u4Byte rxevm_0:8;
621 u4Byte rxevm_1:8;
622 u4Byte rxsnr_0:8;*/
623 char rxevm[2];
624 char rxsnr[4];
625
626 //DWORD 4
627 /*u4Byte rxsnr_1:8;
628 u4Byte rxsnr_2:8;
629 u4Byte rxsnr_3:8;
630 u4Byte pdsnr_0:8;*/
631 u8 pdsnr[2];
632
633 //DWORD 5
634 /*u4Byte pdsnr_1:8;
635 u4Byte csi_current_0:8;
636 u4Byte csi_current_1:8;
637 u4Byte csi_target_0:8;*/
638 u8 csi_current[2];
639 u8 csi_target[2];
640
641 //DWORD 6
642 /*u4Byte csi_target_1:8;
643 u4Byte sigevm:8;
644 u4Byte max_ex_pwr:8;
645 u4Byte ex_intf_flag:1;
646 u4Byte sgi_en:1;
647 u4Byte rxsc:2;
648 u4Byte reserve:4;*/
649 u8 sigevm;
650 u8 max_ex_pwr;
651 u8 ex_intf_flag:1;
652 u8 sgi_en:1;
653 u8 rxsc:2;
654 u8 reserve:4;
655
656 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
657
658 #define HWSET_MAX_SIZE_92S 128
659 #define MAX_802_11_HEADER_LENGTH 40
660 #define MAX_PKT_AGG_NUM 256
661 #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
662
663 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
664 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
665 //#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
666 #define ENCRYPTION_MAX_OVERHEAD 128
667 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
668 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
669 #define MAX_FRAGMENT_COUNT 8
670 #ifdef RTL8192U
671 #define MAX_TRANSMIT_BUFFER_SIZE 8000
672 #else
673 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
674 #endif
675 #define scrclng 4 // octets for crc32 (FCS, ICV)
676
677 typedef enum rf_optype
678 {
679 RF_OP_By_SW_3wire = 0,
680 RF_OP_By_FW,
681 RF_OP_MAX
682 }rf_op_type;
683 /* 8190 Loopback Mode definition */
684 typedef enum _rtl819xUsb_loopback{
685 RTL819xU_NO_LOOPBACK = 0,
686 RTL819xU_MAC_LOOPBACK = 1,
687 RTL819xU_DMA_LOOPBACK = 2,
688 RTL819xU_CCK_LOOPBACK = 3,
689 }rtl819xUsb_loopback_e;
690
691 /* for rtl819x */
692 typedef enum _RT_STATUS{
693 RT_STATUS_SUCCESS = 0,
694 RT_STATUS_FAILURE = 1,
695 RT_STATUS_PENDING = 2,
696 RT_STATUS_RESOURCE = 3
697 }RT_STATUS,*PRT_STATUS;
698
699 //#ifdef RTL8192SU
700 typedef enum _RTL8192SUSB_LOOPBACK{
701 RTL8192SU_NO_LOOPBACK = 0,
702 RTL8192SU_MAC_LOOPBACK = 1,
703 RTL8192SU_DMA_LOOPBACK = 2,
704 RTL8192SU_CCK_LOOPBACK = 3,
705 }RTL8192SUSB_LOOPBACK_E;
706 //#endif
707
708 //+by amy 080507
709 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
710
711
712 /* Firmware Queue Layout */
713 #define NUM_OF_FIRMWARE_QUEUE 10
714 #define NUM_OF_PAGES_IN_FW 0x100
715
716
717 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020
718 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020
719 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040
720 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040
721 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
722 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4
723 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20
724 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
725 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
726 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18
727
728
729 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
730 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
731 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
732 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
733 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
734 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
735 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
736 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
737 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
738 //=================================================================
739 //=================================================================
740
741 #define EPROM_93c46 0
742 #define EPROM_93c56 1
743
744 #define DEFAULT_FRAG_THRESHOLD 2342U
745 #define MIN_FRAG_THRESHOLD 256U
746 #define DEFAULT_BEACONINTERVAL 0x64U
747 #define DEFAULT_BEACON_ESSID "Rtl819xU"
748
749 #define DEFAULT_SSID ""
750 #define DEFAULT_RETRY_RTS 7
751 #define DEFAULT_RETRY_DATA 7
752 #define PRISM_HDR_SIZE 64
753
754 #define PHY_RSSI_SLID_WIN_MAX 100
755
756
757 typedef enum _WIRELESS_MODE {
758 WIRELESS_MODE_UNKNOWN = 0x00,
759 WIRELESS_MODE_A = 0x01,
760 WIRELESS_MODE_B = 0x02,
761 WIRELESS_MODE_G = 0x04,
762 WIRELESS_MODE_AUTO = 0x08,
763 WIRELESS_MODE_N_24G = 0x10,
764 WIRELESS_MODE_N_5G = 0x20
765 } WIRELESS_MODE;
766
767
768 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
769
770 typedef struct buffer
771 {
772 struct buffer *next;
773 u32 *buf;
774
775 } buffer;
776
777 typedef struct rtl_reg_debug{
778 unsigned int cmd;
779 struct {
780 unsigned char type;
781 unsigned char addr;
782 unsigned char page;
783 unsigned char length;
784 } head;
785 unsigned char buf[0xff];
786 }rtl_reg_debug;
787
788 typedef struct _rt_9x_tx_rate_history {
789 u32 cck[4];
790 u32 ofdm[8];
791 // HT_MCS[0][]: BW=0 SG=0
792 // HT_MCS[1][]: BW=1 SG=0
793 // HT_MCS[2][]: BW=0 SG=1
794 // HT_MCS[3][]: BW=1 SG=1
795 u32 ht_mcs[4][16];
796 }rt_tx_rahis_t, *prt_tx_rahis_t;
797 typedef struct _RT_SMOOTH_DATA_4RF {
798 char elements[4][100];//array to store values
799 u32 index; //index to current array to store
800 u32 TotalNum; //num of valid elements
801 u32 TotalVal[4]; //sum of valid elements
802 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
803
804 #define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size
805 //stats seems messed up, clean it ASAP
806 typedef struct Stats
807 {
808 unsigned long txrdu;
809 // unsigned long rxrdu;
810 //unsigned long rxnolast;
811 //unsigned long rxnodata;
812 // unsigned long rxreset;
813 // unsigned long rxnopointer;
814 unsigned long rxok;
815 unsigned long rxframgment;
816 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
817 unsigned long rxurberr;
818 unsigned long rxstaterr;
819 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
820 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
821 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
822 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
823 unsigned long numpacket_matchbssid; // debug use only.
824 unsigned long numpacket_toself; // debug use only.
825 unsigned long num_process_phyinfo; // debug use only.
826 unsigned long numqry_phystatus;
827 unsigned long numqry_phystatusCCK;
828 unsigned long numqry_phystatusHT;
829 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
830 unsigned long txnperr;
831 unsigned long txnpdrop;
832 unsigned long txresumed;
833 // unsigned long rxerr;
834 // unsigned long rxoverflow;
835 // unsigned long rxint;
836 unsigned long txnpokint;
837 // unsigned long txhpokint;
838 // unsigned long txhperr;
839 // unsigned long ints;
840 // unsigned long shints;
841 unsigned long txoverflow;
842 // unsigned long rxdmafail;
843 // unsigned long txbeacon;
844 // unsigned long txbeaconerr;
845 unsigned long txlpokint;
846 unsigned long txlpdrop;
847 unsigned long txlperr;
848 unsigned long txbeokint;
849 unsigned long txbedrop;
850 unsigned long txbeerr;
851 unsigned long txbkokint;
852 unsigned long txbkdrop;
853 unsigned long txbkerr;
854 unsigned long txviokint;
855 unsigned long txvidrop;
856 unsigned long txvierr;
857 unsigned long txvookint;
858 unsigned long txvodrop;
859 unsigned long txvoerr;
860 unsigned long txbeaconokint;
861 unsigned long txbeacondrop;
862 unsigned long txbeaconerr;
863 unsigned long txmanageokint;
864 unsigned long txmanagedrop;
865 unsigned long txmanageerr;
866 unsigned long txdatapkt;
867 unsigned long txfeedback;
868 unsigned long txfeedbackok;
869
870 unsigned long txoktotal;
871 unsigned long txokbytestotal;
872 unsigned long txokinperiod;
873 unsigned long txmulticast;
874 unsigned long txbytesmulticast;
875 unsigned long txbroadcast;
876 unsigned long txbytesbroadcast;
877 unsigned long txunicast;
878 unsigned long txbytesunicast;
879
880 unsigned long rxoktotal;
881 unsigned long rxbytesunicast;
882 unsigned long txfeedbackfail;
883 unsigned long txerrtotal;
884 unsigned long txerrbytestotal;
885 unsigned long txerrmulticast;
886 unsigned long txerrbroadcast;
887 unsigned long txerrunicast;
888 unsigned long txretrycount;
889 unsigned long txfeedbackretry;
890 u8 last_packet_rate;
891 unsigned long slide_signal_strength[100];
892 unsigned long slide_evm[100];
893 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
894 unsigned long slide_evm_total; // For recording sliding window's EVM value
895 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
896 long signal_quality;
897 long last_signal_strength_inpercent;
898 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
899 u8 rx_rssi_percentage[4];
900 u8 rx_evm_percentage[2];
901 long rxSNRdB[4];
902 rt_tx_rahis_t txrate;
903 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
904 u32 Slide_Beacon_Total; //cosa add for beacon rssi
905 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
906
907 u32 CurrentShowTxate;
908 } Stats;
909
910
911 // Bandwidth Offset
912 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
913 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
914 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
915
916 //+by amy 080507
917
918 typedef struct ChnlAccessSetting {
919 u16 SIFS_Timer;
920 u16 DIFS_Timer;
921 u16 SlotTimeTimer;
922 u16 EIFS_Timer;
923 u16 CWminIndex;
924 u16 CWmaxIndex;
925 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
926
927 typedef struct _BB_REGISTER_DEFINITION{
928 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
929 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
930 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
931 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
932 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
933 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
934 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
935 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
936 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
937 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
938 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
939 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
940 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
941 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
942 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
943 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
944 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
945 u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
946 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
947
948 typedef enum _RT_RF_TYPE_819xU{
949 RF_TYPE_MIN = 0,
950 RF_8225,
951 RF_8256,
952 RF_8258,
953 RF_6052=4, // 4 11b/g/n RF
954 RF_PSEUDO_11N = 5,
955 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
956
957 //#ifdef RTL8192SU
958 typedef enum _RF_POWER_STATE{
959 RF_ON,
960 RF_SLEEP,
961 RF_OFF,
962 RF_SHUT_DOWN,
963 }RF_POWER_STATE, *PRF_POWER_STATE;
964 //#endif
965
966 typedef struct _rate_adaptive
967 {
968 u8 rate_adaptive_disabled;
969 u8 ratr_state;
970 u16 reserve;
971
972 u32 high_rssi_thresh_for_ra;
973 u32 high2low_rssi_thresh_for_ra;
974 u8 low2high_rssi_thresh_for_ra40M;
975 u32 low_rssi_thresh_for_ra40M;
976 u8 low2high_rssi_thresh_for_ra20M;
977 u32 low_rssi_thresh_for_ra20M;
978 u32 upper_rssi_threshold_ratr;
979 u32 middle_rssi_threshold_ratr;
980 u32 low_rssi_threshold_ratr;
981 u32 low_rssi_threshold_ratr_40M;
982 u32 low_rssi_threshold_ratr_20M;
983 u8 ping_rssi_enable; //cosa add for test
984 u32 ping_rssi_ratr; //cosa add for test
985 u32 ping_rssi_thresh_for_ra;//cosa add for test
986 u32 last_ratr;
987
988 } rate_adaptive, *prate_adaptive;
989
990 #define TxBBGainTableLength 37
991 #define CCKTxBBGainTableLength 23
992
993 typedef struct _txbbgain_struct
994 {
995 long txbb_iq_amplifygain;
996 u32 txbbgain_value;
997 } txbbgain_struct, *ptxbbgain_struct;
998
999 typedef struct _ccktxbbgain_struct
1000 {
1001 //The Value is from a22 to a29 one Byte one time is much Safer
1002 u8 ccktxbb_valuearray[8];
1003 } ccktxbbgain_struct,*pccktxbbgain_struct;
1004
1005
1006 typedef struct _init_gain
1007 {
1008 u8 xaagccore1;
1009 u8 xbagccore1;
1010 u8 xcagccore1;
1011 u8 xdagccore1;
1012 u8 cca;
1013
1014 } init_gain, *pinit_gain;
1015 //by amy 0606
1016
1017 typedef struct _phy_ofdm_rx_status_report_819xusb
1018 {
1019 u8 trsw_gain_X[4];
1020 u8 pwdb_all;
1021 u8 cfosho_X[4];
1022 u8 cfotail_X[4];
1023 u8 rxevm_X[2];
1024 u8 rxsnr_X[4];
1025 u8 pdsnr_X[2];
1026 u8 csi_current_X[2];
1027 u8 csi_target_X[2];
1028 u8 sigevm;
1029 u8 max_ex_pwr;
1030 u8 sgi_en;
1031 u8 rxsc_sgien_exflg;
1032 }phy_sts_ofdm_819xusb_t;
1033
1034 typedef struct _phy_cck_rx_status_report_819xusb
1035 {
1036 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1037 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1038 u8 adc_pwdb_X[4];
1039 u8 sq_rpt;
1040 u8 cck_agc_rpt;
1041 }phy_sts_cck_819xusb_t;
1042
1043
1044 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1045 u8 reserved:4;
1046 u8 rxsc:2;
1047 u8 sgi_en:1;
1048 u8 ex_intf_flag:1;
1049 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1050
1051 typedef enum _RT_CUSTOMER_ID
1052 {
1053 RT_CID_DEFAULT = 0,
1054 RT_CID_8187_ALPHA0 = 1,
1055 RT_CID_8187_SERCOMM_PS = 2,
1056 RT_CID_8187_HW_LED = 3,
1057 RT_CID_8187_NETGEAR = 4,
1058 RT_CID_WHQL = 5,
1059 RT_CID_819x_CAMEO = 6,
1060 RT_CID_819x_RUNTOP = 7,
1061 RT_CID_819x_Senao = 8,
1062 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
1063 RT_CID_819x_Netcore = 10,
1064 RT_CID_Nettronix = 11,
1065 RT_CID_DLINK = 12,
1066 RT_CID_PRONET = 13,
1067 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1068
1069 //================================================================================
1070 // LED customization.
1071 //================================================================================
1072
1073 typedef enum _LED_STRATEGY_8190{
1074 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
1075 SW_LED_MODE1, // SW control for PCI Express
1076 SW_LED_MODE2, // SW control for Cameo.
1077 SW_LED_MODE3, // SW contorl for RunTop.
1078 SW_LED_MODE4, // SW control for Netcore
1079 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
1080 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
1081
1082 typedef enum _RESET_TYPE {
1083 RESET_TYPE_NORESET = 0x00,
1084 RESET_TYPE_NORMAL = 0x01,
1085 RESET_TYPE_SILENT = 0x02
1086 } RESET_TYPE;
1087
1088 /* The simple tx command OP code. */
1089 typedef enum _tag_TxCmd_Config_Index{
1090 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
1091 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
1092 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
1093 TXCMD_SET_TX_DURATION = 0xFF900003,
1094 TXCMD_SET_RX_RSSI = 0xFF900004,
1095 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
1096 TXCMD_XXXX_CTRL,
1097 }DCMD_TXCMD_OP;
1098
1099 typedef enum{
1100 NIC_8192U = 1,
1101 NIC_8190P = 2,
1102 NIC_8192E = 3,
1103 NIC_8192SE = 4,
1104 NIC_8192SU = 5,
1105 } nic_t;
1106
1107 //definded by WB. Ready to fill handlers for different NIC types.
1108 //add handle here when necessary.
1109 struct rtl819x_ops{
1110 nic_t nic_type;
1111 void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1112 short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1113 short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1114 void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1115 void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1116 bool (* rtl819x_adapter_start)(struct net_device *dev);
1117 void (* rtl819x_link_change)(struct net_device *dev);
1118 void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1119 void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1120 };
1121
1122 typedef struct r8192_priv
1123 {
1124 struct rtl819x_ops* ops;
1125 struct usb_device *udev;
1126 //added for maintain info from eeprom
1127 short epromtype;
1128 u16 eeprom_vid;
1129 u16 eeprom_pid;
1130 u8 eeprom_CustomerID;
1131 u8 eeprom_SubCustomerID;
1132 u8 eeprom_ChannelPlan;
1133 RT_CUSTOMER_ID CustomerID;
1134 LED_STRATEGY_8190 LedStrategy;
1135 u8 txqueue_to_outpipemap[9];
1136 u8 RtOutPipes[16];
1137 u8 RtInPipes[16];
1138 u8 ep_in_num;
1139 u8 ep_out_num;
1140 u8 ep_num;
1141 int irq;
1142 struct ieee80211_device *ieee80211;
1143
1144 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1145 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1146 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1147 short enable_gpio0;
1148 enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1149 short hw_plcp_len;
1150 short plcp_preamble_mode;
1151
1152 spinlock_t irq_lock;
1153 // spinlock_t irq_th_lock;
1154 spinlock_t tx_lock;
1155 spinlock_t ps_lock;
1156 struct mutex mutex;
1157 spinlock_t rf_lock; //used to lock rf write operation added by wb
1158
1159 u16 irq_mask;
1160 // short irq_enabled;
1161 // struct net_device *dev; //comment this out.
1162 short chan;
1163 short sens;
1164 short max_sens;
1165
1166
1167 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1168 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1169 // u8 cck_txpwr_base;
1170 // u8 ofdm_txpwr_base;
1171 // u8 challow[15]; //channels from 1 to 14, 0 not used
1172 short up;
1173 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1174 // short prism_hdr;
1175
1176 // struct timer_list scan_timer;
1177 /*short scanpending;
1178 short stopscan;*/
1179 // spinlock_t scan_lock;
1180 // u8 active_probe;
1181 //u8 active_scan_num;
1182 struct semaphore wx_sem;
1183 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1184 // short hw_wep;
1185
1186 // short digphy;
1187 // short antb;
1188 // short diversity;
1189 // u8 cs_treshold;
1190 // short rcr_csense;
1191 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1192 RT_RF_TYPE_819xU rf_chip;
1193
1194 // u32 key0[4];
1195 short (*rf_set_sens)(struct net_device *dev,short sens);
1196 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1197 void (*rf_close)(struct net_device *dev);
1198 void (*rf_init)(struct net_device *dev);
1199 //short rate;
1200 short promisc;
1201 /*stats*/
1202 struct Stats stats;
1203 struct iw_statistics wstats;
1204 struct proc_dir_entry *dir_dev;
1205
1206 /*RX stuff*/
1207 // u32 *rxring;
1208 // u32 *rxringtail;
1209 // dma_addr_t rxringdma;
1210 struct urb **rx_urb;
1211 struct urb **rx_cmd_urb;
1212
1213 /* modified by davad for Rx process */
1214 struct sk_buff_head rx_queue;
1215 struct sk_buff_head skb_queue;
1216
1217 struct work_struct qos_activate;
1218
1219 short tx_urb_index;
1220 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1221
1222
1223 struct tasklet_struct irq_rx_tasklet;
1224 struct urb *rxurb_task;
1225
1226 //2 Tx Related variables
1227 u16 ShortRetryLimit;
1228 u16 LongRetryLimit;
1229 u32 TransmitConfig;
1230 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1231
1232 u32 LastRxDescTSFHigh;
1233 u32 LastRxDescTSFLow;
1234
1235
1236 //2 Rx Related variables
1237 u16 EarlyRxThreshold;
1238 u32 ReceiveConfig;
1239 u8 AcmControl;
1240
1241 u8 RFProgType;
1242
1243 u8 retry_data;
1244 u8 retry_rts;
1245 u16 rts;
1246
1247 struct ChnlAccessSetting ChannelAccessSetting;
1248
1249 struct work_struct reset_wq;
1250
1251 /**********************************************************/
1252 //for rtl819xUsb
1253 u16 basic_rate;
1254 u8 short_preamble;
1255 u8 slot_time;
1256 bool bDcut;
1257 bool bCurrentRxAggrEnable;
1258 u8 Rf_Mode; //add for Firmware RF -R/W switch
1259 prt_firmware pFirmware;
1260 rtl819xUsb_loopback_e LoopbackMode;
1261 firmware_source_e firmware_source;
1262 bool usb_error;
1263
1264 u16 EEPROMTxPowerDiff;
1265 u8 EEPROMThermalMeter;
1266 u8 EEPROMPwDiff;
1267 u8 EEPROMCrystalCap;
1268 u8 EEPROM_Def_Ver;
1269 u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1270 u8 EEPROMTxPowerLevelCCK_V1[3];
1271 u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1272 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1273
1274 //RTL8192SU
1275 bool bDmDisableProtect;
1276 bool bIgnoreDiffRateTxPowerOffset;
1277
1278 // For EEPROM TX Power Index like 8190 series
1279 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1280 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1281 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1282 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1283
1284 // F92S new definition
1285 //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1286 u8 RfCckChnlAreaTxPwr[2][3];
1287 u8 RfOfdmChnlAreaTxPwr1T[2][3];
1288 u8 RfOfdmChnlAreaTxPwr2T[2][3];
1289
1290 // Add For EEPROM Efuse switch and Efuse Shadow map Setting
1291 bool EepromOrEfuse;
1292 bool bBootFromEfuse; // system boot form EFUSE
1293 u8 EfuseMap[2][HWSET_MAX_SIZE_92S];
1294
1295 u8 EEPROMUsbOption;
1296 u8 EEPROMUsbPhyParam[5];
1297 u8 EEPROMTxPwrBase;
1298 u8 EEPROMBoardType;
1299 bool bBootFromEEPROM; // system boot from EEPROM
1300 u8 EEPROMTSSI_A;
1301 u8 EEPROMTSSI_B;
1302 u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B.
1303 u8 EEPROMTxPwrTkMode;
1304
1305 u8 bTXPowerDataReadFromEEPORM;
1306
1307 u8 EEPROMVersion;
1308 u8 EEPROMUsbEndPointNumber;
1309
1310 bool AutoloadFailFlag;
1311 u8 RfTxPwrLevelCck[2][14];
1312 u8 RfTxPwrLevelOfdm1T[2][14];
1313 u8 RfTxPwrLevelOfdm2T[2][14];
1314 // 2009/01/20 MH Add for new EEPROM format.
1315 u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff
1316 u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff
1317 u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel
1318 u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel
1319 u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel
1320 u8 TxPwrbandEdgeFlag; // Band edge enable flag
1321
1322 // L1 and L2 high power threshold.
1323 u8 MidHighPwrTHR_L1;
1324 u8 MidHighPwrTHR_L2;
1325 u8 TxPwrSafetyFlag; // for Tx power safety spec
1326 //RTL8192SU
1327
1328 /*PHY related*/
1329 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1330 // Read/write are allow for following hardware information variables
1331 u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1332 u32 CCKTxPowerLevelOriginalOffset;
1333 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1334 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1335 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1336 u32 Pwr_Track;
1337 u8 TxPowerDiff;
1338 u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1339 u8 CrystalCap; // CrystalCap.
1340 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1341
1342 u8 CckPwEnl;
1343 // Use to calculate PWBD.
1344 u8 bCckHighPower;
1345 long undecorated_smoothed_pwdb;
1346
1347 //for set channel
1348 u8 SwChnlInProgress;
1349 u8 SwChnlStage;
1350 u8 SwChnlStep;
1351 u8 SetBWModeInProgress;
1352 HT_CHANNEL_WIDTH CurrentChannelBW;
1353 u8 ChannelPlan;
1354 u8 pwrGroupCnt;
1355 // 8190 40MHz mode
1356 //
1357 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1358 // Joseph test for shorten RF configuration time.
1359 // We save RF reg0 in this variable to reduce RF reading.
1360 //
1361 u32 RfReg0Value[4];
1362 u8 NumTotalRFPath;
1363 bool brfpath_rxenable[4];
1364 //RF set related
1365 bool SetRFPowerStateInProgress;
1366 //+by amy 080507
1367 struct timer_list watch_dog_timer;
1368
1369 //+by amy 080515 for dynamic mechenism
1370 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1371 bool bdynamic_txpower; //bDynamicTxPower
1372 bool bDynamicTxHighPower; // Tx high power state
1373 bool bDynamicTxLowPower; // Tx low power state
1374 bool bLastDTPFlag_High;
1375 bool bLastDTPFlag_Low;
1376
1377 bool bstore_last_dtpflag;
1378 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1379 //Add by amy for Rate Adaptive
1380 rate_adaptive rate_adaptive;
1381 //Add by amy for TX power tracking
1382 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1383 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1384 u8 EEPROMTxPowerTrackEnable;
1385 u8 txpower_count;//For 6 sec do tracking again
1386 bool btxpower_trackingInit;
1387 u8 OFDM_index;
1388 u8 CCK_index;
1389 //2007/09/10 Mars Add CCK TX Power Tracking
1390 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1391 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1392 u8 rfa_txpowertrackingindex;
1393 u8 rfa_txpowertrackingindex_real;
1394 u8 rfa_txpowertracking_default;
1395 u8 rfc_txpowertrackingindex;
1396 u8 rfc_txpowertrackingindex_real;
1397
1398 s8 cck_present_attentuation;
1399 u8 cck_present_attentuation_20Mdefault;
1400 u8 cck_present_attentuation_40Mdefault;
1401 char cck_present_attentuation_difference;
1402 bool btxpower_tracking;
1403 bool bcck_in_ch14;
1404 bool btxpowerdata_readfromEEPORM;
1405 u16 TSSI_13dBm;
1406 //For Backup Initial Gain
1407 init_gain initgain_backup;
1408 u8 DefaultInitialGain[4];
1409 // For EDCA Turbo mode, Added by amy 080515.
1410 bool bis_any_nonbepkts;
1411 bool bcurrent_turbo_EDCA;
1412 bool bis_cur_rdlstate;
1413 struct timer_list fsync_timer;
1414 bool bfsync_processing; // 500ms Fsync timer is active or not
1415 u32 rate_record;
1416 u32 rateCountDiffRecord;
1417 u32 ContiuneDiffCount;
1418 bool bswitch_fsync;
1419
1420 u8 framesync;
1421 u32 framesyncC34;
1422 u8 framesyncMonitor;
1423 //Added by amy 080516 for RX related
1424 u16 nrxAMPDU_size;
1425 u8 nrxAMPDU_aggr_num;
1426
1427 //by amy for gpio
1428 bool bHwRadioOff;
1429
1430 //by amy for reset_count
1431 u32 reset_count;
1432 bool bpbc_pressed;
1433 //by amy for debug
1434 u32 txpower_checkcnt;
1435 u32 txpower_tracking_callback_cnt;
1436 u8 thermal_read_val[40];
1437 u8 thermal_readback_index;
1438 u32 ccktxpower_adjustcnt_not_ch14;
1439 u32 ccktxpower_adjustcnt_ch14;
1440 u8 tx_fwinfo_force_subcarriermode;
1441 u8 tx_fwinfo_force_subcarrierval;
1442 //by amy for silent reset
1443 RESET_TYPE ResetProgress;
1444 bool bForcedSilentReset;
1445 bool bDisableNormalResetCheck;
1446 u16 TxCounter;
1447 u16 RxCounter;
1448 int IrpPendingCount;
1449 bool bResetInProgress;
1450 bool force_reset;
1451 u8 InitialGainOperateType;
1452
1453 u16 SifsTime;
1454
1455 //define work item by amy 080526
1456 struct delayed_work update_beacon_wq;
1457 struct delayed_work watch_dog_wq;
1458 struct delayed_work txpower_tracking_wq;
1459 struct delayed_work rfpath_check_wq;
1460 struct delayed_work gpio_change_rf_wq;
1461 struct delayed_work initialgain_operate_wq;
1462
1463 struct workqueue_struct *priv_wq;
1464 //#ifdef RTL8192SU
1465 //lzm add for 8192S
1466 u32 IntrMask;
1467 // RF and BB access related synchronization flags.
1468 bool bChangeBBInProgress; // BaseBand RW is still in progress.
1469 bool bChangeRFInProgress; // RF RW is still in progress.
1470
1471 u32 CCKTxPowerAdjustCntCh14; //debug only
1472 u32 CCKTxPowerAdjustCntNotCh14; //debug only
1473 u32 TXPowerTrackingCallbackCnt; //debug only
1474 u32 TxPowerCheckCnt; //debug only
1475 u32 RFWritePageCnt[3]; //debug only
1476 u32 RFReadPageCnt[3]; //debug only
1477 u8 ThermalReadBackIndex; //debug only
1478 u8 ThermalReadVal[40]; //debug only
1479
1480 // For HCT test, 2005.07.15, by rcnjko.
1481 // not realize true, just define it, set it 0 default, because some func use it
1482 bool bInHctTest;
1483
1484 // The current Tx Power Level
1485 u8 CurrentCckTxPwrIdx;
1486 u8 CurrentOfdm24GTxPwrIdx;
1487
1488 // For pass 92S common phycfg.c compiler
1489 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1490 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1491 u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14
1492 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1493 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1494 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1495
1496 bool bRFSiOrPi;//0=si, 1=pi.
1497 //lzm add for 8192S
1498
1499 bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1500 u8 CurrentFwCmdIO;
1501
1502 u8 MinSpaceCfg;
1503
1504 u16 rf_pathmap;
1505 //#endif
1506
1507
1508
1509
1510
1511 }r8192_priv;
1512
1513 // for rtl8187
1514 // now mirging to rtl8187B
1515 /*
1516 typedef enum{
1517 LOW_PRIORITY = 0x02,
1518 NORM_PRIORITY
1519 } priority_t;
1520 */
1521 //for rtl8187B
1522 typedef enum{
1523 BULK_PRIORITY = 0x01,
1524 //RSVD0,
1525 //RSVD1,
1526 LOW_PRIORITY,
1527 NORM_PRIORITY,
1528 VO_PRIORITY,
1529 VI_PRIORITY, //0x05
1530 BE_PRIORITY,
1531 BK_PRIORITY,
1532 RSVD2,
1533 RSVD3,
1534 BEACON_PRIORITY, //0x0A
1535 HIGH_PRIORITY,
1536 MANAGE_PRIORITY,
1537 RSVD4,
1538 RSVD5,
1539 UART_PRIORITY //0x0F
1540 } priority_t;
1541
1542 #ifdef JOHN_HWSEC
1543 struct ssid_thread {
1544 struct net_device *dev;
1545 u8 name[IW_ESSID_MAX_SIZE + 1];
1546 };
1547 #endif
1548
1549 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1550 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
1551 bool FirmwareDownload92S(struct net_device *dev);
1552
1553 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1554 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1555
1556 u32 read_cam(struct net_device *dev, u8 addr);
1557 void write_cam(struct net_device *dev, u8 addr, u32 data);
1558
1559 u8 read_nic_byte(struct net_device *dev, int x);
1560 u8 read_nic_byte_E(struct net_device *dev, int x);
1561 u32 read_nic_dword(struct net_device *dev, int x);
1562 u16 read_nic_word(struct net_device *dev, int x) ;
1563 void write_nic_byte(struct net_device *dev, int x,u8 y);
1564 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1565 void write_nic_word(struct net_device *dev, int x,u16 y);
1566 void write_nic_dword(struct net_device *dev, int x,u32 y);
1567 void force_pci_posting(struct net_device *dev);
1568
1569 void rtl8192_rtx_disable(struct net_device *);
1570 void rtl8192_rx_enable(struct net_device *);
1571 void rtl8192_tx_enable(struct net_device *);
1572
1573 void rtl8192_disassociate(struct net_device *dev);
1574 //void fix_rx_fifo(struct net_device *dev);
1575 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1576
1577 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1578 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1579 void rtl8192_update_msr(struct net_device *dev);
1580 int rtl8192_down(struct net_device *dev);
1581 int rtl8192_up(struct net_device *dev);
1582 void rtl8192_commit(struct net_device *dev);
1583 void rtl8192_set_chan(struct net_device *dev,short ch);
1584 void write_phy(struct net_device *dev, u8 adr, u8 data);
1585 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1586 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1587 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1588 void rtl8192_set_rxconf(struct net_device *dev);
1589 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1590 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate);
1591 void CamResetAllEntry(struct net_device* dev);
1592 void EnableHWSecurityConfig8192(struct net_device *dev);
1593 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1594 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1595
1596 #endif
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