drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *reclaim;
  77         unsigned                scanning : 1;
  78
  79         /* periodic schedule support */
  80 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  81         unsigned                periodic_size;
  82         __hc32                  *periodic;      /* hw periodic table */
  83         dma_addr_t              periodic_dma;
  84         unsigned                i_thresh;       /* uframes HC might cache */
  85
  86         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  87         int                     next_uframe;    /* scan periodic, start here */
  88         unsigned                periodic_sched; /* periodic activity count */
  89
  90         /* list of itds completed while clock_frame was still active */
  91         struct list_head        cached_itd_list;
  92         unsigned                clock_frame;
  93
  94         /* per root hub port */
  95         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  96
  97         /* bit vectors (one bit per port) */
  98         unsigned long           bus_suspended;          /* which ports were
  99                         already suspended at the start of a bus suspend */
 100         unsigned long           companion_ports;        /* which ports are
 101                         dedicated to the companion controller */
 102         unsigned long           owned_ports;            /* which ports are
 103                         owned by the companion during a bus suspend */
 104         unsigned long           port_c_suspend;         /* which ports have
 105                         the change-suspend feature turned on */
 106         unsigned long           suspended_ports;        /* which ports are
 107                         suspended */
 108
 109         /* per-HC memory pools (could be per-bus, but ...) */
 110         struct dma_pool         *qh_pool;       /* qh per active urb */
 111         struct dma_pool         *qtd_pool;      /* one or more per qh */
 112         struct dma_pool         *itd_pool;      /* itd per iso urb */
 113         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 114
 115         struct timer_list       iaa_watchdog;
 116         struct timer_list       watchdog;
 117         unsigned long           actions;
 118         unsigned                stamp;
 119         unsigned                random_frame;
 120         unsigned long           next_statechange;
 121         u32                     command;
 122
 123         /* SILICON QUIRKS */
 124         unsigned                no_selective_suspend:1;
 125         unsigned                has_fsl_port_bug:1; /* FreeScale */
 126         unsigned                big_endian_mmio:1;
 127         unsigned                big_endian_desc:1;
 128         unsigned                has_amcc_usb23:1;
 129         unsigned                need_io_watchdog:1;
 130
 131         /* required for usb32 quirk */
 132         #define OHCI_CTRL_HCFS          (3 << 6)
 133         #define OHCI_USB_OPER           (2 << 6)
 134         #define OHCI_USB_SUSPEND        (3 << 6)
 135
 136         #define OHCI_HCCTRL_OFFSET      0x4
 137         #define OHCI_HCCTRL_LEN         0x4
 138         __hc32                  *ohci_hcctrl_reg;
 139         unsigned                has_hostpc:1;
 140
 141         u8                      sbrn;           /* packed release number */
 142
 143         /* irq statistics */
 144 #ifdef EHCI_STATS
 145         struct ehci_stats       stats;
 146 #       define COUNT(x) do { (x)++; } while (0)
 147 #else
 148 #       define COUNT(x) do {} while (0)
 149 #endif
 150
 151         /* debug files */
 152 #ifdef DEBUG
 153         struct dentry           *debug_dir;
 154         struct dentry           *debug_async;
 155         struct dentry           *debug_periodic;
 156         struct dentry           *debug_registers;
 157 #endif
 158 };
 159
 160 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 161 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 162 {
 163         return (struct ehci_hcd *) (hcd->hcd_priv);
 164 }
 165 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 166 {
 167         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 168 }
 169
 170
 171 static inline void
 172 iaa_watchdog_start(struct ehci_hcd *ehci)
 173 {
 174         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 175         mod_timer(&ehci->iaa_watchdog,
 176                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 177 }
 178
 179 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 180 {
 181         del_timer(&ehci->iaa_watchdog);
 182 }
 183
 184 enum ehci_timer_action {
 185         TIMER_IO_WATCHDOG,
 186         TIMER_ASYNC_SHRINK,
 187         TIMER_ASYNC_OFF,
 188 };
 189
 190 static inline void
 191 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 192 {
 193         clear_bit (action, &ehci->actions);
 194 }
 195
 196 static void free_cached_itd_list(struct ehci_hcd *ehci);
 197
 198 /*-------------------------------------------------------------------------*/
 199
 200 #include <linux/usb/ehci_def.h>
 201
 202 /*-------------------------------------------------------------------------*/
 203
 204 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 205
 206 /*
 207  * EHCI Specification 0.95 Section 3.5
 208  * QTD: describe data transfer components (buffer, direction, ...)
 209  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 210  *
 211  * These are associated only with "QH" (Queue Head) structures,
 212  * used with control, bulk, and interrupt transfers.
 213  */
 214 struct ehci_qtd {
 215         /* first part defined by EHCI spec */
 216         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 217         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 218         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 219 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 220 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 221 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 222 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 223 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 224 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 225 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 226 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 227 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 228 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 229 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 230 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 231 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 232
 233 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 234 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 235 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 236
 237         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 238         __hc32                  hw_buf_hi [5];        /* Appendix B */
 239
 240         /* the rest is HCD-private */
 241         dma_addr_t              qtd_dma;                /* qtd address */
 242         struct list_head        qtd_list;               /* sw qtd list */
 243         struct urb              *urb;                   /* qtd's urb */
 244         size_t                  length;                 /* length of buffer */
 245 } __attribute__ ((aligned (32)));
 246
 247 /* mask NakCnt+T in qh->hw_alt_next */
 248 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 249
 250 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 251
 252 /*-------------------------------------------------------------------------*/
 253
 254 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 255 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 256
 257 /*
 258  * Now the following defines are not converted using the
 259  * cpu_to_le32() macro anymore, since we have to support
 260  * "dynamic" switching between be and le support, so that the driver
 261  * can be used on one system with SoC EHCI controller using big-endian
 262  * descriptors as well as a normal little-endian PCI EHCI controller.
 263  */
 264 /* values for that type tag */
 265 #define Q_TYPE_ITD      (0 << 1)
 266 #define Q_TYPE_QH       (1 << 1)
 267 #define Q_TYPE_SITD     (2 << 1)
 268 #define Q_TYPE_FSTN     (3 << 1)
 269
 270 /* next async queue entry, or pointer to interrupt/periodic QH */
 271 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 272
 273 /* for periodic/async schedules and qtd lists, mark end of list */
 274 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 275
 276 /*
 277  * Entries in periodic shadow table are pointers to one of four kinds
 278  * of data structure.  That's dictated by the hardware; a type tag is
 279  * encoded in the low bits of the hardware's periodic schedule.  Use
 280  * Q_NEXT_TYPE to get the tag.
 281  *
 282  * For entries in the async schedule, the type tag always says "qh".
 283  */
 284 union ehci_shadow {
 285         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 286         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 287         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 288         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 289         __hc32                  *hw_next;       /* (all types) */
 290         void                    *ptr;
 291 };
 292
 293 /*-------------------------------------------------------------------------*/
 294
 295 /*
 296  * EHCI Specification 0.95 Section 3.6
 297  * QH: describes control/bulk/interrupt endpoints
 298  * See Fig 3-7 "Queue Head Structure Layout".
 299  *
 300  * These appear in both the async and (for interrupt) periodic schedules.
 301  */
 302
 303 /* first part defined by EHCI spec */
 304 struct ehci_qh_hw {
 305         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 306         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 307 #define QH_HEAD         0x00008000
 308         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 309 #define QH_SMASK        0x000000ff
 310 #define QH_CMASK        0x0000ff00
 311 #define QH_HUBADDR      0x007f0000
 312 #define QH_HUBPORT      0x3f800000
 313 #define QH_MULT         0xc0000000
 314         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 315
 316         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 317         __hc32                  hw_qtd_next;
 318         __hc32                  hw_alt_next;
 319         __hc32                  hw_token;
 320         __hc32                  hw_buf [5];
 321         __hc32                  hw_buf_hi [5];
 322 } __attribute__ ((aligned(32)));
 323
 324 struct ehci_qh {
 325         struct ehci_qh_hw       *hw;
 326         /* the rest is HCD-private */
 327         dma_addr_t              qh_dma;         /* address of qh */
 328         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 329         struct list_head        qtd_list;       /* sw qtd list */
 330         struct ehci_qtd         *dummy;
 331         struct ehci_qh          *reclaim;       /* next to reclaim */
 332
 333         struct ehci_hcd         *ehci;
 334
 335         /*
 336          * Do NOT use atomic operations for QH refcounting. On some CPUs
 337          * (PPC7448 for example), atomic operations cannot be performed on
 338          * memory that is cache-inhibited (i.e. being used for DMA).
 339          * Spinlocks are used to protect all QH fields.
 340          */
 341         u32                     refcount;
 342         unsigned                stamp;
 343
 344         u8                      needs_rescan;   /* Dequeue during giveback */
 345         u8                      qh_state;
 346 #define QH_STATE_LINKED         1               /* HC sees this */
 347 #define QH_STATE_UNLINK         2               /* HC may still see this */
 348 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 349 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 350 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 351
 352         u8                      xacterrs;       /* XactErr retry counter */
 353 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 354
 355         /* periodic schedule info */
 356         u8                      usecs;          /* intr bandwidth */
 357         u8                      gap_uf;         /* uframes split/csplit gap */
 358         u8                      c_usecs;        /* ... split completion bw */
 359         u16                     tt_usecs;       /* tt downstream bandwidth */
 360         unsigned short          period;         /* polling interval */
 361         unsigned short          start;          /* where polling starts */
 362 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 363
 364         struct usb_device       *dev;           /* access to TT */
 365         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 366 };
 367
 368 /*-------------------------------------------------------------------------*/
 369
 370 /* description of one iso transaction (up to 3 KB data if highspeed) */
 371 struct ehci_iso_packet {
 372         /* These will be copied to iTD when scheduling */
 373         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 374         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 375         u8                      cross;          /* buf crosses pages */
 376         /* for full speed OUT splits */
 377         u32                     buf1;
 378 };
 379
 380 /* temporary schedule data for packets from iso urbs (both speeds)
 381  * each packet is one logical usb transaction to the device (not TT),
 382  * beginning at stream->next_uframe
 383  */
 384 struct ehci_iso_sched {
 385         struct list_head        td_list;
 386         unsigned                span;
 387         struct ehci_iso_packet  packet [0];
 388 };
 389
 390 /*
 391  * ehci_iso_stream - groups all (s)itds for this endpoint.
 392  * acts like a qh would, if EHCI had them for ISO.
 393  */
 394 struct ehci_iso_stream {
 395         /* first two fields match QH, but info1 == 0 */
 396         __hc32                  hw_next;
 397         __hc32                  hw_info1;
 398
 399         u32                     refcount;
 400         u8                      bEndpointAddress;
 401         u8                      highspeed;
 402         u16                     depth;          /* depth in uframes */
 403         struct list_head        td_list;        /* queued itds/sitds */
 404         struct list_head        free_list;      /* list of unused itds/sitds */
 405         struct usb_device       *udev;
 406         struct usb_host_endpoint *ep;
 407
 408         /* output of (re)scheduling */
 409         unsigned long           start;          /* jiffies */
 410         unsigned long           rescheduled;
 411         int                     next_uframe;
 412         __hc32                  splits;
 413
 414         /* the rest is derived from the endpoint descriptor,
 415          * trusting urb->interval == f(epdesc->bInterval) and
 416          * including the extra info for hw_bufp[0..2]
 417          */
 418         u8                      usecs, c_usecs;
 419         u16                     interval;
 420         u16                     tt_usecs;
 421         u16                     maxp;
 422         u16                     raw_mask;
 423         unsigned                bandwidth;
 424
 425         /* This is used to initialize iTD's hw_bufp fields */
 426         __hc32                  buf0;
 427         __hc32                  buf1;
 428         __hc32                  buf2;
 429
 430         /* this is used to initialize sITD's tt info */
 431         __hc32                  address;
 432 };
 433
 434 /*-------------------------------------------------------------------------*/
 435
 436 /*
 437  * EHCI Specification 0.95 Section 3.3
 438  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 439  *
 440  * Schedule records for high speed iso xfers
 441  */
 442 struct ehci_itd {
 443         /* first part defined by EHCI spec */
 444         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 445         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 446 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 447 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 448 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 449 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 450 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 451 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 452
 453 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 454
 455         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 456         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 457
 458         /* the rest is HCD-private */
 459         dma_addr_t              itd_dma;        /* for this itd */
 460         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 461
 462         struct urb              *urb;
 463         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 464         struct list_head        itd_list;       /* list of stream's itds */
 465
 466         /* any/all hw_transactions here may be used by that urb */
 467         unsigned                frame;          /* where scheduled */
 468         unsigned                pg;
 469         unsigned                index[8];       /* in urb->iso_frame_desc */
 470 } __attribute__ ((aligned (32)));
 471
 472 /*-------------------------------------------------------------------------*/
 473
 474 /*
 475  * EHCI Specification 0.95 Section 3.4
 476  * siTD, aka split-transaction isochronous Transfer Descriptor
 477  *       ... describe full speed iso xfers through TT in hubs
 478  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 479  */
 480 struct ehci_sitd {
 481         /* first part defined by EHCI spec */
 482         __hc32                  hw_next;
 483 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 484         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 485         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 486         __hc32                  hw_results;             /* EHCI table 3-11 */
 487 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 488 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 489 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 490 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 491 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 492 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 493 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 494 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 495 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 496 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 497
 498 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 499
 500         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 501         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 502         __hc32                  hw_buf_hi [2];          /* Appendix B */
 503
 504         /* the rest is HCD-private */
 505         dma_addr_t              sitd_dma;
 506         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 507
 508         struct urb              *urb;
 509         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 510         struct list_head        sitd_list;      /* list of stream's sitds */
 511         unsigned                frame;
 512         unsigned                index;
 513 } __attribute__ ((aligned (32)));
 514
 515 /*-------------------------------------------------------------------------*/
 516
 517 /*
 518  * EHCI Specification 0.96 Section 3.7
 519  * Periodic Frame Span Traversal Node (FSTN)
 520  *
 521  * Manages split interrupt transactions (using TT) that span frame boundaries
 522  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 523  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 524  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 525  */
 526 struct ehci_fstn {
 527         __hc32                  hw_next;        /* any periodic q entry */
 528         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 529
 530         /* the rest is HCD-private */
 531         dma_addr_t              fstn_dma;
 532         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 533 } __attribute__ ((aligned (32)));
 534
 535 /*-------------------------------------------------------------------------*/
 536
 537 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 538
 539 /*
 540  * Some EHCI controllers have a Transaction Translator built into the
 541  * root hub. This is a non-standard feature.  Each controller will need
 542  * to add code to the following inline functions, and call them as
 543  * needed (mostly in root hub code).
 544  */
 545
 546 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 547
 548 /* Returns the speed of a device attached to a port on the root hub. */
 549 static inline unsigned int
 550 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 551 {
 552         if (ehci_is_TDI(ehci)) {
 553                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 554                 case 0:
 555                         return 0;
 556                 case 1:
 557                         return (1<<USB_PORT_FEAT_LOWSPEED);
 558                 case 2:
 559                 default:
 560                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 561                 }
 562         }
 563         return (1<<USB_PORT_FEAT_HIGHSPEED);
 564 }
 565
 566 #else
 567
 568 #define ehci_is_TDI(e)                  (0)
 569
 570 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 571 #endif
 572
 573 /*-------------------------------------------------------------------------*/
 574
 575 #ifdef CONFIG_PPC_83xx
 576 /* Some Freescale processors have an erratum in which the TT
 577  * port number in the queue head was 0..N-1 instead of 1..N.
 578  */
 579 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 580 #else
 581 #define ehci_has_fsl_portno_bug(e)              (0)
 582 #endif
 583
 584 /*
 585  * While most USB host controllers implement their registers in
 586  * little-endian format, a minority (celleb companion chip) implement
 587  * them in big endian format.
 588  *
 589  * This attempts to support either format at compile time without a
 590  * runtime penalty, or both formats with the additional overhead
 591  * of checking a flag bit.
 592  */
 593
 594 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 595 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 596 #else
 597 #define ehci_big_endian_mmio(e)         0
 598 #endif
 599
 600 /*
 601  * Big-endian read/write functions are arch-specific.
 602  * Other arches can be added if/when they're needed.
 603  */
 604 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 605 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 606 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 607 #endif
 608
 609 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 610                 __u32 __iomem * regs)
 611 {
 612 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 613         return ehci_big_endian_mmio(ehci) ?
 614                 readl_be(regs) :
 615                 readl(regs);
 616 #else
 617         return readl(regs);
 618 #endif
 619 }
 620
 621 static inline void ehci_writel(const struct ehci_hcd *ehci,
 622                 const unsigned int val, __u32 __iomem *regs)
 623 {
 624 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 625         ehci_big_endian_mmio(ehci) ?
 626                 writel_be(val, regs) :
 627                 writel(val, regs);
 628 #else
 629         writel(val, regs);
 630 #endif
 631 }
 632
 633 /*
 634  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 635  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 636  * Other common bits are dependant on has_amcc_usb23 quirk flag.
 637  */
 638 #ifdef CONFIG_44x
 639 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 640 {
 641         u32 hc_control;
 642
 643         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 644         if (operational)
 645                 hc_control |= OHCI_USB_OPER;
 646         else
 647                 hc_control |= OHCI_USB_SUSPEND;
 648
 649         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 650         (void) readl_be(ehci->ohci_hcctrl_reg);
 651 }
 652 #else
 653 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 654 { }
 655 #endif
 656
 657 /*-------------------------------------------------------------------------*/
 658
 659 /*
 660  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 661  * format, but also its DMA data structures (descriptors).
 662  *
 663  * EHCI controllers accessed through PCI work normally (little-endian
 664  * everywhere), so we won't bother supporting a BE-only mode for now.
 665  */
 666 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 667 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 668
 669 /* cpu to ehci */
 670 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 671 {
 672         return ehci_big_endian_desc(ehci)
 673                 ? (__force __hc32)cpu_to_be32(x)
 674                 : (__force __hc32)cpu_to_le32(x);
 675 }
 676
 677 /* ehci to cpu */
 678 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 679 {
 680         return ehci_big_endian_desc(ehci)
 681                 ? be32_to_cpu((__force __be32)x)
 682                 : le32_to_cpu((__force __le32)x);
 683 }
 684
 685 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 686 {
 687         return ehci_big_endian_desc(ehci)
 688                 ? be32_to_cpup((__force __be32 *)x)
 689                 : le32_to_cpup((__force __le32 *)x);
 690 }
 691
 692 #else
 693
 694 /* cpu to ehci */
 695 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 696 {
 697         return cpu_to_le32(x);
 698 }
 699
 700 /* ehci to cpu */
 701 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 702 {
 703         return le32_to_cpu(x);
 704 }
 705
 706 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 707 {
 708         return le32_to_cpup(x);
 709 }
 710
 711 #endif
 712
 713 /*-------------------------------------------------------------------------*/
 714
 715 #ifndef DEBUG
 716 #define STUB_DEBUG_FILES
 717 #endif  /* DEBUG */
 718
 719 /*-------------------------------------------------------------------------*/
 720
 721 #endif /* __LINUX_EHCI_HCD_H */