drivers/usb/host/pci-quirks.c

   1 /*
   2  * This file contains code to reset and initialize USB host controllers.
   3  * Some of it includes work-arounds for PCI hardware and BIOS quirks.
   4  * It may need to run early during booting -- before USB would normally
   5  * initialize -- to ensure that Linux doesn't use any legacy modes.
   6  *
   7  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
   8  *  (and others)
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/acpi.h>
  17 #include "pci-quirks.h"
  18 #include "xhci-ext-caps.h"
  19
  20
  21 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
  22 #define UHCI_USBCMD             0               /* command register */
  23 #define UHCI_USBINTR            4               /* interrupt register */
  24 #define UHCI_USBLEGSUP_RWC      0x8f00          /* the R/WC bits */
  25 #define UHCI_USBLEGSUP_RO       0x5040          /* R/O and reserved bits */
  26 #define UHCI_USBCMD_RUN         0x0001          /* RUN/STOP bit */
  27 #define UHCI_USBCMD_HCRESET     0x0002          /* Host Controller reset */
  28 #define UHCI_USBCMD_EGSM        0x0008          /* Global Suspend Mode */
  29 #define UHCI_USBCMD_CONFIGURE   0x0040          /* Config Flag */
  30 #define UHCI_USBINTR_RESUME     0x0002          /* Resume interrupt enable */
  31
  32 #define OHCI_CONTROL            0x04
  33 #define OHCI_CMDSTATUS          0x08
  34 #define OHCI_INTRSTATUS         0x0c
  35 #define OHCI_INTRENABLE         0x10
  36 #define OHCI_INTRDISABLE        0x14
  37 #define OHCI_OCR                (1 << 3)        /* ownership change request */
  38 #define OHCI_CTRL_RWC           (1 << 9)        /* remote wakeup connected */
  39 #define OHCI_CTRL_IR            (1 << 8)        /* interrupt routing */
  40 #define OHCI_INTR_OC            (1 << 30)       /* ownership change */
  41
  42 #define EHCI_HCC_PARAMS         0x08            /* extended capabilities */
  43 #define EHCI_USBCMD             0               /* command register */
  44 #define EHCI_USBCMD_RUN         (1 << 0)        /* RUN/STOP bit */
  45 #define EHCI_USBSTS             4               /* status register */
  46 #define EHCI_USBSTS_HALTED      (1 << 12)       /* HCHalted bit */
  47 #define EHCI_USBINTR            8               /* interrupt register */
  48 #define EHCI_CONFIGFLAG         0x40            /* configured flag register */
  49 #define EHCI_USBLEGSUP          0               /* legacy support register */
  50 #define EHCI_USBLEGSUP_BIOS     (1 << 16)       /* BIOS semaphore */
  51 #define EHCI_USBLEGSUP_OS       (1 << 24)       /* OS semaphore */
  52 #define EHCI_USBLEGCTLSTS       4               /* legacy control/status */
  53 #define EHCI_USBLEGCTLSTS_SOOE  (1 << 13)       /* SMI on ownership change */
  54
  55
  56 /*
  57  * Make sure the controller is completely inactive, unable to
  58  * generate interrupts or do DMA.
  59  */
  60 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
  61 {
  62         /* Turn off PIRQ enable and SMI enable.  (This also turns off the
  63          * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
  64          */
  65         pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
  66
  67         /* Reset the HC - this will force us to get a
  68          * new notification of any already connected
  69          * ports due to the virtual disconnect that it
  70          * implies.
  71          */
  72         outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
  73         mb();
  74         udelay(5);
  75         if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
  76                 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
  77
  78         /* Just to be safe, disable interrupt requests and
  79          * make sure the controller is stopped.
  80          */
  81         outw(0, base + UHCI_USBINTR);
  82         outw(0, base + UHCI_USBCMD);
  83 }
  84 EXPORT_SYMBOL_GPL(uhci_reset_hc);
  85
  86 /*
  87  * Initialize a controller that was newly discovered or has just been
  88  * resumed.  In either case we can't be sure of its previous state.
  89  *
  90  * Returns: 1 if the controller was reset, 0 otherwise.
  91  */
  92 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
  93 {
  94         u16 legsup;
  95         unsigned int cmd, intr;
  96
  97         /*
  98          * When restarting a suspended controller, we expect all the
  99          * settings to be the same as we left them:
 100          *
 101          *      PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
 102          *      Controller is stopped and configured with EGSM set;
 103          *      No interrupts enabled except possibly Resume Detect.
 104          *
 105          * If any of these conditions are violated we do a complete reset.
 106          */
 107         pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
 108         if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
 109                 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
 110                                 __func__, legsup);
 111                 goto reset_needed;
 112         }
 113
 114         cmd = inw(base + UHCI_USBCMD);
 115         if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
 116                         !(cmd & UHCI_USBCMD_EGSM)) {
 117                 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
 118                                 __func__, cmd);
 119                 goto reset_needed;
 120         }
 121
 122         intr = inw(base + UHCI_USBINTR);
 123         if (intr & (~UHCI_USBINTR_RESUME)) {
 124                 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
 125                                 __func__, intr);
 126                 goto reset_needed;
 127         }
 128         return 0;
 129
 130 reset_needed:
 131         dev_dbg(&pdev->dev, "Performing full reset\n");
 132         uhci_reset_hc(pdev, base);
 133         return 1;
 134 }
 135 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
 136
 137 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
 138 {
 139         u16 cmd;
 140         return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
 141 }
 142
 143 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
 144 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
 145
 146 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
 147 {
 148         unsigned long base = 0;
 149         int i;
 150
 151         if (!pio_enabled(pdev))
 152                 return;
 153
 154         for (i = 0; i < PCI_ROM_RESOURCE; i++)
 155                 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
 156                         base = pci_resource_start(pdev, i);
 157                         break;
 158                 }
 159
 160         if (base)
 161                 uhci_check_and_reset_hc(pdev, base);
 162 }
 163
 164 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
 165 {
 166         return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
 167 }
 168
 169 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
 170 {
 171         void __iomem *base;
 172
 173         if (!mmio_resource_enabled(pdev, 0))
 174                 return;
 175
 176         base = pci_ioremap_bar(pdev, 0);
 177         if (base == NULL)
 178                 return;
 179
 180 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
 181 #ifndef __hppa__
 182 {
 183         u32 control = readl(base + OHCI_CONTROL);
 184         if (control & OHCI_CTRL_IR) {
 185                 int wait_time = 500; /* arbitrary; 5 seconds */
 186                 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
 187                 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
 188                 while (wait_time > 0 &&
 189                                 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
 190                         wait_time -= 10;
 191                         msleep(10);
 192                 }
 193                 if (wait_time <= 0)
 194                         dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
 195                                         " (BIOS bug?) %08x\n",
 196                                         readl(base + OHCI_CONTROL));
 197
 198                 /* reset controller, preserving RWC */
 199                 writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL);
 200         }
 201 }
 202 #endif
 203
 204         /*
 205          * disable interrupts
 206          */
 207         writel(~(u32)0, base + OHCI_INTRDISABLE);
 208         writel(~(u32)0, base + OHCI_INTRSTATUS);
 209
 210         iounmap(base);
 211 }
 212
 213 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
 214 {
 215         int wait_time, delta;
 216         void __iomem *base, *op_reg_base;
 217         u32     hcc_params, val;
 218         u8      offset, cap_length;
 219         int     count = 256/4;
 220         int     tried_handoff = 0;
 221
 222         if (!mmio_resource_enabled(pdev, 0))
 223                 return;
 224
 225         base = pci_ioremap_bar(pdev, 0);
 226         if (base == NULL)
 227                 return;
 228
 229         cap_length = readb(base);
 230         op_reg_base = base + cap_length;
 231
 232         /* EHCI 0.96 and later may have "extended capabilities"
 233          * spec section 5.1 explains the bios handoff, e.g. for
 234          * booting from USB disk or using a usb keyboard
 235          */
 236         hcc_params = readl(base + EHCI_HCC_PARAMS);
 237         offset = (hcc_params >> 8) & 0xff;
 238         while (offset && --count) {
 239                 u32             cap;
 240                 int             msec;
 241
 242                 pci_read_config_dword(pdev, offset, &cap);
 243                 switch (cap & 0xff) {
 244                 case 1:                 /* BIOS/SMM/... handoff support */
 245                         if ((cap & EHCI_USBLEGSUP_BIOS)) {
 246                                 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
 247
 248 #if 0
 249 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
 250  * but that seems dubious in general (the BIOS left it off intentionally)
 251  * and is known to prevent some systems from booting.  so we won't do this
 252  * unless maybe we can determine when we're on a system that needs SMI forced.
 253  */
 254                                 /* BIOS workaround (?): be sure the
 255                                  * pre-Linux code receives the SMI
 256                                  */
 257                                 pci_read_config_dword(pdev,
 258                                                 offset + EHCI_USBLEGCTLSTS,
 259                                                 &val);
 260                                 pci_write_config_dword(pdev,
 261                                                 offset + EHCI_USBLEGCTLSTS,
 262                                                 val | EHCI_USBLEGCTLSTS_SOOE);
 263 #endif
 264
 265                                 /* some systems get upset if this semaphore is
 266                                  * set for any other reason than forcing a BIOS
 267                                  * handoff..
 268                                  */
 269                                 pci_write_config_byte(pdev, offset + 3, 1);
 270                         }
 271
 272                         /* if boot firmware now owns EHCI, spin till
 273                          * it hands it over.
 274                          */
 275                         msec = 1000;
 276                         while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
 277                                 tried_handoff = 1;
 278                                 msleep(10);
 279                                 msec -= 10;
 280                                 pci_read_config_dword(pdev, offset, &cap);
 281                         }
 282
 283                         if (cap & EHCI_USBLEGSUP_BIOS) {
 284                                 /* well, possibly buggy BIOS... try to shut
 285                                  * it down, and hope nothing goes too wrong
 286                                  */
 287                                 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
 288                                                 " (BIOS bug?) %08x\n", cap);
 289                                 pci_write_config_byte(pdev, offset + 2, 0);
 290                         }
 291
 292                         /* just in case, always disable EHCI SMIs */
 293                         pci_write_config_dword(pdev,
 294                                         offset + EHCI_USBLEGCTLSTS,
 295                                         0);
 296
 297                         /* If the BIOS ever owned the controller then we
 298                          * can't expect any power sessions to remain intact.
 299                          */
 300                         if (tried_handoff)
 301                                 writel(0, op_reg_base + EHCI_CONFIGFLAG);
 302                         break;
 303                 case 0:                 /* illegal reserved capability */
 304                         cap = 0;
 305                         /* FALLTHROUGH */
 306                 default:
 307                         dev_warn(&pdev->dev, "EHCI: unrecognized capability "
 308                                         "%02x\n", cap & 0xff);
 309                         break;
 310                 }
 311                 offset = (cap >> 8) & 0xff;
 312         }
 313         if (!count)
 314                 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
 315
 316         /*
 317          * halt EHCI & disable its interrupts in any case
 318          */
 319         val = readl(op_reg_base + EHCI_USBSTS);
 320         if ((val & EHCI_USBSTS_HALTED) == 0) {
 321                 val = readl(op_reg_base + EHCI_USBCMD);
 322                 val &= ~EHCI_USBCMD_RUN;
 323                 writel(val, op_reg_base + EHCI_USBCMD);
 324
 325                 wait_time = 2000;
 326                 delta = 100;
 327                 do {
 328                         writel(0x3f, op_reg_base + EHCI_USBSTS);
 329                         udelay(delta);
 330                         wait_time -= delta;
 331                         val = readl(op_reg_base + EHCI_USBSTS);
 332                         if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
 333                                 break;
 334                         }
 335                 } while (wait_time > 0);
 336         }
 337         writel(0, op_reg_base + EHCI_USBINTR);
 338         writel(0x3f, op_reg_base + EHCI_USBSTS);
 339
 340         iounmap(base);
 341
 342         return;
 343 }
 344
 345 /*
 346  * handshake - spin reading a register until handshake completes
 347  * @ptr: address of hc register to be read
 348  * @mask: bits to look at in result of read
 349  * @done: value of those bits when handshake succeeds
 350  * @wait_usec: timeout in microseconds
 351  * @delay_usec: delay in microseconds to wait between polling
 352  *
 353  * Polls a register every delay_usec microseconds.
 354  * Returns 0 when the mask bits have the value done.
 355  * Returns -ETIMEDOUT if this condition is not true after
 356  * wait_usec microseconds have passed.
 357  */
 358 static int handshake(void __iomem *ptr, u32 mask, u32 done,
 359                 int wait_usec, int delay_usec)
 360 {
 361         u32     result;
 362
 363         do {
 364                 result = readl(ptr);
 365                 result &= mask;
 366                 if (result == done)
 367                         return 0;
 368                 udelay(delay_usec);
 369                 wait_usec -= delay_usec;
 370         } while (wait_usec > 0);
 371         return -ETIMEDOUT;
 372 }
 373
 374 /**
 375  * PCI Quirks for xHCI.
 376  *
 377  * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
 378  * It signals to the BIOS that the OS wants control of the host controller,
 379  * and then waits 5 seconds for the BIOS to hand over control.
 380  * If we timeout, assume the BIOS is broken and take control anyway.
 381  */
 382 static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
 383 {
 384         void __iomem *base;
 385         int ext_cap_offset;
 386         void __iomem *op_reg_base;
 387         u32 val;
 388         int timeout;
 389
 390         if (!mmio_resource_enabled(pdev, 0))
 391                 return;
 392
 393         base = ioremap_nocache(pci_resource_start(pdev, 0),
 394                                 pci_resource_len(pdev, 0));
 395         if (base == NULL)
 396                 return;
 397
 398         /*
 399          * Find the Legacy Support Capability register -
 400          * this is optional for xHCI host controllers.
 401          */
 402         ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
 403         do {
 404                 if (!ext_cap_offset)
 405                         /* We've reached the end of the extended capabilities */
 406                         goto hc_init;
 407                 val = readl(base + ext_cap_offset);
 408                 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
 409                         break;
 410                 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
 411         } while (1);
 412
 413         /* If the BIOS owns the HC, signal that the OS wants it, and wait */
 414         if (val & XHCI_HC_BIOS_OWNED) {
 415                 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
 416
 417                 /* Wait for 5 seconds with 10 microsecond polling interval */
 418                 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
 419                                 0, 5000, 10);
 420
 421                 /* Assume a buggy BIOS and take HC ownership anyway */
 422                 if (timeout) {
 423                         dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
 424                                         " (BIOS bug ?) %08x\n", val);
 425                         writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
 426                 }
 427         }
 428
 429         /* Disable any BIOS SMIs */
 430         writel(XHCI_LEGACY_DISABLE_SMI,
 431                         base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 432
 433 hc_init:
 434         op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 435
 436         /* Wait for the host controller to be ready before writing any
 437          * operational or runtime registers.  Wait 5 seconds and no more.
 438          */
 439         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
 440                         5000, 10);
 441         /* Assume a buggy HC and start HC initialization anyway */
 442         if (timeout) {
 443                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 444                 dev_warn(&pdev->dev,
 445                                 "xHCI HW not ready after 5 sec (HC bug?) "
 446                                 "status = 0x%x\n", val);
 447         }
 448
 449         /* Send the halt and disable interrupts command */
 450         val = readl(op_reg_base + XHCI_CMD_OFFSET);
 451         val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
 452         writel(val, op_reg_base + XHCI_CMD_OFFSET);
 453
 454         /* Wait for the HC to halt - poll every 125 usec (one microframe). */
 455         timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
 456                         XHCI_MAX_HALT_USEC, 125);
 457         if (timeout) {
 458                 val = readl(op_reg_base + XHCI_STS_OFFSET);
 459                 dev_warn(&pdev->dev,
 460                                 "xHCI HW did not halt within %d usec "
 461                                 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
 462         }
 463
 464         iounmap(base);
 465 }
 466
 467 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 468 {
 469         if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
 470                 quirk_usb_handoff_uhci(pdev);
 471         else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
 472                 quirk_usb_handoff_ohci(pdev);
 473         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
 474                 quirk_usb_disable_ehci(pdev);
 475         else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
 476                 quirk_usb_handoff_xhci(pdev);
 477 }
 478 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);