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[TCP] slow start: Make comments and code logic clearer.
[linux-2.6/verdex.git] / drivers / ata / sata_nv.c
blob4cea3ef752264dd8fb6991ea1ddcf5e3ccc03bc6
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <scsi/scsi_device.h>
49 #include <linux/libata.h>
50
51 #define DRV_NAME "sata_nv"
52 #define DRV_VERSION "3.3"
53
54 #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
55
56 enum {
57 NV_MMIO_BAR = 5,
58
59 NV_PORTS = 2,
60 NV_PIO_MASK = 0x1f,
61 NV_MWDMA_MASK = 0x07,
62 NV_UDMA_MASK = 0x7f,
63 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
65
66 /* INT_STATUS/ENABLE */
67 NV_INT_STATUS = 0x10,
68 NV_INT_ENABLE = 0x11,
69 NV_INT_STATUS_CK804 = 0x440,
70 NV_INT_ENABLE_CK804 = 0x441,
71
72 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
80 NV_INT_ALL = 0x0f,
81 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
83
84 /* INT_CONFIG */
85 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
87
88 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
91 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
166 NV_ADMA_STAT_TIMEOUT,
167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
171
172 };
173
174 /* ADMA Physical Region Descriptor - one SG segment */
175 struct nv_adma_prd {
176 __le64 addr;
177 __le32 len;
178 u8 flags;
179 u8 packet_len;
180 __le16 reserved;
181 };
182
183 enum nv_adma_regbits {
184 CMDEND = (1 << 15), /* end of command list */
185 WNB = (1 << 14), /* wait-not-BSY */
186 IGN = (1 << 13), /* ignore this entry */
187 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
188 DA2 = (1 << (2 + 8)),
189 DA1 = (1 << (1 + 8)),
190 DA0 = (1 << (0 + 8)),
191 };
192
193 /* ADMA Command Parameter Block
194 The first 5 SG segments are stored inside the Command Parameter Block itself.
195 If there are more than 5 segments the remainder are stored in a separate
196 memory area indicated by next_aprd. */
197 struct nv_adma_cpb {
198 u8 resp_flags; /* 0 */
199 u8 reserved1; /* 1 */
200 u8 ctl_flags; /* 2 */
201 /* len is length of taskfile in 64 bit words */
202 u8 len; /* 3 */
203 u8 tag; /* 4 */
204 u8 next_cpb_idx; /* 5 */
205 __le16 reserved2; /* 6-7 */
206 __le16 tf[12]; /* 8-31 */
207 struct nv_adma_prd aprd[5]; /* 32-111 */
208 __le64 next_aprd; /* 112-119 */
209 __le64 reserved3; /* 120-127 */
210 };
211
212
213 struct nv_adma_port_priv {
214 struct nv_adma_cpb *cpb;
215 dma_addr_t cpb_dma;
216 struct nv_adma_prd *aprd;
217 dma_addr_t aprd_dma;
218 void __iomem * ctl_block;
219 void __iomem * gen_block;
220 void __iomem * notifier_clear_block;
221 u8 flags;
222 int last_issue_ncq;
223 };
224
225 struct nv_host_priv {
226 unsigned long type;
227 };
228
229 #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
230
231 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
232 static void nv_remove_one (struct pci_dev *pdev);
233 #ifdef CONFIG_PM
234 static int nv_pci_device_resume(struct pci_dev *pdev);
235 #endif
236 static void nv_ck804_host_stop(struct ata_host *host);
237 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
238 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
239 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
240 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
241 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
242
243 static void nv_nf2_freeze(struct ata_port *ap);
244 static void nv_nf2_thaw(struct ata_port *ap);
245 static void nv_ck804_freeze(struct ata_port *ap);
246 static void nv_ck804_thaw(struct ata_port *ap);
247 static void nv_error_handler(struct ata_port *ap);
248 static int nv_adma_slave_config(struct scsi_device *sdev);
249 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
250 static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
251 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
252 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
253 static void nv_adma_irq_clear(struct ata_port *ap);
254 static int nv_adma_port_start(struct ata_port *ap);
255 static void nv_adma_port_stop(struct ata_port *ap);
256 #ifdef CONFIG_PM
257 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
258 static int nv_adma_port_resume(struct ata_port *ap);
259 #endif
260 static void nv_adma_freeze(struct ata_port *ap);
261 static void nv_adma_thaw(struct ata_port *ap);
262 static void nv_adma_error_handler(struct ata_port *ap);
263 static void nv_adma_host_stop(struct ata_host *host);
264 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
265 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
266
267 enum nv_host_type
268 {
269 GENERIC,
270 NFORCE2,
271 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
272 CK804,
273 ADMA
274 };
275
276 static const struct pci_device_id nv_pci_tbl[] = {
277 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
278 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
279 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
286 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
287 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
288 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
289 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
290 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
291 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
292 PCI_ANY_ID, PCI_ANY_ID,
293 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
294 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
295 PCI_ANY_ID, PCI_ANY_ID,
296 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
297
298 { } /* terminate list */
299 };
300
301 static struct pci_driver nv_pci_driver = {
302 .name = DRV_NAME,
303 .id_table = nv_pci_tbl,
304 .probe = nv_init_one,
305 #ifdef CONFIG_PM
306 .suspend = ata_pci_device_suspend,
307 .resume = nv_pci_device_resume,
308 #endif
309 .remove = nv_remove_one,
310 };
311
312 static struct scsi_host_template nv_sht = {
313 .module = THIS_MODULE,
314 .name = DRV_NAME,
315 .ioctl = ata_scsi_ioctl,
316 .queuecommand = ata_scsi_queuecmd,
317 .can_queue = ATA_DEF_QUEUE,
318 .this_id = ATA_SHT_THIS_ID,
319 .sg_tablesize = LIBATA_MAX_PRD,
320 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
321 .emulated = ATA_SHT_EMULATED,
322 .use_clustering = ATA_SHT_USE_CLUSTERING,
323 .proc_name = DRV_NAME,
324 .dma_boundary = ATA_DMA_BOUNDARY,
325 .slave_configure = ata_scsi_slave_config,
326 .slave_destroy = ata_scsi_slave_destroy,
327 .bios_param = ata_std_bios_param,
328 };
329
330 static struct scsi_host_template nv_adma_sht = {
331 .module = THIS_MODULE,
332 .name = DRV_NAME,
333 .ioctl = ata_scsi_ioctl,
334 .queuecommand = ata_scsi_queuecmd,
335 .can_queue = NV_ADMA_MAX_CPBS,
336 .this_id = ATA_SHT_THIS_ID,
337 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
338 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
339 .emulated = ATA_SHT_EMULATED,
340 .use_clustering = ATA_SHT_USE_CLUSTERING,
341 .proc_name = DRV_NAME,
342 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
343 .slave_configure = nv_adma_slave_config,
344 .slave_destroy = ata_scsi_slave_destroy,
345 .bios_param = ata_std_bios_param,
346 };
347
348 static const struct ata_port_operations nv_generic_ops = {
349 .port_disable = ata_port_disable,
350 .tf_load = ata_tf_load,
351 .tf_read = ata_tf_read,
352 .exec_command = ata_exec_command,
353 .check_status = ata_check_status,
354 .dev_select = ata_std_dev_select,
355 .bmdma_setup = ata_bmdma_setup,
356 .bmdma_start = ata_bmdma_start,
357 .bmdma_stop = ata_bmdma_stop,
358 .bmdma_status = ata_bmdma_status,
359 .qc_prep = ata_qc_prep,
360 .qc_issue = ata_qc_issue_prot,
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
363 .error_handler = nv_error_handler,
364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
365 .data_xfer = ata_data_xfer,
366 .irq_clear = ata_bmdma_irq_clear,
367 .irq_on = ata_irq_on,
368 .irq_ack = ata_irq_ack,
369 .scr_read = nv_scr_read,
370 .scr_write = nv_scr_write,
371 .port_start = ata_port_start,
372 };
373
374 static const struct ata_port_operations nv_nf2_ops = {
375 .port_disable = ata_port_disable,
376 .tf_load = ata_tf_load,
377 .tf_read = ata_tf_read,
378 .exec_command = ata_exec_command,
379 .check_status = ata_check_status,
380 .dev_select = ata_std_dev_select,
381 .bmdma_setup = ata_bmdma_setup,
382 .bmdma_start = ata_bmdma_start,
383 .bmdma_stop = ata_bmdma_stop,
384 .bmdma_status = ata_bmdma_status,
385 .qc_prep = ata_qc_prep,
386 .qc_issue = ata_qc_issue_prot,
387 .freeze = nv_nf2_freeze,
388 .thaw = nv_nf2_thaw,
389 .error_handler = nv_error_handler,
390 .post_internal_cmd = ata_bmdma_post_internal_cmd,
391 .data_xfer = ata_data_xfer,
392 .irq_clear = ata_bmdma_irq_clear,
393 .irq_on = ata_irq_on,
394 .irq_ack = ata_irq_ack,
395 .scr_read = nv_scr_read,
396 .scr_write = nv_scr_write,
397 .port_start = ata_port_start,
398 };
399
400 static const struct ata_port_operations nv_ck804_ops = {
401 .port_disable = ata_port_disable,
402 .tf_load = ata_tf_load,
403 .tf_read = ata_tf_read,
404 .exec_command = ata_exec_command,
405 .check_status = ata_check_status,
406 .dev_select = ata_std_dev_select,
407 .bmdma_setup = ata_bmdma_setup,
408 .bmdma_start = ata_bmdma_start,
409 .bmdma_stop = ata_bmdma_stop,
410 .bmdma_status = ata_bmdma_status,
411 .qc_prep = ata_qc_prep,
412 .qc_issue = ata_qc_issue_prot,
413 .freeze = nv_ck804_freeze,
414 .thaw = nv_ck804_thaw,
415 .error_handler = nv_error_handler,
416 .post_internal_cmd = ata_bmdma_post_internal_cmd,
417 .data_xfer = ata_data_xfer,
418 .irq_clear = ata_bmdma_irq_clear,
419 .irq_on = ata_irq_on,
420 .irq_ack = ata_irq_ack,
421 .scr_read = nv_scr_read,
422 .scr_write = nv_scr_write,
423 .port_start = ata_port_start,
424 .host_stop = nv_ck804_host_stop,
425 };
426
427 static const struct ata_port_operations nv_adma_ops = {
428 .port_disable = ata_port_disable,
429 .tf_load = ata_tf_load,
430 .tf_read = nv_adma_tf_read,
431 .check_atapi_dma = nv_adma_check_atapi_dma,
432 .exec_command = ata_exec_command,
433 .check_status = ata_check_status,
434 .dev_select = ata_std_dev_select,
435 .bmdma_setup = ata_bmdma_setup,
436 .bmdma_start = ata_bmdma_start,
437 .bmdma_stop = ata_bmdma_stop,
438 .bmdma_status = ata_bmdma_status,
439 .qc_prep = nv_adma_qc_prep,
440 .qc_issue = nv_adma_qc_issue,
441 .freeze = nv_adma_freeze,
442 .thaw = nv_adma_thaw,
443 .error_handler = nv_adma_error_handler,
444 .post_internal_cmd = nv_adma_post_internal_cmd,
445 .data_xfer = ata_data_xfer,
446 .irq_clear = nv_adma_irq_clear,
447 .irq_on = ata_irq_on,
448 .irq_ack = ata_irq_ack,
449 .scr_read = nv_scr_read,
450 .scr_write = nv_scr_write,
451 .port_start = nv_adma_port_start,
452 .port_stop = nv_adma_port_stop,
453 #ifdef CONFIG_PM
454 .port_suspend = nv_adma_port_suspend,
455 .port_resume = nv_adma_port_resume,
456 #endif
457 .host_stop = nv_adma_host_stop,
458 };
459
460 static const struct ata_port_info nv_port_info[] = {
461 /* generic */
462 {
463 .sht = &nv_sht,
464 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
465 ATA_FLAG_HRST_TO_RESUME,
466 .pio_mask = NV_PIO_MASK,
467 .mwdma_mask = NV_MWDMA_MASK,
468 .udma_mask = NV_UDMA_MASK,
469 .port_ops = &nv_generic_ops,
470 .irq_handler = nv_generic_interrupt,
471 },
472 /* nforce2/3 */
473 {
474 .sht = &nv_sht,
475 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
476 ATA_FLAG_HRST_TO_RESUME,
477 .pio_mask = NV_PIO_MASK,
478 .mwdma_mask = NV_MWDMA_MASK,
479 .udma_mask = NV_UDMA_MASK,
480 .port_ops = &nv_nf2_ops,
481 .irq_handler = nv_nf2_interrupt,
482 },
483 /* ck804 */
484 {
485 .sht = &nv_sht,
486 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
487 ATA_FLAG_HRST_TO_RESUME,
488 .pio_mask = NV_PIO_MASK,
489 .mwdma_mask = NV_MWDMA_MASK,
490 .udma_mask = NV_UDMA_MASK,
491 .port_ops = &nv_ck804_ops,
492 .irq_handler = nv_ck804_interrupt,
493 },
494 /* ADMA */
495 {
496 .sht = &nv_adma_sht,
497 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
498 ATA_FLAG_HRST_TO_RESUME |
499 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
500 .pio_mask = NV_PIO_MASK,
501 .mwdma_mask = NV_MWDMA_MASK,
502 .udma_mask = NV_UDMA_MASK,
503 .port_ops = &nv_adma_ops,
504 .irq_handler = nv_adma_interrupt,
505 },
506 };
507
508 MODULE_AUTHOR("NVIDIA");
509 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
510 MODULE_LICENSE("GPL");
511 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
512 MODULE_VERSION(DRV_VERSION);
513
514 static int adma_enabled = 1;
515
516 static void nv_adma_register_mode(struct ata_port *ap)
517 {
518 struct nv_adma_port_priv *pp = ap->private_data;
519 void __iomem *mmio = pp->ctl_block;
520 u16 tmp, status;
521 int count = 0;
522
523 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
524 return;
525
526 status = readw(mmio + NV_ADMA_STAT);
527 while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
528 ndelay(50);
529 status = readw(mmio + NV_ADMA_STAT);
530 count++;
531 }
532 if(count == 20)
533 ata_port_printk(ap, KERN_WARNING,
534 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
535 status);
536
537 tmp = readw(mmio + NV_ADMA_CTL);
538 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
539
540 count = 0;
541 status = readw(mmio + NV_ADMA_STAT);
542 while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
543 ndelay(50);
544 status = readw(mmio + NV_ADMA_STAT);
545 count++;
546 }
547 if(count == 20)
548 ata_port_printk(ap, KERN_WARNING,
549 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
550 status);
551
552 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
553 }
554
555 static void nv_adma_mode(struct ata_port *ap)
556 {
557 struct nv_adma_port_priv *pp = ap->private_data;
558 void __iomem *mmio = pp->ctl_block;
559 u16 tmp, status;
560 int count = 0;
561
562 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
563 return;
564
565 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
566
567 tmp = readw(mmio + NV_ADMA_CTL);
568 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
569
570 status = readw(mmio + NV_ADMA_STAT);
571 while(((status & NV_ADMA_STAT_LEGACY) ||
572 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
573 ndelay(50);
574 status = readw(mmio + NV_ADMA_STAT);
575 count++;
576 }
577 if(count == 20)
578 ata_port_printk(ap, KERN_WARNING,
579 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
580 status);
581
582 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
583 }
584
585 static int nv_adma_slave_config(struct scsi_device *sdev)
586 {
587 struct ata_port *ap = ata_shost_to_port(sdev->host);
588 struct nv_adma_port_priv *pp = ap->private_data;
589 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
590 u64 bounce_limit;
591 unsigned long segment_boundary;
592 unsigned short sg_tablesize;
593 int rc;
594 int adma_enable;
595 u32 current_reg, new_reg, config_mask;
596
597 rc = ata_scsi_slave_config(sdev);
598
599 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
600 /* Not a proper libata device, ignore */
601 return rc;
602
603 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
604 /*
605 * NVIDIA reports that ADMA mode does not support ATAPI commands.
606 * Therefore ATAPI commands are sent through the legacy interface.
607 * However, the legacy interface only supports 32-bit DMA.
608 * Restrict DMA parameters as required by the legacy interface
609 * when an ATAPI device is connected.
610 */
611 bounce_limit = ATA_DMA_MASK;
612 segment_boundary = ATA_DMA_BOUNDARY;
613 /* Subtract 1 since an extra entry may be needed for padding, see
614 libata-scsi.c */
615 sg_tablesize = LIBATA_MAX_PRD - 1;
616
617 /* Since the legacy DMA engine is in use, we need to disable ADMA
618 on the port. */
619 adma_enable = 0;
620 nv_adma_register_mode(ap);
621 }
622 else {
623 bounce_limit = *ap->dev->dma_mask;
624 segment_boundary = NV_ADMA_DMA_BOUNDARY;
625 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
626 adma_enable = 1;
627 }
628
629 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
630
631 if(ap->port_no == 1)
632 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
633 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
634 else
635 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
636 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
637
638 if(adma_enable) {
639 new_reg = current_reg | config_mask;
640 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
641 }
642 else {
643 new_reg = current_reg & ~config_mask;
644 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
645 }
646
647 if(current_reg != new_reg)
648 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
649
650 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
651 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
652 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
653 ata_port_printk(ap, KERN_INFO,
654 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
655 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
656 return rc;
657 }
658
659 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
660 {
661 struct nv_adma_port_priv *pp = qc->ap->private_data;
662 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
663 }
664
665 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
666 {
667 /* Since commands where a result TF is requested are not
668 executed in ADMA mode, the only time this function will be called
669 in ADMA mode will be if a command fails. In this case we
670 don't care about going into register mode with ADMA commands
671 pending, as the commands will all shortly be aborted anyway. */
672 nv_adma_register_mode(ap);
673
674 ata_tf_read(ap, tf);
675 }
676
677 static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
678 {
679 unsigned int idx = 0;
680
681 if(tf->flags & ATA_TFLAG_ISADDR) {
682 if (tf->flags & ATA_TFLAG_LBA48) {
683 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
684 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
685 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
686 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
687 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
688 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
689 } else
690 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
691
692 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
693 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
694 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
695 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
696 }
697
698 if(tf->flags & ATA_TFLAG_DEVICE)
699 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
700
701 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
702
703 while(idx < 12)
704 cpb[idx++] = cpu_to_le16(IGN);
705
706 return idx;
707 }
708
709 static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
710 {
711 struct nv_adma_port_priv *pp = ap->private_data;
712 u8 flags = pp->cpb[cpb_num].resp_flags;
713
714 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
715
716 if (unlikely((force_err ||
717 flags & (NV_CPB_RESP_ATA_ERR |
718 NV_CPB_RESP_CMD_ERR |
719 NV_CPB_RESP_CPB_ERR)))) {
720 struct ata_eh_info *ehi = &ap->eh_info;
721 int freeze = 0;
722
723 ata_ehi_clear_desc(ehi);
724 ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x", flags );
725 if (flags & NV_CPB_RESP_ATA_ERR) {
726 ata_ehi_push_desc(ehi, ": ATA error");
727 ehi->err_mask |= AC_ERR_DEV;
728 } else if (flags & NV_CPB_RESP_CMD_ERR) {
729 ata_ehi_push_desc(ehi, ": CMD error");
730 ehi->err_mask |= AC_ERR_DEV;
731 } else if (flags & NV_CPB_RESP_CPB_ERR) {
732 ata_ehi_push_desc(ehi, ": CPB error");
733 ehi->err_mask |= AC_ERR_SYSTEM;
734 freeze = 1;
735 } else {
736 /* notifier error, but no error in CPB flags? */
737 ehi->err_mask |= AC_ERR_OTHER;
738 freeze = 1;
739 }
740 /* Kill all commands. EH will determine what actually failed. */
741 if (freeze)
742 ata_port_freeze(ap);
743 else
744 ata_port_abort(ap);
745 return 1;
746 }
747
748 if (likely(flags & NV_CPB_RESP_DONE)) {
749 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
750 VPRINTK("CPB flags done, flags=0x%x\n", flags);
751 if (likely(qc)) {
752 DPRINTK("Completing qc from tag %d\n",cpb_num);
753 ata_qc_complete(qc);
754 } else {
755 struct ata_eh_info *ehi = &ap->eh_info;
756 /* Notifier bits set without a command may indicate the drive
757 is misbehaving. Raise host state machine violation on this
758 condition. */
759 ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n",
760 cpb_num);
761 ehi->err_mask |= AC_ERR_HSM;
762 ehi->action |= ATA_EH_SOFTRESET;
763 ata_port_freeze(ap);
764 return 1;
765 }
766 }
767 return 0;
768 }
769
770 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
771 {
772 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
773
774 /* freeze if hotplugged */
775 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
776 ata_port_freeze(ap);
777 return 1;
778 }
779
780 /* bail out if not our interrupt */
781 if (!(irq_stat & NV_INT_DEV))
782 return 0;
783
784 /* DEV interrupt w/ no active qc? */
785 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
786 ata_check_status(ap);
787 return 1;
788 }
789
790 /* handle interrupt */
791 return ata_host_intr(ap, qc);
792 }
793
794 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
795 {
796 struct ata_host *host = dev_instance;
797 int i, handled = 0;
798 u32 notifier_clears[2];
799
800 spin_lock(&host->lock);
801
802 for (i = 0; i < host->n_ports; i++) {
803 struct ata_port *ap = host->ports[i];
804 notifier_clears[i] = 0;
805
806 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
807 struct nv_adma_port_priv *pp = ap->private_data;
808 void __iomem *mmio = pp->ctl_block;
809 u16 status;
810 u32 gen_ctl;
811 u32 notifier, notifier_error;
812
813 /* if ADMA is disabled, use standard ata interrupt handler */
814 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
815 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
816 >> (NV_INT_PORT_SHIFT * i);
817 handled += nv_host_intr(ap, irq_stat);
818 continue;
819 }
820
821 /* if in ATA register mode, check for standard interrupts */
822 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
823 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
824 >> (NV_INT_PORT_SHIFT * i);
825 if(ata_tag_valid(ap->active_tag))
826 /** NV_INT_DEV indication seems unreliable at times
827 at least in ADMA mode. Force it on always when a
828 command is active, to prevent losing interrupts. */
829 irq_stat |= NV_INT_DEV;
830 handled += nv_host_intr(ap, irq_stat);
831 }
832
833 notifier = readl(mmio + NV_ADMA_NOTIFIER);
834 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
835 notifier_clears[i] = notifier | notifier_error;
836
837 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
838
839 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
840 !notifier_error)
841 /* Nothing to do */
842 continue;
843
844 status = readw(mmio + NV_ADMA_STAT);
845
846 /* Clear status. Ensure the controller sees the clearing before we start
847 looking at any of the CPB statuses, so that any CPB completions after
848 this point in the handler will raise another interrupt. */
849 writew(status, mmio + NV_ADMA_STAT);
850 readw(mmio + NV_ADMA_STAT); /* flush posted write */
851 rmb();
852
853 handled++; /* irq handled if we got here */
854
855 /* freeze if hotplugged or controller error */
856 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
857 NV_ADMA_STAT_HOTUNPLUG |
858 NV_ADMA_STAT_TIMEOUT |
859 NV_ADMA_STAT_SERROR))) {
860 struct ata_eh_info *ehi = &ap->eh_info;
861
862 ata_ehi_clear_desc(ehi);
863 ata_ehi_push_desc(ehi, "ADMA status 0x%08x", status );
864 if (status & NV_ADMA_STAT_TIMEOUT) {
865 ehi->err_mask |= AC_ERR_SYSTEM;
866 ata_ehi_push_desc(ehi, ": timeout");
867 } else if (status & NV_ADMA_STAT_HOTPLUG) {
868 ata_ehi_hotplugged(ehi);
869 ata_ehi_push_desc(ehi, ": hotplug");
870 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
871 ata_ehi_hotplugged(ehi);
872 ata_ehi_push_desc(ehi, ": hot unplug");
873 } else if (status & NV_ADMA_STAT_SERROR) {
874 /* let libata analyze SError and figure out the cause */
875 ata_ehi_push_desc(ehi, ": SError");
876 }
877 ata_port_freeze(ap);
878 continue;
879 }
880
881 if (status & (NV_ADMA_STAT_DONE |
882 NV_ADMA_STAT_CPBERR)) {
883 u32 check_commands;
884 int pos, error = 0;
885
886 if(ata_tag_valid(ap->active_tag))
887 check_commands = 1 << ap->active_tag;
888 else
889 check_commands = ap->sactive;
890
891 /** Check CPBs for completed commands */
892 while ((pos = ffs(check_commands)) && !error) {
893 pos--;
894 error = nv_adma_check_cpb(ap, pos,
895 notifier_error & (1 << pos) );
896 check_commands &= ~(1 << pos );
897 }
898 }
899 }
900 }
901
902 if(notifier_clears[0] || notifier_clears[1]) {
903 /* Note: Both notifier clear registers must be written
904 if either is set, even if one is zero, according to NVIDIA. */
905 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
906 writel(notifier_clears[0], pp->notifier_clear_block);
907 pp = host->ports[1]->private_data;
908 writel(notifier_clears[1], pp->notifier_clear_block);
909 }
910
911 spin_unlock(&host->lock);
912
913 return IRQ_RETVAL(handled);
914 }
915
916 static void nv_adma_freeze(struct ata_port *ap)
917 {
918 struct nv_adma_port_priv *pp = ap->private_data;
919 void __iomem *mmio = pp->ctl_block;
920 u16 tmp;
921
922 nv_ck804_freeze(ap);
923
924 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
925 return;
926
927 /* clear any outstanding CK804 notifications */
928 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
929 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
930
931 /* Disable interrupt */
932 tmp = readw(mmio + NV_ADMA_CTL);
933 writew( tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
934 mmio + NV_ADMA_CTL);
935 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
936 }
937
938 static void nv_adma_thaw(struct ata_port *ap)
939 {
940 struct nv_adma_port_priv *pp = ap->private_data;
941 void __iomem *mmio = pp->ctl_block;
942 u16 tmp;
943
944 nv_ck804_thaw(ap);
945
946 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
947 return;
948
949 /* Enable interrupt */
950 tmp = readw(mmio + NV_ADMA_CTL);
951 writew( tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
952 mmio + NV_ADMA_CTL);
953 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
954 }
955
956 static void nv_adma_irq_clear(struct ata_port *ap)
957 {
958 struct nv_adma_port_priv *pp = ap->private_data;
959 void __iomem *mmio = pp->ctl_block;
960 u32 notifier_clears[2];
961
962 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
963 ata_bmdma_irq_clear(ap);
964 return;
965 }
966
967 /* clear any outstanding CK804 notifications */
968 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
969 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
970
971 /* clear ADMA status */
972 writew(0xffff, mmio + NV_ADMA_STAT);
973
974 /* clear notifiers - note both ports need to be written with
975 something even though we are only clearing on one */
976 if (ap->port_no == 0) {
977 notifier_clears[0] = 0xFFFFFFFF;
978 notifier_clears[1] = 0;
979 } else {
980 notifier_clears[0] = 0;
981 notifier_clears[1] = 0xFFFFFFFF;
982 }
983 pp = ap->host->ports[0]->private_data;
984 writel(notifier_clears[0], pp->notifier_clear_block);
985 pp = ap->host->ports[1]->private_data;
986 writel(notifier_clears[1], pp->notifier_clear_block);
987 }
988
989 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
990 {
991 struct nv_adma_port_priv *pp = qc->ap->private_data;
992
993 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE)
994 ata_bmdma_post_internal_cmd(qc);
995 }
996
997 static int nv_adma_port_start(struct ata_port *ap)
998 {
999 struct device *dev = ap->host->dev;
1000 struct nv_adma_port_priv *pp;
1001 int rc;
1002 void *mem;
1003 dma_addr_t mem_dma;
1004 void __iomem *mmio;
1005 u16 tmp;
1006
1007 VPRINTK("ENTER\n");
1008
1009 rc = ata_port_start(ap);
1010 if (rc)
1011 return rc;
1012
1013 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1014 if (!pp)
1015 return -ENOMEM;
1016
1017 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
1018 ap->port_no * NV_ADMA_PORT_SIZE;
1019 pp->ctl_block = mmio;
1020 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1021 pp->notifier_clear_block = pp->gen_block +
1022 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1023
1024 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1025 &mem_dma, GFP_KERNEL);
1026 if (!mem)
1027 return -ENOMEM;
1028 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1029
1030 /*
1031 * First item in chunk of DMA memory:
1032 * 128-byte command parameter block (CPB)
1033 * one for each command tag
1034 */
1035 pp->cpb = mem;
1036 pp->cpb_dma = mem_dma;
1037
1038 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1039 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1040
1041 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1042 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1043
1044 /*
1045 * Second item: block of ADMA_SGTBL_LEN s/g entries
1046 */
1047 pp->aprd = mem;
1048 pp->aprd_dma = mem_dma;
1049
1050 ap->private_data = pp;
1051
1052 /* clear any outstanding interrupt conditions */
1053 writew(0xffff, mmio + NV_ADMA_STAT);
1054
1055 /* initialize port variables */
1056 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1057
1058 /* clear CPB fetch count */
1059 writew(0, mmio + NV_ADMA_CPB_COUNT);
1060
1061 /* clear GO for register mode, enable interrupt */
1062 tmp = readw(mmio + NV_ADMA_CTL);
1063 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1064 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1065
1066 tmp = readw(mmio + NV_ADMA_CTL);
1067 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1068 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1069 udelay(1);
1070 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1071 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1072
1073 return 0;
1074 }
1075
1076 static void nv_adma_port_stop(struct ata_port *ap)
1077 {
1078 struct nv_adma_port_priv *pp = ap->private_data;
1079 void __iomem *mmio = pp->ctl_block;
1080
1081 VPRINTK("ENTER\n");
1082 writew(0, mmio + NV_ADMA_CTL);
1083 }
1084
1085 #ifdef CONFIG_PM
1086 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1087 {
1088 struct nv_adma_port_priv *pp = ap->private_data;
1089 void __iomem *mmio = pp->ctl_block;
1090
1091 /* Go to register mode - clears GO */
1092 nv_adma_register_mode(ap);
1093
1094 /* clear CPB fetch count */
1095 writew(0, mmio + NV_ADMA_CPB_COUNT);
1096
1097 /* disable interrupt, shut down port */
1098 writew(0, mmio + NV_ADMA_CTL);
1099
1100 return 0;
1101 }
1102
1103 static int nv_adma_port_resume(struct ata_port *ap)
1104 {
1105 struct nv_adma_port_priv *pp = ap->private_data;
1106 void __iomem *mmio = pp->ctl_block;
1107 u16 tmp;
1108
1109 /* set CPB block location */
1110 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1111 writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1112
1113 /* clear any outstanding interrupt conditions */
1114 writew(0xffff, mmio + NV_ADMA_STAT);
1115
1116 /* initialize port variables */
1117 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1118
1119 /* clear CPB fetch count */
1120 writew(0, mmio + NV_ADMA_CPB_COUNT);
1121
1122 /* clear GO for register mode, enable interrupt */
1123 tmp = readw(mmio + NV_ADMA_CTL);
1124 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1125 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1126
1127 tmp = readw(mmio + NV_ADMA_CTL);
1128 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1129 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1130 udelay(1);
1131 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1132 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1133
1134 return 0;
1135 }
1136 #endif
1137
1138 static void nv_adma_setup_port(struct ata_port *ap)
1139 {
1140 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1141 struct ata_ioports *ioport = &ap->ioaddr;
1142
1143 VPRINTK("ENTER\n");
1144
1145 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1146
1147 ioport->cmd_addr = mmio;
1148 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
1149 ioport->error_addr =
1150 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1151 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1152 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1153 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1154 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1155 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
1156 ioport->status_addr =
1157 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
1158 ioport->altstatus_addr =
1159 ioport->ctl_addr = mmio + 0x20;
1160 }
1161
1162 static int nv_adma_host_init(struct ata_host *host)
1163 {
1164 struct pci_dev *pdev = to_pci_dev(host->dev);
1165 unsigned int i;
1166 u32 tmp32;
1167
1168 VPRINTK("ENTER\n");
1169
1170 /* enable ADMA on the ports */
1171 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1172 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1173 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1174 NV_MCP_SATA_CFG_20_PORT1_EN |
1175 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1176
1177 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1178
1179 for (i = 0; i < host->n_ports; i++)
1180 nv_adma_setup_port(host->ports[i]);
1181
1182 return 0;
1183 }
1184
1185 static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1186 struct scatterlist *sg,
1187 int idx,
1188 struct nv_adma_prd *aprd)
1189 {
1190 u8 flags = 0;
1191 if (qc->tf.flags & ATA_TFLAG_WRITE)
1192 flags |= NV_APRD_WRITE;
1193 if (idx == qc->n_elem - 1)
1194 flags |= NV_APRD_END;
1195 else if (idx != 4)
1196 flags |= NV_APRD_CONT;
1197
1198 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1199 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1200 aprd->flags = flags;
1201 aprd->packet_len = 0;
1202 }
1203
1204 static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1205 {
1206 struct nv_adma_port_priv *pp = qc->ap->private_data;
1207 unsigned int idx;
1208 struct nv_adma_prd *aprd;
1209 struct scatterlist *sg;
1210
1211 VPRINTK("ENTER\n");
1212
1213 idx = 0;
1214
1215 ata_for_each_sg(sg, qc) {
1216 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1217 nv_adma_fill_aprd(qc, sg, idx, aprd);
1218 idx++;
1219 }
1220 if (idx > 5)
1221 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1222 else
1223 cpb->next_aprd = cpu_to_le64(0);
1224 }
1225
1226 static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1227 {
1228 struct nv_adma_port_priv *pp = qc->ap->private_data;
1229
1230 /* ADMA engine can only be used for non-ATAPI DMA commands,
1231 or interrupt-driven no-data commands, where a result taskfile
1232 is not required. */
1233 if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1234 (qc->tf.flags & ATA_TFLAG_POLLING) ||
1235 (qc->flags & ATA_QCFLAG_RESULT_TF))
1236 return 1;
1237
1238 if((qc->flags & ATA_QCFLAG_DMAMAP) ||
1239 (qc->tf.protocol == ATA_PROT_NODATA))
1240 return 0;
1241
1242 return 1;
1243 }
1244
1245 static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1246 {
1247 struct nv_adma_port_priv *pp = qc->ap->private_data;
1248 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1249 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1250 NV_CPB_CTL_IEN;
1251
1252 if (nv_adma_use_reg_mode(qc)) {
1253 nv_adma_register_mode(qc->ap);
1254 ata_qc_prep(qc);
1255 return;
1256 }
1257
1258 cpb->resp_flags = NV_CPB_RESP_DONE;
1259 wmb();
1260 cpb->ctl_flags = 0;
1261 wmb();
1262
1263 cpb->len = 3;
1264 cpb->tag = qc->tag;
1265 cpb->next_cpb_idx = 0;
1266
1267 /* turn on NCQ flags for NCQ commands */
1268 if (qc->tf.protocol == ATA_PROT_NCQ)
1269 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1270
1271 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1272
1273 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1274
1275 if(qc->flags & ATA_QCFLAG_DMAMAP) {
1276 nv_adma_fill_sg(qc, cpb);
1277 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1278 } else
1279 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
1280
1281 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1282 finished filling in all of the contents */
1283 wmb();
1284 cpb->ctl_flags = ctl_flags;
1285 wmb();
1286 cpb->resp_flags = 0;
1287 }
1288
1289 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1290 {
1291 struct nv_adma_port_priv *pp = qc->ap->private_data;
1292 void __iomem *mmio = pp->ctl_block;
1293 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
1294
1295 VPRINTK("ENTER\n");
1296
1297 if (nv_adma_use_reg_mode(qc)) {
1298 /* use ATA register mode */
1299 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
1300 nv_adma_register_mode(qc->ap);
1301 return ata_qc_issue_prot(qc);
1302 } else
1303 nv_adma_mode(qc->ap);
1304
1305 /* write append register, command tag in lower 8 bits
1306 and (number of cpbs to append -1) in top 8 bits */
1307 wmb();
1308
1309 if(curr_ncq != pp->last_issue_ncq) {
1310 /* Seems to need some delay before switching between NCQ and non-NCQ
1311 commands, else we get command timeouts and such. */
1312 udelay(20);
1313 pp->last_issue_ncq = curr_ncq;
1314 }
1315
1316 writew(qc->tag, mmio + NV_ADMA_APPEND);
1317
1318 DPRINTK("Issued tag %u\n",qc->tag);
1319
1320 return 0;
1321 }
1322
1323 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1324 {
1325 struct ata_host *host = dev_instance;
1326 unsigned int i;
1327 unsigned int handled = 0;
1328 unsigned long flags;
1329
1330 spin_lock_irqsave(&host->lock, flags);
1331
1332 for (i = 0; i < host->n_ports; i++) {
1333 struct ata_port *ap;
1334
1335 ap = host->ports[i];
1336 if (ap &&
1337 !(ap->flags & ATA_FLAG_DISABLED)) {
1338 struct ata_queued_cmd *qc;
1339
1340 qc = ata_qc_from_tag(ap, ap->active_tag);
1341 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1342 handled += ata_host_intr(ap, qc);
1343 else
1344 // No request pending? Clear interrupt status
1345 // anyway, in case there's one pending.
1346 ap->ops->check_status(ap);
1347 }
1348
1349 }
1350
1351 spin_unlock_irqrestore(&host->lock, flags);
1352
1353 return IRQ_RETVAL(handled);
1354 }
1355
1356 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
1357 {
1358 int i, handled = 0;
1359
1360 for (i = 0; i < host->n_ports; i++) {
1361 struct ata_port *ap = host->ports[i];
1362
1363 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1364 handled += nv_host_intr(ap, irq_stat);
1365
1366 irq_stat >>= NV_INT_PORT_SHIFT;
1367 }
1368
1369 return IRQ_RETVAL(handled);
1370 }
1371
1372 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
1373 {
1374 struct ata_host *host = dev_instance;
1375 u8 irq_stat;
1376 irqreturn_t ret;
1377
1378 spin_lock(&host->lock);
1379 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
1380 ret = nv_do_interrupt(host, irq_stat);
1381 spin_unlock(&host->lock);
1382
1383 return ret;
1384 }
1385
1386 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
1387 {
1388 struct ata_host *host = dev_instance;
1389 u8 irq_stat;
1390 irqreturn_t ret;
1391
1392 spin_lock(&host->lock);
1393 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1394 ret = nv_do_interrupt(host, irq_stat);
1395 spin_unlock(&host->lock);
1396
1397 return ret;
1398 }
1399
1400 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1401 {
1402 if (sc_reg > SCR_CONTROL)
1403 return 0xffffffffU;
1404
1405 return ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
1406 }
1407
1408 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1409 {
1410 if (sc_reg > SCR_CONTROL)
1411 return;
1412
1413 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1414 }
1415
1416 static void nv_nf2_freeze(struct ata_port *ap)
1417 {
1418 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1419 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1420 u8 mask;
1421
1422 mask = ioread8(scr_addr + NV_INT_ENABLE);
1423 mask &= ~(NV_INT_ALL << shift);
1424 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1425 }
1426
1427 static void nv_nf2_thaw(struct ata_port *ap)
1428 {
1429 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1430 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1431 u8 mask;
1432
1433 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
1434
1435 mask = ioread8(scr_addr + NV_INT_ENABLE);
1436 mask |= (NV_INT_MASK << shift);
1437 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1438 }
1439
1440 static void nv_ck804_freeze(struct ata_port *ap)
1441 {
1442 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1443 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1444 u8 mask;
1445
1446 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1447 mask &= ~(NV_INT_ALL << shift);
1448 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1449 }
1450
1451 static void nv_ck804_thaw(struct ata_port *ap)
1452 {
1453 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1454 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1455 u8 mask;
1456
1457 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1458
1459 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1460 mask |= (NV_INT_MASK << shift);
1461 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1462 }
1463
1464 static int nv_hardreset(struct ata_port *ap, unsigned int *class,
1465 unsigned long deadline)
1466 {
1467 unsigned int dummy;
1468
1469 /* SATA hardreset fails to retrieve proper device signature on
1470 * some controllers. Don't classify on hardreset. For more
1471 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1472 */
1473 return sata_std_hardreset(ap, &dummy, deadline);
1474 }
1475
1476 static void nv_error_handler(struct ata_port *ap)
1477 {
1478 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1479 nv_hardreset, ata_std_postreset);
1480 }
1481
1482 static void nv_adma_error_handler(struct ata_port *ap)
1483 {
1484 struct nv_adma_port_priv *pp = ap->private_data;
1485 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1486 void __iomem *mmio = pp->ctl_block;
1487 int i;
1488 u16 tmp;
1489
1490 if(ata_tag_valid(ap->active_tag) || ap->sactive) {
1491 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1492 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1493 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1494 u32 status = readw(mmio + NV_ADMA_STAT);
1495 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1496 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
1497
1498 ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
1499 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1500 "next cpb count 0x%X next cpb idx 0x%x\n",
1501 notifier, notifier_error, gen_ctl, status,
1502 cpb_count, next_cpb_idx);
1503
1504 for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
1505 struct nv_adma_cpb *cpb = &pp->cpb[i];
1506 if( (ata_tag_valid(ap->active_tag) && i == ap->active_tag) ||
1507 ap->sactive & (1 << i) )
1508 ata_port_printk(ap, KERN_ERR,
1509 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1510 i, cpb->ctl_flags, cpb->resp_flags);
1511 }
1512 }
1513
1514 /* Push us back into port register mode for error handling. */
1515 nv_adma_register_mode(ap);
1516
1517 /* Mark all of the CPBs as invalid to prevent them from being executed */
1518 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1519 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1520
1521 /* clear CPB fetch count */
1522 writew(0, mmio + NV_ADMA_CPB_COUNT);
1523
1524 /* Reset channel */
1525 tmp = readw(mmio + NV_ADMA_CTL);
1526 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1527 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1528 udelay(1);
1529 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1530 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1531 }
1532
1533 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1534 nv_hardreset, ata_std_postreset);
1535 }
1536
1537 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1538 {
1539 static int printed_version = 0;
1540 const struct ata_port_info *ppi[] = { NULL, NULL };
1541 struct ata_host *host;
1542 struct nv_host_priv *hpriv;
1543 int rc;
1544 u32 bar;
1545 void __iomem *base;
1546 unsigned long type = ent->driver_data;
1547
1548 // Make sure this is a SATA controller by counting the number of bars
1549 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1550 // it's an IDE controller and we ignore it.
1551 for (bar=0; bar<6; bar++)
1552 if (pci_resource_start(pdev, bar) == 0)
1553 return -ENODEV;
1554
1555 if (!printed_version++)
1556 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1557
1558 rc = pcim_enable_device(pdev);
1559 if (rc)
1560 return rc;
1561
1562 /* determine type and allocate host */
1563 if (type >= CK804 && adma_enabled) {
1564 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1565 type = ADMA;
1566 }
1567
1568 ppi[0] = &nv_port_info[type];
1569 rc = ata_pci_prepare_native_host(pdev, ppi, &host);
1570 if (rc)
1571 return rc;
1572
1573 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1574 if (!hpriv)
1575 return -ENOMEM;
1576 hpriv->type = type;
1577 host->private_data = hpriv;
1578
1579 /* set 64bit dma masks, may fail */
1580 if (type == ADMA) {
1581 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
1582 pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1583 }
1584
1585 /* request and iomap NV_MMIO_BAR */
1586 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
1587 if (rc)
1588 return rc;
1589
1590 /* configure SCR access */
1591 base = host->iomap[NV_MMIO_BAR];
1592 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1593 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1594
1595 /* enable SATA space for CK804 */
1596 if (type >= CK804) {
1597 u8 regval;
1598
1599 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1600 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1601 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1602 }
1603
1604 /* init ADMA */
1605 if (type == ADMA) {
1606 rc = nv_adma_host_init(host);
1607 if (rc)
1608 return rc;
1609 }
1610
1611 pci_set_master(pdev);
1612 return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
1613 IRQF_SHARED, ppi[0]->sht);
1614 }
1615
1616 static void nv_remove_one (struct pci_dev *pdev)
1617 {
1618 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1619 struct nv_host_priv *hpriv = host->private_data;
1620
1621 ata_pci_remove_one(pdev);
1622 kfree(hpriv);
1623 }
1624
1625 #ifdef CONFIG_PM
1626 static int nv_pci_device_resume(struct pci_dev *pdev)
1627 {
1628 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1629 struct nv_host_priv *hpriv = host->private_data;
1630 int rc;
1631
1632 rc = ata_pci_device_do_resume(pdev);
1633 if(rc)
1634 return rc;
1635
1636 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1637 if(hpriv->type >= CK804) {
1638 u8 regval;
1639
1640 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1641 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1642 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1643 }
1644 if(hpriv->type == ADMA) {
1645 u32 tmp32;
1646 struct nv_adma_port_priv *pp;
1647 /* enable/disable ADMA on the ports appropriately */
1648 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1649
1650 pp = host->ports[0]->private_data;
1651 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1652 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1653 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1654 else
1655 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
1656 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1657 pp = host->ports[1]->private_data;
1658 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1659 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
1660 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1661 else
1662 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
1663 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1664
1665 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1666 }
1667 }
1668
1669 ata_host_resume(host);
1670
1671 return 0;
1672 }
1673 #endif
1674
1675 static void nv_ck804_host_stop(struct ata_host *host)
1676 {
1677 struct pci_dev *pdev = to_pci_dev(host->dev);
1678 u8 regval;
1679
1680 /* disable SATA space for CK804 */
1681 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1682 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1683 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1684 }
1685
1686 static void nv_adma_host_stop(struct ata_host *host)
1687 {
1688 struct pci_dev *pdev = to_pci_dev(host->dev);
1689 u32 tmp32;
1690
1691 /* disable ADMA on the ports */
1692 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1693 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1694 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1695 NV_MCP_SATA_CFG_20_PORT1_EN |
1696 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1697
1698 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1699
1700 nv_ck804_host_stop(host);
1701 }
1702
1703 static int __init nv_init(void)
1704 {
1705 return pci_register_driver(&nv_pci_driver);
1706 }
1707
1708 static void __exit nv_exit(void)
1709 {
1710 pci_unregister_driver(&nv_pci_driver);
1711 }
1712
1713 module_init(nv_init);
1714 module_exit(nv_exit);
1715 module_param_named(adma, adma_enabled, bool, 0444);
1716 MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");
Verdex Pro support