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[TCP] slow start: Make comments and code logic clearer.
[linux-2.6/verdex.git] / drivers / ata / sata_sis.c
blobee66c5fa7ac8d51144923a6dc52aaf0afbf3f7f8
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
43 #include "sis.h"
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "0.7"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
67 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
68 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
69
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
77
78 { } /* terminate list */
79 };
80
81 static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
86 };
87
88 static struct scsi_host_template sis_sht = {
89 .module = THIS_MODULE,
90 .name = DRV_NAME,
91 .ioctl = ata_scsi_ioctl,
92 .queuecommand = ata_scsi_queuecmd,
93 .can_queue = ATA_DEF_QUEUE,
94 .this_id = ATA_SHT_THIS_ID,
95 .sg_tablesize = ATA_MAX_PRD,
96 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
97 .emulated = ATA_SHT_EMULATED,
98 .use_clustering = ATA_SHT_USE_CLUSTERING,
99 .proc_name = DRV_NAME,
100 .dma_boundary = ATA_DMA_BOUNDARY,
101 .slave_configure = ata_scsi_slave_config,
102 .slave_destroy = ata_scsi_slave_destroy,
103 .bios_param = ata_std_bios_param,
104 };
105
106 static const struct ata_port_operations sis_ops = {
107 .port_disable = ata_port_disable,
108 .tf_load = ata_tf_load,
109 .tf_read = ata_tf_read,
110 .check_status = ata_check_status,
111 .exec_command = ata_exec_command,
112 .dev_select = ata_std_dev_select,
113 .bmdma_setup = ata_bmdma_setup,
114 .bmdma_start = ata_bmdma_start,
115 .bmdma_stop = ata_bmdma_stop,
116 .bmdma_status = ata_bmdma_status,
117 .qc_prep = ata_qc_prep,
118 .qc_issue = ata_qc_issue_prot,
119 .data_xfer = ata_data_xfer,
120 .freeze = ata_bmdma_freeze,
121 .thaw = ata_bmdma_thaw,
122 .error_handler = ata_bmdma_error_handler,
123 .post_internal_cmd = ata_bmdma_post_internal_cmd,
124 .irq_clear = ata_bmdma_irq_clear,
125 .irq_on = ata_irq_on,
126 .irq_ack = ata_irq_ack,
127 .scr_read = sis_scr_read,
128 .scr_write = sis_scr_write,
129 .port_start = ata_port_start,
130 };
131
132 static const struct ata_port_info sis_port_info = {
133 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
134 .pio_mask = 0x1f,
135 .mwdma_mask = 0x7,
136 .udma_mask = 0x7f,
137 .port_ops = &sis_ops,
138 };
139
140 MODULE_AUTHOR("Uwe Koziolek");
141 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
142 MODULE_LICENSE("GPL");
143 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
144 MODULE_VERSION(DRV_VERSION);
145
146 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
147 {
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
150 u8 pmr;
151
152 if (ap->port_no) {
153 switch (pdev->device) {
154 case 0x0180:
155 case 0x0181:
156 pci_read_config_byte(pdev, SIS_PMR, &pmr);
157 if ((pmr & SIS_PMR_COMBINED) == 0)
158 addr += SIS180_SATA1_OFS;
159 break;
160
161 case 0x0182:
162 case 0x0183:
163 case 0x1182:
164 case 0x1183:
165 addr += SIS182_SATA1_OFS;
166 break;
167 }
168 }
169 return addr;
170 }
171
172 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
173 {
174 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
175 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
176 u32 val, val2 = 0;
177 u8 pmr;
178
179 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
180 return 0xffffffff;
181
182 pci_read_config_byte(pdev, SIS_PMR, &pmr);
183
184 pci_read_config_dword(pdev, cfg_addr, &val);
185
186 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
187 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
188 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
189
190 return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
191 }
192
193 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
194 {
195 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
196 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
197 u8 pmr;
198
199 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
200 return;
201
202 pci_read_config_byte(pdev, SIS_PMR, &pmr);
203
204 pci_write_config_dword(pdev, cfg_addr, val);
205
206 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
207 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
208 pci_write_config_dword(pdev, cfg_addr+0x10, val);
209 }
210
211 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
212 {
213 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
214 u32 val, val2 = 0;
215 u8 pmr;
216
217 if (sc_reg > SCR_CONTROL)
218 return 0xffffffffU;
219
220 if (ap->flags & SIS_FLAG_CFGSCR)
221 return sis_scr_cfg_read(ap, sc_reg);
222
223 pci_read_config_byte(pdev, SIS_PMR, &pmr);
224
225 val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
226
227 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
228 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
229 val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
230
231 return (val | val2) & 0xfffffffb;
232 }
233
234 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
235 {
236 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
237 u8 pmr;
238
239 if (sc_reg > SCR_CONTROL)
240 return;
241
242 pci_read_config_byte(pdev, SIS_PMR, &pmr);
243
244 if (ap->flags & SIS_FLAG_CFGSCR)
245 sis_scr_cfg_write(ap, sc_reg, val);
246 else {
247 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
248 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
249 (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
250 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
251 }
252 }
253
254 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
255 {
256 static int printed_version;
257 struct ata_port_info pi = sis_port_info;
258 const struct ata_port_info *ppi[] = { &pi, NULL };
259 struct ata_host *host;
260 u32 genctl, val;
261 u8 pmr;
262 u8 port2_start = 0x20;
263 int rc;
264
265 if (!printed_version++)
266 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
267
268 rc = pcim_enable_device(pdev);
269 if (rc)
270 return rc;
271
272 /* check and see if the SCRs are in IO space or PCI cfg space */
273 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
274 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
275 pi.flags |= SIS_FLAG_CFGSCR;
276
277 /* if hardware thinks SCRs are in IO space, but there are
278 * no IO resources assigned, change to PCI cfg space.
279 */
280 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
281 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
282 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
283 genctl &= ~GENCTL_IOMAPPED_SCR;
284 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
285 pi.flags |= SIS_FLAG_CFGSCR;
286 }
287
288 pci_read_config_byte(pdev, SIS_PMR, &pmr);
289 switch (ent->device) {
290 case 0x0180:
291 case 0x0181:
292
293 /* The PATA-handling is provided by pata_sis */
294 switch (pmr & 0x30) {
295 case 0x10:
296 ppi[1] = &sis_info133;
297 break;
298
299 case 0x30:
300 ppi[0] = &sis_info133;
301 break;
302 }
303 if ((pmr & SIS_PMR_COMBINED) == 0) {
304 dev_printk(KERN_INFO, &pdev->dev,
305 "Detected SiS 180/181/964 chipset in SATA mode\n");
306 port2_start = 64;
307 } else {
308 dev_printk(KERN_INFO, &pdev->dev,
309 "Detected SiS 180/181 chipset in combined mode\n");
310 port2_start=0;
311 pi.flags |= ATA_FLAG_SLAVE_POSS;
312 }
313 break;
314
315 case 0x0182:
316 case 0x0183:
317 pci_read_config_dword ( pdev, 0x6C, &val);
318 if (val & (1L << 31)) {
319 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
320 pi.flags |= ATA_FLAG_SLAVE_POSS;
321 } else {
322 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
323 }
324 break;
325
326 case 0x1182:
327 case 0x1183:
328 pci_read_config_dword(pdev, 0x64, &val);
329 if (val & 0x10000000) {
330 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
331 } else {
332 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
333 pi.flags |= ATA_FLAG_SLAVE_POSS;
334 }
335 break;
336 }
337
338 rc = ata_pci_prepare_native_host(pdev, ppi, &host);
339 if (rc)
340 return rc;
341
342 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
343 void __iomem *mmio;
344
345 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
346 if (rc)
347 return rc;
348 mmio = host->iomap[SIS_SCR_PCI_BAR];
349
350 host->ports[0]->ioaddr.scr_addr = mmio;
351 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
352 }
353
354 pci_set_master(pdev);
355 pci_intx(pdev, 1);
356 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
357 &sis_sht);
358 }
359
360 static int __init sis_init(void)
361 {
362 return pci_register_driver(&sis_pci_driver);
363 }
364
365 static void __exit sis_exit(void)
366 {
367 pci_unregister_driver(&sis_pci_driver);
368 }
369
370 module_init(sis_init);
371 module_exit(sis_exit);
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