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[CONNECTOR]: Replace delayed work with usual work queue.
[linux-2.6/verdex.git] / include / asm-ia64 / pal.h
blobbc768153f3c95a9cb55020888463f245baaea9d0
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
3
4 /*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
23 * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
24 * Manual Rev 2.2 (Jan 2006)
25 */
26
27 /*
28 * Note that some of these calls use a static-register only calling
29 * convention which has nothing to do with the regular calling
30 * convention.
31 */
32 #define PAL_CACHE_FLUSH 1 /* flush i/d cache */
33 #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
34 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
35 #define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
36 #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
37 #define PAL_PTCE_INFO 6 /* purge TLB info */
38 #define PAL_VM_INFO 7 /* return supported virtual memory features */
39 #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
40 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
41 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
42 #define PAL_DEBUG_INFO 11 /* get number of debug registers */
43 #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
44 #define PAL_FREQ_BASE 13 /* base frequency of the platform */
45 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
46 #define PAL_PERF_MON_INFO 15 /* return performance monitor info */
47 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
48 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
49 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
50 #define PAL_RSE_INFO 19 /* return rse information */
51 #define PAL_VERSION 20 /* return version of PAL code */
52 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
53 #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
54 #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
55 #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
56 #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
57 #define PAL_MC_RESUME 26 /* Return to interrupted process */
58 #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
59 #define PAL_HALT 28 /* enter the low power HALT state */
60 #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
61 #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
62 #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
63 #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
64 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
65 #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
66
67 #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
68 #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
69 #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
70 #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
71 #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
72 #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
73 #define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
74 #define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
75 #define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
76
77 #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
78 #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
79 #define PAL_TEST_PROC 258 /* perform late processor self-test */
80 #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
81 #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
82 #define PAL_VM_TR_READ 261 /* read contents of translation register */
83 #define PAL_GET_PSTATE 262 /* get the current P-state */
84 #define PAL_SET_PSTATE 263 /* set the P-state */
85 #define PAL_BRAND_INFO 274 /* Processor branding information */
86
87 #define PAL_GET_PSTATE_TYPE_LASTSET 0
88 #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
89 #define PAL_GET_PSTATE_TYPE_AVGNORESET 2
90 #define PAL_GET_PSTATE_TYPE_INSTANT 3
91
92 #ifndef __ASSEMBLY__
93
94 #include <linux/types.h>
95 #include <asm/fpu.h>
96
97 /*
98 * Data types needed to pass information into PAL procedures and
99 * interpret information returned by them.
100 */
101
102 /* Return status from the PAL procedure */
103 typedef s64 pal_status_t;
104
105 #define PAL_STATUS_SUCCESS 0 /* No error */
106 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
107 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
108 #define PAL_STATUS_ERROR (-3) /* Error */
109 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
110 * specified level and type of
111 * cache without sideeffects
112 * and "restrict" was 1
113 */
114 #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
115
116 /* Processor cache level in the heirarchy */
117 typedef u64 pal_cache_level_t;
118 #define PAL_CACHE_LEVEL_L0 0 /* L0 */
119 #define PAL_CACHE_LEVEL_L1 1 /* L1 */
120 #define PAL_CACHE_LEVEL_L2 2 /* L2 */
121
122
123 /* Processor cache type at a particular level in the heirarchy */
124
125 typedef u64 pal_cache_type_t;
126 #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
127 #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
128 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
129
130
131 #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
132 #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
133
134 /* Processor cache line size in bytes */
135 typedef int pal_cache_line_size_t;
136
137 /* Processor cache line state */
138 typedef u64 pal_cache_line_state_t;
139 #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
140 #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
141 #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
142 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
143
144 typedef struct pal_freq_ratio {
145 u32 den, num; /* numerator & denominator */
146 } itc_ratio, proc_ratio;
147
148 typedef union pal_cache_config_info_1_s {
149 struct {
150 u64 u : 1, /* 0 Unified cache ? */
151 at : 2, /* 2-1 Cache mem attr*/
152 reserved : 5, /* 7-3 Reserved */
153 associativity : 8, /* 16-8 Associativity*/
154 line_size : 8, /* 23-17 Line size */
155 stride : 8, /* 31-24 Stride */
156 store_latency : 8, /*39-32 Store latency*/
157 load_latency : 8, /* 47-40 Load latency*/
158 store_hints : 8, /* 55-48 Store hints*/
159 load_hints : 8; /* 63-56 Load hints */
160 } pcci1_bits;
161 u64 pcci1_data;
162 } pal_cache_config_info_1_t;
163
164 typedef union pal_cache_config_info_2_s {
165 struct {
166 u32 cache_size; /*cache size in bytes*/
167
168
169 u32 alias_boundary : 8, /* 39-32 aliased addr
170 * separation for max
171 * performance.
172 */
173 tag_ls_bit : 8, /* 47-40 LSb of addr*/
174 tag_ms_bit : 8, /* 55-48 MSb of addr*/
175 reserved : 8; /* 63-56 Reserved */
176 } pcci2_bits;
177 u64 pcci2_data;
178 } pal_cache_config_info_2_t;
179
180
181 typedef struct pal_cache_config_info_s {
182 pal_status_t pcci_status;
183 pal_cache_config_info_1_t pcci_info_1;
184 pal_cache_config_info_2_t pcci_info_2;
185 u64 pcci_reserved;
186 } pal_cache_config_info_t;
187
188 #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
189 #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
190 #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
191 #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
192 #define pcci_stride pcci_info_1.pcci1_bits.stride
193 #define pcci_line_size pcci_info_1.pcci1_bits.line_size
194 #define pcci_assoc pcci_info_1.pcci1_bits.associativity
195 #define pcci_cache_attr pcci_info_1.pcci1_bits.at
196 #define pcci_unified pcci_info_1.pcci1_bits.u
197 #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
198 #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
199 #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
200 #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
201
202
203
204 /* Possible values for cache attributes */
205
206 #define PAL_CACHE_ATTR_WT 0 /* Write through cache */
207 #define PAL_CACHE_ATTR_WB 1 /* Write back cache */
208 #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
209 * back depending on TLB
210 * memory attributes
211 */
212
213
214 /* Possible values for cache hints */
215
216 #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
217 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
218 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
219
220 /* Processor cache protection information */
221 typedef union pal_cache_protection_element_u {
222 u32 pcpi_data;
223 struct {
224 u32 data_bits : 8, /* # data bits covered by
225 * each unit of protection
226 */
227
228 tagprot_lsb : 6, /* Least -do- */
229 tagprot_msb : 6, /* Most Sig. tag address
230 * bit that this
231 * protection covers.
232 */
233 prot_bits : 6, /* # of protection bits */
234 method : 4, /* Protection method */
235 t_d : 2; /* Indicates which part
236 * of the cache this
237 * protection encoding
238 * applies.
239 */
240 } pcp_info;
241 } pal_cache_protection_element_t;
242
243 #define pcpi_cache_prot_part pcp_info.t_d
244 #define pcpi_prot_method pcp_info.method
245 #define pcpi_prot_bits pcp_info.prot_bits
246 #define pcpi_tagprot_msb pcp_info.tagprot_msb
247 #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
248 #define pcpi_data_bits pcp_info.data_bits
249
250 /* Processor cache part encodings */
251 #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
252 #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
253 #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
254 * more significant )
255 */
256 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
257 * more significant )
258 */
259 #define PAL_CACHE_PROT_PART_MAX 6
260
261
262 typedef struct pal_cache_protection_info_s {
263 pal_status_t pcpi_status;
264 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
265 } pal_cache_protection_info_t;
266
267
268 /* Processor cache protection method encodings */
269 #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
270 #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
271 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
272 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
273
274
275 /* Processor cache line identification in the heirarchy */
276 typedef union pal_cache_line_id_u {
277 u64 pclid_data;
278 struct {
279 u64 cache_type : 8, /* 7-0 cache type */
280 level : 8, /* 15-8 level of the
281 * cache in the
282 * heirarchy.
283 */
284 way : 8, /* 23-16 way in the set
285 */
286 part : 8, /* 31-24 part of the
287 * cache
288 */
289 reserved : 32; /* 63-32 is reserved*/
290 } pclid_info_read;
291 struct {
292 u64 cache_type : 8, /* 7-0 cache type */
293 level : 8, /* 15-8 level of the
294 * cache in the
295 * heirarchy.
296 */
297 way : 8, /* 23-16 way in the set
298 */
299 part : 8, /* 31-24 part of the
300 * cache
301 */
302 mesi : 8, /* 39-32 cache line
303 * state
304 */
305 start : 8, /* 47-40 lsb of data to
306 * invert
307 */
308 length : 8, /* 55-48 #bits to
309 * invert
310 */
311 trigger : 8; /* 63-56 Trigger error
312 * by doing a load
313 * after the write
314 */
315
316 } pclid_info_write;
317 } pal_cache_line_id_u_t;
318
319 #define pclid_read_part pclid_info_read.part
320 #define pclid_read_way pclid_info_read.way
321 #define pclid_read_level pclid_info_read.level
322 #define pclid_read_cache_type pclid_info_read.cache_type
323
324 #define pclid_write_trigger pclid_info_write.trigger
325 #define pclid_write_length pclid_info_write.length
326 #define pclid_write_start pclid_info_write.start
327 #define pclid_write_mesi pclid_info_write.mesi
328 #define pclid_write_part pclid_info_write.part
329 #define pclid_write_way pclid_info_write.way
330 #define pclid_write_level pclid_info_write.level
331 #define pclid_write_cache_type pclid_info_write.cache_type
332
333 /* Processor cache line part encodings */
334 #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
335 #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
336 #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
337 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
338 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
339 * protection
340 */
341 typedef struct pal_cache_line_info_s {
342 pal_status_t pcli_status; /* Return status of the read cache line
343 * info call.
344 */
345 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
346 u64 pcli_data_len; /* data length in bits */
347 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
348
349 } pal_cache_line_info_t;
350
351
352 /* Machine Check related crap */
353
354 /* Pending event status bits */
355 typedef u64 pal_mc_pending_events_t;
356
357 #define PAL_MC_PENDING_MCA (1 << 0)
358 #define PAL_MC_PENDING_INIT (1 << 1)
359
360 /* Error information type */
361 typedef u64 pal_mc_info_index_t;
362
363 #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
364 #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
365 #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
366 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
367 #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
368 #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
369 #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
370 #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
371 * dependent
372 */
373
374
375 typedef struct pal_process_state_info_s {
376 u64 reserved1 : 2,
377 rz : 1, /* PAL_CHECK processor
378 * rendezvous
379 * successful.
380 */
381
382 ra : 1, /* PAL_CHECK attempted
383 * a rendezvous.
384 */
385 me : 1, /* Distinct multiple
386 * errors occurred
387 */
388
389 mn : 1, /* Min. state save
390 * area has been
391 * registered with PAL
392 */
393
394 sy : 1, /* Storage integrity
395 * synched
396 */
397
398
399 co : 1, /* Continuable */
400 ci : 1, /* MC isolated */
401 us : 1, /* Uncontained storage
402 * damage.
403 */
404
405
406 hd : 1, /* Non-essential hw
407 * lost (no loss of
408 * functionality)
409 * causing the
410 * processor to run in
411 * degraded mode.
412 */
413
414 tl : 1, /* 1 => MC occurred
415 * after an instr was
416 * executed but before
417 * the trap that
418 * resulted from instr
419 * execution was
420 * generated.
421 * (Trap Lost )
422 */
423 mi : 1, /* More information available
424 * call PAL_MC_ERROR_INFO
425 */
426 pi : 1, /* Precise instruction pointer */
427 pm : 1, /* Precise min-state save area */
428
429 dy : 1, /* Processor dynamic
430 * state valid
431 */
432
433
434 in : 1, /* 0 = MC, 1 = INIT */
435 rs : 1, /* RSE valid */
436 cm : 1, /* MC corrected */
437 ex : 1, /* MC is expected */
438 cr : 1, /* Control regs valid*/
439 pc : 1, /* Perf cntrs valid */
440 dr : 1, /* Debug regs valid */
441 tr : 1, /* Translation regs
442 * valid
443 */
444 rr : 1, /* Region regs valid */
445 ar : 1, /* App regs valid */
446 br : 1, /* Branch regs valid */
447 pr : 1, /* Predicate registers
448 * valid
449 */
450
451 fp : 1, /* fp registers valid*/
452 b1 : 1, /* Preserved bank one
453 * general registers
454 * are valid
455 */
456 b0 : 1, /* Preserved bank zero
457 * general registers
458 * are valid
459 */
460 gr : 1, /* General registers
461 * are valid
462 * (excl. banked regs)
463 */
464 dsize : 16, /* size of dynamic
465 * state returned
466 * by the processor
467 */
468
469 se : 1, /* Shared error. MCA in a
470 shared structure */
471 reserved2 : 10,
472 cc : 1, /* Cache check */
473 tc : 1, /* TLB check */
474 bc : 1, /* Bus check */
475 rc : 1, /* Register file check */
476 uc : 1; /* Uarch check */
477
478 } pal_processor_state_info_t;
479
480 typedef struct pal_cache_check_info_s {
481 u64 op : 4, /* Type of cache
482 * operation that
483 * caused the machine
484 * check.
485 */
486 level : 2, /* Cache level */
487 reserved1 : 2,
488 dl : 1, /* Failure in data part
489 * of cache line
490 */
491 tl : 1, /* Failure in tag part
492 * of cache line
493 */
494 dc : 1, /* Failure in dcache */
495 ic : 1, /* Failure in icache */
496 mesi : 3, /* Cache line state */
497 mv : 1, /* mesi valid */
498 way : 5, /* Way in which the
499 * error occurred
500 */
501 wiv : 1, /* Way field valid */
502 reserved2 : 1,
503 dp : 1, /* Data poisoned on MBE */
504 reserved3 : 8,
505
506 index : 20, /* Cache line index */
507 reserved4 : 2,
508
509 is : 1, /* instruction set (1 == ia32) */
510 iv : 1, /* instruction set field valid */
511 pl : 2, /* privilege level */
512 pv : 1, /* privilege level field valid */
513 mcc : 1, /* Machine check corrected */
514 tv : 1, /* Target address
515 * structure is valid
516 */
517 rq : 1, /* Requester identifier
518 * structure is valid
519 */
520 rp : 1, /* Responder identifier
521 * structure is valid
522 */
523 pi : 1; /* Precise instruction pointer
524 * structure is valid
525 */
526 } pal_cache_check_info_t;
527
528 typedef struct pal_tlb_check_info_s {
529
530 u64 tr_slot : 8, /* Slot# of TR where
531 * error occurred
532 */
533 trv : 1, /* tr_slot field is valid */
534 reserved1 : 1,
535 level : 2, /* TLB level where failure occurred */
536 reserved2 : 4,
537 dtr : 1, /* Fail in data TR */
538 itr : 1, /* Fail in inst TR */
539 dtc : 1, /* Fail in data TC */
540 itc : 1, /* Fail in inst. TC */
541 op : 4, /* Cache operation */
542 reserved3 : 30,
543
544 is : 1, /* instruction set (1 == ia32) */
545 iv : 1, /* instruction set field valid */
546 pl : 2, /* privilege level */
547 pv : 1, /* privilege level field valid */
548 mcc : 1, /* Machine check corrected */
549 tv : 1, /* Target address
550 * structure is valid
551 */
552 rq : 1, /* Requester identifier
553 * structure is valid
554 */
555 rp : 1, /* Responder identifier
556 * structure is valid
557 */
558 pi : 1; /* Precise instruction pointer
559 * structure is valid
560 */
561 } pal_tlb_check_info_t;
562
563 typedef struct pal_bus_check_info_s {
564 u64 size : 5, /* Xaction size */
565 ib : 1, /* Internal bus error */
566 eb : 1, /* External bus error */
567 cc : 1, /* Error occurred
568 * during cache-cache
569 * transfer.
570 */
571 type : 8, /* Bus xaction type*/
572 sev : 5, /* Bus error severity*/
573 hier : 2, /* Bus hierarchy level */
574 dp : 1, /* Data poisoned on MBE */
575 bsi : 8, /* Bus error status
576 * info
577 */
578 reserved2 : 22,
579
580 is : 1, /* instruction set (1 == ia32) */
581 iv : 1, /* instruction set field valid */
582 pl : 2, /* privilege level */
583 pv : 1, /* privilege level field valid */
584 mcc : 1, /* Machine check corrected */
585 tv : 1, /* Target address
586 * structure is valid
587 */
588 rq : 1, /* Requester identifier
589 * structure is valid
590 */
591 rp : 1, /* Responder identifier
592 * structure is valid
593 */
594 pi : 1; /* Precise instruction pointer
595 * structure is valid
596 */
597 } pal_bus_check_info_t;
598
599 typedef struct pal_reg_file_check_info_s {
600 u64 id : 4, /* Register file identifier */
601 op : 4, /* Type of register
602 * operation that
603 * caused the machine
604 * check.
605 */
606 reg_num : 7, /* Register number */
607 rnv : 1, /* reg_num valid */
608 reserved2 : 38,
609
610 is : 1, /* instruction set (1 == ia32) */
611 iv : 1, /* instruction set field valid */
612 pl : 2, /* privilege level */
613 pv : 1, /* privilege level field valid */
614 mcc : 1, /* Machine check corrected */
615 reserved3 : 3,
616 pi : 1; /* Precise instruction pointer
617 * structure is valid
618 */
619 } pal_reg_file_check_info_t;
620
621 typedef struct pal_uarch_check_info_s {
622 u64 sid : 5, /* Structure identification */
623 level : 3, /* Level of failure */
624 array_id : 4, /* Array identification */
625 op : 4, /* Type of
626 * operation that
627 * caused the machine
628 * check.
629 */
630 way : 6, /* Way of structure */
631 wv : 1, /* way valid */
632 xv : 1, /* index valid */
633 reserved1 : 8,
634 index : 8, /* Index or set of the uarch
635 * structure that failed.
636 */
637 reserved2 : 24,
638
639 is : 1, /* instruction set (1 == ia32) */
640 iv : 1, /* instruction set field valid */
641 pl : 2, /* privilege level */
642 pv : 1, /* privilege level field valid */
643 mcc : 1, /* Machine check corrected */
644 tv : 1, /* Target address
645 * structure is valid
646 */
647 rq : 1, /* Requester identifier
648 * structure is valid
649 */
650 rp : 1, /* Responder identifier
651 * structure is valid
652 */
653 pi : 1; /* Precise instruction pointer
654 * structure is valid
655 */
656 } pal_uarch_check_info_t;
657
658 typedef union pal_mc_error_info_u {
659 u64 pmei_data;
660 pal_processor_state_info_t pme_processor;
661 pal_cache_check_info_t pme_cache;
662 pal_tlb_check_info_t pme_tlb;
663 pal_bus_check_info_t pme_bus;
664 pal_reg_file_check_info_t pme_reg_file;
665 pal_uarch_check_info_t pme_uarch;
666 } pal_mc_error_info_t;
667
668 #define pmci_proc_unknown_check pme_processor.uc
669 #define pmci_proc_bus_check pme_processor.bc
670 #define pmci_proc_tlb_check pme_processor.tc
671 #define pmci_proc_cache_check pme_processor.cc
672 #define pmci_proc_dynamic_state_size pme_processor.dsize
673 #define pmci_proc_gpr_valid pme_processor.gr
674 #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
675 #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
676 #define pmci_proc_fp_valid pme_processor.fp
677 #define pmci_proc_predicate_regs_valid pme_processor.pr
678 #define pmci_proc_branch_regs_valid pme_processor.br
679 #define pmci_proc_app_regs_valid pme_processor.ar
680 #define pmci_proc_region_regs_valid pme_processor.rr
681 #define pmci_proc_translation_regs_valid pme_processor.tr
682 #define pmci_proc_debug_regs_valid pme_processor.dr
683 #define pmci_proc_perf_counters_valid pme_processor.pc
684 #define pmci_proc_control_regs_valid pme_processor.cr
685 #define pmci_proc_machine_check_expected pme_processor.ex
686 #define pmci_proc_machine_check_corrected pme_processor.cm
687 #define pmci_proc_rse_valid pme_processor.rs
688 #define pmci_proc_machine_check_or_init pme_processor.in
689 #define pmci_proc_dynamic_state_valid pme_processor.dy
690 #define pmci_proc_operation pme_processor.op
691 #define pmci_proc_trap_lost pme_processor.tl
692 #define pmci_proc_hardware_damage pme_processor.hd
693 #define pmci_proc_uncontained_storage_damage pme_processor.us
694 #define pmci_proc_machine_check_isolated pme_processor.ci
695 #define pmci_proc_continuable pme_processor.co
696 #define pmci_proc_storage_intergrity_synced pme_processor.sy
697 #define pmci_proc_min_state_save_area_regd pme_processor.mn
698 #define pmci_proc_distinct_multiple_errors pme_processor.me
699 #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
700 #define pmci_proc_pal_rendezvous_complete pme_processor.rz
701
702
703 #define pmci_cache_level pme_cache.level
704 #define pmci_cache_line_state pme_cache.mesi
705 #define pmci_cache_line_state_valid pme_cache.mv
706 #define pmci_cache_line_index pme_cache.index
707 #define pmci_cache_instr_cache_fail pme_cache.ic
708 #define pmci_cache_data_cache_fail pme_cache.dc
709 #define pmci_cache_line_tag_fail pme_cache.tl
710 #define pmci_cache_line_data_fail pme_cache.dl
711 #define pmci_cache_operation pme_cache.op
712 #define pmci_cache_way_valid pme_cache.wv
713 #define pmci_cache_target_address_valid pme_cache.tv
714 #define pmci_cache_way pme_cache.way
715 #define pmci_cache_mc pme_cache.mc
716
717 #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
718 #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
719 #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
720 #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
721 #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
722 #define pmci_tlb_mc pme_tlb.mc
723
724 #define pmci_bus_status_info pme_bus.bsi
725 #define pmci_bus_req_address_valid pme_bus.rq
726 #define pmci_bus_resp_address_valid pme_bus.rp
727 #define pmci_bus_target_address_valid pme_bus.tv
728 #define pmci_bus_error_severity pme_bus.sev
729 #define pmci_bus_transaction_type pme_bus.type
730 #define pmci_bus_cache_cache_transfer pme_bus.cc
731 #define pmci_bus_transaction_size pme_bus.size
732 #define pmci_bus_internal_error pme_bus.ib
733 #define pmci_bus_external_error pme_bus.eb
734 #define pmci_bus_mc pme_bus.mc
735
736 /*
737 * NOTE: this min_state_save area struct only includes the 1KB
738 * architectural state save area. The other 3 KB is scratch space
739 * for PAL.
740 */
741
742 typedef struct pal_min_state_area_s {
743 u64 pmsa_nat_bits; /* nat bits for saved GRs */
744 u64 pmsa_gr[15]; /* GR1 - GR15 */
745 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
746 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
747 u64 pmsa_pr; /* predicate registers */
748 u64 pmsa_br0; /* branch register 0 */
749 u64 pmsa_rsc; /* ar.rsc */
750 u64 pmsa_iip; /* cr.iip */
751 u64 pmsa_ipsr; /* cr.ipsr */
752 u64 pmsa_ifs; /* cr.ifs */
753 u64 pmsa_xip; /* previous iip */
754 u64 pmsa_xpsr; /* previous psr */
755 u64 pmsa_xfs; /* previous ifs */
756 u64 pmsa_br1; /* branch register 1 */
757 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
758 } pal_min_state_area_t;
759
760
761 struct ia64_pal_retval {
762 /*
763 * A zero status value indicates call completed without error.
764 * A negative status value indicates reason of call failure.
765 * A positive status value indicates success but an
766 * informational value should be printed (e.g., "reboot for
767 * change to take effect").
768 */
769 s64 status;
770 u64 v0;
771 u64 v1;
772 u64 v2;
773 };
774
775 /*
776 * Note: Currently unused PAL arguments are generally labeled
777 * "reserved" so the value specified in the PAL documentation
778 * (generally 0) MUST be passed. Reserved parameters are not optional
779 * parameters.
780 */
781 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
782 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
783 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
784 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
785 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
786 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
787
788 #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
789 struct ia64_fpreg fr[6]; \
790 ia64_save_scratch_fpregs(fr); \
791 iprv = ia64_pal_call_static(a0, a1, a2, a3); \
792 ia64_load_scratch_fpregs(fr); \
793 } while (0)
794
795 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
796 struct ia64_fpreg fr[6]; \
797 ia64_save_scratch_fpregs(fr); \
798 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
799 ia64_load_scratch_fpregs(fr); \
800 } while (0)
801
802 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
803 struct ia64_fpreg fr[6]; \
804 ia64_save_scratch_fpregs(fr); \
805 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
806 ia64_load_scratch_fpregs(fr); \
807 } while (0)
808
809 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
810 struct ia64_fpreg fr[6]; \
811 ia64_save_scratch_fpregs(fr); \
812 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
813 ia64_load_scratch_fpregs(fr); \
814 } while (0)
815
816 typedef int (*ia64_pal_handler) (u64, ...);
817 extern ia64_pal_handler ia64_pal;
818 extern void ia64_pal_handler_init (void *);
819
820 extern ia64_pal_handler ia64_pal;
821
822 extern pal_cache_config_info_t l0d_cache_config_info;
823 extern pal_cache_config_info_t l0i_cache_config_info;
824 extern pal_cache_config_info_t l1_cache_config_info;
825 extern pal_cache_config_info_t l2_cache_config_info;
826
827 extern pal_cache_protection_info_t l0d_cache_protection_info;
828 extern pal_cache_protection_info_t l0i_cache_protection_info;
829 extern pal_cache_protection_info_t l1_cache_protection_info;
830 extern pal_cache_protection_info_t l2_cache_protection_info;
831
832 extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
833 pal_cache_type_t);
834
835 extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
836 pal_cache_type_t);
837
838
839 extern void pal_error(int);
840
841
842 /* Useful wrappers for the current list of pal procedures */
843
844 typedef union pal_bus_features_u {
845 u64 pal_bus_features_val;
846 struct {
847 u64 pbf_reserved1 : 29;
848 u64 pbf_req_bus_parking : 1;
849 u64 pbf_bus_lock_mask : 1;
850 u64 pbf_enable_half_xfer_rate : 1;
851 u64 pbf_reserved2 : 20;
852 u64 pbf_enable_shared_line_replace : 1;
853 u64 pbf_enable_exclusive_line_replace : 1;
854 u64 pbf_disable_xaction_queueing : 1;
855 u64 pbf_disable_resp_err_check : 1;
856 u64 pbf_disable_berr_check : 1;
857 u64 pbf_disable_bus_req_internal_err_signal : 1;
858 u64 pbf_disable_bus_req_berr_signal : 1;
859 u64 pbf_disable_bus_init_event_check : 1;
860 u64 pbf_disable_bus_init_event_signal : 1;
861 u64 pbf_disable_bus_addr_err_check : 1;
862 u64 pbf_disable_bus_addr_err_signal : 1;
863 u64 pbf_disable_bus_data_err_check : 1;
864 } pal_bus_features_s;
865 } pal_bus_features_u_t;
866
867 extern void pal_bus_features_print (u64);
868
869 /* Provide information about configurable processor bus features */
870 static inline s64
871 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
872 pal_bus_features_u_t *features_status,
873 pal_bus_features_u_t *features_control)
874 {
875 struct ia64_pal_retval iprv;
876 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
877 if (features_avail)
878 features_avail->pal_bus_features_val = iprv.v0;
879 if (features_status)
880 features_status->pal_bus_features_val = iprv.v1;
881 if (features_control)
882 features_control->pal_bus_features_val = iprv.v2;
883 return iprv.status;
884 }
885
886 /* Enables/disables specific processor bus features */
887 static inline s64
888 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
889 {
890 struct ia64_pal_retval iprv;
891 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
892 return iprv.status;
893 }
894
895 /* Get detailed cache information */
896 static inline s64
897 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
898 {
899 struct ia64_pal_retval iprv;
900
901 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
902
903 if (iprv.status == 0) {
904 conf->pcci_status = iprv.status;
905 conf->pcci_info_1.pcci1_data = iprv.v0;
906 conf->pcci_info_2.pcci2_data = iprv.v1;
907 conf->pcci_reserved = iprv.v2;
908 }
909 return iprv.status;
910
911 }
912
913 /* Get detailed cche protection information */
914 static inline s64
915 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
916 {
917 struct ia64_pal_retval iprv;
918
919 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
920
921 if (iprv.status == 0) {
922 prot->pcpi_status = iprv.status;
923 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
924 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
925 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
926 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
927 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
928 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
929 }
930 return iprv.status;
931 }
932
933 /*
934 * Flush the processor instruction or data caches. *PROGRESS must be
935 * initialized to zero before calling this for the first time..
936 */
937 static inline s64
938 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
939 {
940 struct ia64_pal_retval iprv;
941 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
942 if (vector)
943 *vector = iprv.v0;
944 *progress = iprv.v1;
945 return iprv.status;
946 }
947
948
949 /* Initialize the processor controlled caches */
950 static inline s64
951 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
952 {
953 struct ia64_pal_retval iprv;
954 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
955 return iprv.status;
956 }
957
958 /* Initialize the tags and data of a data or unified cache line of
959 * processor controlled cache to known values without the availability
960 * of backing memory.
961 */
962 static inline s64
963 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
964 {
965 struct ia64_pal_retval iprv;
966 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
967 return iprv.status;
968 }
969
970
971 /* Read the data and tag of a processor controlled cache line for diags */
972 static inline s64
973 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
974 {
975 struct ia64_pal_retval iprv;
976 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
977 physical_addr, 0);
978 return iprv.status;
979 }
980
981 /* Return summary information about the heirarchy of caches controlled by the processor */
982 static inline s64
983 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
984 {
985 struct ia64_pal_retval iprv;
986 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
987 if (cache_levels)
988 *cache_levels = iprv.v0;
989 if (unique_caches)
990 *unique_caches = iprv.v1;
991 return iprv.status;
992 }
993
994 /* Write the data and tag of a processor-controlled cache line for diags */
995 static inline s64
996 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
997 {
998 struct ia64_pal_retval iprv;
999 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1000 physical_addr, data);
1001 return iprv.status;
1002 }
1003
1004
1005 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1006 static inline s64
1007 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1008 u64 *buffer_size, u64 *buffer_align)
1009 {
1010 struct ia64_pal_retval iprv;
1011 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1012 if (buffer_size)
1013 *buffer_size = iprv.v0;
1014 if (buffer_align)
1015 *buffer_align = iprv.v1;
1016 return iprv.status;
1017 }
1018
1019 /* Copy relocatable PAL procedures from ROM to memory */
1020 static inline s64
1021 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1022 {
1023 struct ia64_pal_retval iprv;
1024 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1025 if (pal_proc_offset)
1026 *pal_proc_offset = iprv.v0;
1027 return iprv.status;
1028 }
1029
1030 /* Return the number of instruction and data debug register pairs */
1031 static inline s64
1032 ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1033 {
1034 struct ia64_pal_retval iprv;
1035 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1036 if (inst_regs)
1037 *inst_regs = iprv.v0;
1038 if (data_regs)
1039 *data_regs = iprv.v1;
1040
1041 return iprv.status;
1042 }
1043
1044 #ifdef TBD
1045 /* Switch from IA64-system environment to IA-32 system environment */
1046 static inline s64
1047 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1048 {
1049 struct ia64_pal_retval iprv;
1050 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1051 return iprv.status;
1052 }
1053 #endif
1054
1055 /* Get unique geographical address of this processor on its bus */
1056 static inline s64
1057 ia64_pal_fixed_addr (u64 *global_unique_addr)
1058 {
1059 struct ia64_pal_retval iprv;
1060 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1061 if (global_unique_addr)
1062 *global_unique_addr = iprv.v0;
1063 return iprv.status;
1064 }
1065
1066 /* Get base frequency of the platform if generated by the processor */
1067 static inline s64
1068 ia64_pal_freq_base (u64 *platform_base_freq)
1069 {
1070 struct ia64_pal_retval iprv;
1071 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1072 if (platform_base_freq)
1073 *platform_base_freq = iprv.v0;
1074 return iprv.status;
1075 }
1076
1077 /*
1078 * Get the ratios for processor frequency, bus frequency and interval timer to
1079 * to base frequency of the platform
1080 */
1081 static inline s64
1082 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1083 struct pal_freq_ratio *itc_ratio)
1084 {
1085 struct ia64_pal_retval iprv;
1086 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1087 if (proc_ratio)
1088 *(u64 *)proc_ratio = iprv.v0;
1089 if (bus_ratio)
1090 *(u64 *)bus_ratio = iprv.v1;
1091 if (itc_ratio)
1092 *(u64 *)itc_ratio = iprv.v2;
1093 return iprv.status;
1094 }
1095
1096 /*
1097 * Get the current hardware resource sharing policy of the processor
1098 */
1099 static inline s64
1100 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1101 u64 *la)
1102 {
1103 struct ia64_pal_retval iprv;
1104 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1105 if (cur_policy)
1106 *cur_policy = iprv.v0;
1107 if (num_impacted)
1108 *num_impacted = iprv.v1;
1109 if (la)
1110 *la = iprv.v2;
1111 return iprv.status;
1112 }
1113
1114 /* Make the processor enter HALT or one of the implementation dependent low
1115 * power states where prefetching and execution are suspended and cache and
1116 * TLB coherency is not maintained.
1117 */
1118 static inline s64
1119 ia64_pal_halt (u64 halt_state)
1120 {
1121 struct ia64_pal_retval iprv;
1122 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1123 return iprv.status;
1124 }
1125
1126 typedef union pal_power_mgmt_info_u {
1127 u64 ppmi_data;
1128 struct {
1129 u64 exit_latency : 16,
1130 entry_latency : 16,
1131 power_consumption : 28,
1132 im : 1,
1133 co : 1,
1134 reserved : 2;
1135 } pal_power_mgmt_info_s;
1136 } pal_power_mgmt_info_u_t;
1137
1138 /* Return information about processor's optional power management capabilities. */
1139 static inline s64
1140 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1141 {
1142 struct ia64_pal_retval iprv;
1143 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1144 return iprv.status;
1145 }
1146
1147 /* Get the current P-state information */
1148 static inline s64
1149 ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1150 {
1151 struct ia64_pal_retval iprv;
1152 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1153 *pstate_index = iprv.v0;
1154 return iprv.status;
1155 }
1156
1157 /* Set the P-state */
1158 static inline s64
1159 ia64_pal_set_pstate (u64 pstate_index)
1160 {
1161 struct ia64_pal_retval iprv;
1162 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1163 return iprv.status;
1164 }
1165
1166 /* Processor branding information*/
1167 static inline s64
1168 ia64_pal_get_brand_info (char *brand_info)
1169 {
1170 struct ia64_pal_retval iprv;
1171 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1172 return iprv.status;
1173 }
1174
1175 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1176 * suspended, but cache and TLB coherency is maintained.
1177 */
1178 static inline s64
1179 ia64_pal_halt_light (void)
1180 {
1181 struct ia64_pal_retval iprv;
1182 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1183 return iprv.status;
1184 }
1185
1186 /* Clear all the processor error logging registers and reset the indicator that allows
1187 * the error logging registers to be written. This procedure also checks the pending
1188 * machine check bit and pending INIT bit and reports their states.
1189 */
1190 static inline s64
1191 ia64_pal_mc_clear_log (u64 *pending_vector)
1192 {
1193 struct ia64_pal_retval iprv;
1194 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1195 if (pending_vector)
1196 *pending_vector = iprv.v0;
1197 return iprv.status;
1198 }
1199
1200 /* Ensure that all outstanding transactions in a processor are completed or that any
1201 * MCA due to thes outstanding transaction is taken.
1202 */
1203 static inline s64
1204 ia64_pal_mc_drain (void)
1205 {
1206 struct ia64_pal_retval iprv;
1207 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1208 return iprv.status;
1209 }
1210
1211 /* Return the machine check dynamic processor state */
1212 static inline s64
1213 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1214 {
1215 struct ia64_pal_retval iprv;
1216 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1217 if (size)
1218 *size = iprv.v0;
1219 if (pds)
1220 *pds = iprv.v1;
1221 return iprv.status;
1222 }
1223
1224 /* Return processor machine check information */
1225 static inline s64
1226 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1227 {
1228 struct ia64_pal_retval iprv;
1229 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1230 if (size)
1231 *size = iprv.v0;
1232 if (error_info)
1233 *error_info = iprv.v1;
1234 return iprv.status;
1235 }
1236
1237 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1238 * attempt to correct any expected machine checks.
1239 */
1240 static inline s64
1241 ia64_pal_mc_expected (u64 expected, u64 *previous)
1242 {
1243 struct ia64_pal_retval iprv;
1244 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1245 if (previous)
1246 *previous = iprv.v0;
1247 return iprv.status;
1248 }
1249
1250 /* Register a platform dependent location with PAL to which it can save
1251 * minimal processor state in the event of a machine check or initialization
1252 * event.
1253 */
1254 static inline s64
1255 ia64_pal_mc_register_mem (u64 physical_addr)
1256 {
1257 struct ia64_pal_retval iprv;
1258 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1259 return iprv.status;
1260 }
1261
1262 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1263 * and resume execution
1264 */
1265 static inline s64
1266 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1267 {
1268 struct ia64_pal_retval iprv;
1269 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1270 return iprv.status;
1271 }
1272
1273 /* Return the memory attributes implemented by the processor */
1274 static inline s64
1275 ia64_pal_mem_attrib (u64 *mem_attrib)
1276 {
1277 struct ia64_pal_retval iprv;
1278 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1279 if (mem_attrib)
1280 *mem_attrib = iprv.v0 & 0xff;
1281 return iprv.status;
1282 }
1283
1284 /* Return the amount of memory needed for second phase of processor
1285 * self-test and the required alignment of memory.
1286 */
1287 static inline s64
1288 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1289 {
1290 struct ia64_pal_retval iprv;
1291 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1292 if (bytes_needed)
1293 *bytes_needed = iprv.v0;
1294 if (alignment)
1295 *alignment = iprv.v1;
1296 return iprv.status;
1297 }
1298
1299 typedef union pal_perf_mon_info_u {
1300 u64 ppmi_data;
1301 struct {
1302 u64 generic : 8,
1303 width : 8,
1304 cycles : 8,
1305 retired : 8,
1306 reserved : 32;
1307 } pal_perf_mon_info_s;
1308 } pal_perf_mon_info_u_t;
1309
1310 /* Return the performance monitor information about what can be counted
1311 * and how to configure the monitors to count the desired events.
1312 */
1313 static inline s64
1314 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1315 {
1316 struct ia64_pal_retval iprv;
1317 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1318 if (pm_info)
1319 pm_info->ppmi_data = iprv.v0;
1320 return iprv.status;
1321 }
1322
1323 /* Specifies the physical address of the processor interrupt block
1324 * and I/O port space.
1325 */
1326 static inline s64
1327 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1328 {
1329 struct ia64_pal_retval iprv;
1330 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1331 return iprv.status;
1332 }
1333
1334 /* Set the SAL PMI entrypoint in memory */
1335 static inline s64
1336 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1337 {
1338 struct ia64_pal_retval iprv;
1339 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1340 return iprv.status;
1341 }
1342
1343 struct pal_features_s;
1344 /* Provide information about configurable processor features */
1345 static inline s64
1346 ia64_pal_proc_get_features (u64 *features_avail,
1347 u64 *features_status,
1348 u64 *features_control)
1349 {
1350 struct ia64_pal_retval iprv;
1351 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1352 if (iprv.status == 0) {
1353 *features_avail = iprv.v0;
1354 *features_status = iprv.v1;
1355 *features_control = iprv.v2;
1356 }
1357 return iprv.status;
1358 }
1359
1360 /* Enable/disable processor dependent features */
1361 static inline s64
1362 ia64_pal_proc_set_features (u64 feature_select)
1363 {
1364 struct ia64_pal_retval iprv;
1365 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1366 return iprv.status;
1367 }
1368
1369 /*
1370 * Put everything in a struct so we avoid the global offset table whenever
1371 * possible.
1372 */
1373 typedef struct ia64_ptce_info_s {
1374 u64 base;
1375 u32 count[2];
1376 u32 stride[2];
1377 } ia64_ptce_info_t;
1378
1379 /* Return the information required for the architected loop used to purge
1380 * (initialize) the entire TC
1381 */
1382 static inline s64
1383 ia64_get_ptce (ia64_ptce_info_t *ptce)
1384 {
1385 struct ia64_pal_retval iprv;
1386
1387 if (!ptce)
1388 return -1;
1389
1390 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1391 if (iprv.status == 0) {
1392 ptce->base = iprv.v0;
1393 ptce->count[0] = iprv.v1 >> 32;
1394 ptce->count[1] = iprv.v1 & 0xffffffff;
1395 ptce->stride[0] = iprv.v2 >> 32;
1396 ptce->stride[1] = iprv.v2 & 0xffffffff;
1397 }
1398 return iprv.status;
1399 }
1400
1401 /* Return info about implemented application and control registers. */
1402 static inline s64
1403 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1404 {
1405 struct ia64_pal_retval iprv;
1406 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1407 if (reg_info_1)
1408 *reg_info_1 = iprv.v0;
1409 if (reg_info_2)
1410 *reg_info_2 = iprv.v1;
1411 return iprv.status;
1412 }
1413
1414 typedef union pal_hints_u {
1415 u64 ph_data;
1416 struct {
1417 u64 si : 1,
1418 li : 1,
1419 reserved : 62;
1420 } pal_hints_s;
1421 } pal_hints_u_t;
1422
1423 /* Return information about the register stack and RSE for this processor
1424 * implementation.
1425 */
1426 static inline s64
1427 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1428 {
1429 struct ia64_pal_retval iprv;
1430 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1431 if (num_phys_stacked)
1432 *num_phys_stacked = iprv.v0;
1433 if (hints)
1434 hints->ph_data = iprv.v1;
1435 return iprv.status;
1436 }
1437
1438 /*
1439 * Set the current hardware resource sharing policy of the processor
1440 */
1441 static inline s64
1442 ia64_pal_set_hw_policy (u64 policy)
1443 {
1444 struct ia64_pal_retval iprv;
1445 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1446 return iprv.status;
1447 }
1448
1449 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1450 * suspended, but cause cache and TLB coherency to be maintained.
1451 * This is usually called in IA-32 mode.
1452 */
1453 static inline s64
1454 ia64_pal_shutdown (void)
1455 {
1456 struct ia64_pal_retval iprv;
1457 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1458 return iprv.status;
1459 }
1460
1461 /* Perform the second phase of processor self-test. */
1462 static inline s64
1463 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1464 {
1465 struct ia64_pal_retval iprv;
1466 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1467 if (self_test_state)
1468 *self_test_state = iprv.v0;
1469 return iprv.status;
1470 }
1471
1472 typedef union pal_version_u {
1473 u64 pal_version_val;
1474 struct {
1475 u64 pv_pal_b_rev : 8;
1476 u64 pv_pal_b_model : 8;
1477 u64 pv_reserved1 : 8;
1478 u64 pv_pal_vendor : 8;
1479 u64 pv_pal_a_rev : 8;
1480 u64 pv_pal_a_model : 8;
1481 u64 pv_reserved2 : 16;
1482 } pal_version_s;
1483 } pal_version_u_t;
1484
1485
1486 /*
1487 * Return PAL version information. While the documentation states that
1488 * PAL_VERSION can be called in either physical or virtual mode, some
1489 * implementations only allow physical calls. We don't call it very often,
1490 * so the overhead isn't worth eliminating.
1491 */
1492 static inline s64
1493 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1494 {
1495 struct ia64_pal_retval iprv;
1496 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1497 if (pal_min_version)
1498 pal_min_version->pal_version_val = iprv.v0;
1499
1500 if (pal_cur_version)
1501 pal_cur_version->pal_version_val = iprv.v1;
1502
1503 return iprv.status;
1504 }
1505
1506 typedef union pal_tc_info_u {
1507 u64 pti_val;
1508 struct {
1509 u64 num_sets : 8,
1510 associativity : 8,
1511 num_entries : 16,
1512 pf : 1,
1513 unified : 1,
1514 reduce_tr : 1,
1515 reserved : 29;
1516 } pal_tc_info_s;
1517 } pal_tc_info_u_t;
1518
1519 #define tc_reduce_tr pal_tc_info_s.reduce_tr
1520 #define tc_unified pal_tc_info_s.unified
1521 #define tc_pf pal_tc_info_s.pf
1522 #define tc_num_entries pal_tc_info_s.num_entries
1523 #define tc_associativity pal_tc_info_s.associativity
1524 #define tc_num_sets pal_tc_info_s.num_sets
1525
1526
1527 /* Return information about the virtual memory characteristics of the processor
1528 * implementation.
1529 */
1530 static inline s64
1531 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1532 {
1533 struct ia64_pal_retval iprv;
1534 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1535 if (tc_info)
1536 tc_info->pti_val = iprv.v0;
1537 if (tc_pages)
1538 *tc_pages = iprv.v1;
1539 return iprv.status;
1540 }
1541
1542 /* Get page size information about the virtual memory characteristics of the processor
1543 * implementation.
1544 */
1545 static inline s64
1546 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1547 {
1548 struct ia64_pal_retval iprv;
1549 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1550 if (tr_pages)
1551 *tr_pages = iprv.v0;
1552 if (vw_pages)
1553 *vw_pages = iprv.v1;
1554 return iprv.status;
1555 }
1556
1557 typedef union pal_vm_info_1_u {
1558 u64 pvi1_val;
1559 struct {
1560 u64 vw : 1,
1561 phys_add_size : 7,
1562 key_size : 8,
1563 max_pkr : 8,
1564 hash_tag_id : 8,
1565 max_dtr_entry : 8,
1566 max_itr_entry : 8,
1567 max_unique_tcs : 8,
1568 num_tc_levels : 8;
1569 } pal_vm_info_1_s;
1570 } pal_vm_info_1_u_t;
1571
1572 #define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */
1573
1574 typedef union pal_vm_info_2_u {
1575 u64 pvi2_val;
1576 struct {
1577 u64 impl_va_msb : 8,
1578 rid_size : 8,
1579 max_purges : 16,
1580 reserved : 32;
1581 } pal_vm_info_2_s;
1582 } pal_vm_info_2_u_t;
1583
1584 /* Get summary information about the virtual memory characteristics of the processor
1585 * implementation.
1586 */
1587 static inline s64
1588 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1589 {
1590 struct ia64_pal_retval iprv;
1591 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1592 if (vm_info_1)
1593 vm_info_1->pvi1_val = iprv.v0;
1594 if (vm_info_2)
1595 vm_info_2->pvi2_val = iprv.v1;
1596 return iprv.status;
1597 }
1598
1599 typedef union pal_itr_valid_u {
1600 u64 piv_val;
1601 struct {
1602 u64 access_rights_valid : 1,
1603 priv_level_valid : 1,
1604 dirty_bit_valid : 1,
1605 mem_attr_valid : 1,
1606 reserved : 60;
1607 } pal_tr_valid_s;
1608 } pal_tr_valid_u_t;
1609
1610 /* Read a translation register */
1611 static inline s64
1612 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1613 {
1614 struct ia64_pal_retval iprv;
1615 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1616 if (tr_valid)
1617 tr_valid->piv_val = iprv.v0;
1618 return iprv.status;
1619 }
1620
1621 /*
1622 * PAL_PREFETCH_VISIBILITY transaction types
1623 */
1624 #define PAL_VISIBILITY_VIRTUAL 0
1625 #define PAL_VISIBILITY_PHYSICAL 1
1626
1627 /*
1628 * PAL_PREFETCH_VISIBILITY return codes
1629 */
1630 #define PAL_VISIBILITY_OK 1
1631 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1632 #define PAL_VISIBILITY_INVAL_ARG -2
1633 #define PAL_VISIBILITY_ERROR -3
1634
1635 static inline s64
1636 ia64_pal_prefetch_visibility (s64 trans_type)
1637 {
1638 struct ia64_pal_retval iprv;
1639 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1640 return iprv.status;
1641 }
1642
1643 /* data structure for getting information on logical to physical mappings */
1644 typedef union pal_log_overview_u {
1645 struct {
1646 u64 num_log :16, /* Total number of logical
1647 * processors on this die
1648 */
1649 tpc :8, /* Threads per core */
1650 reserved3 :8, /* Reserved */
1651 cpp :8, /* Cores per processor */
1652 reserved2 :8, /* Reserved */
1653 ppid :8, /* Physical processor ID */
1654 reserved1 :8; /* Reserved */
1655 } overview_bits;
1656 u64 overview_data;
1657 } pal_log_overview_t;
1658
1659 typedef union pal_proc_n_log_info1_u{
1660 struct {
1661 u64 tid :16, /* Thread id */
1662 reserved2 :16, /* Reserved */
1663 cid :16, /* Core id */
1664 reserved1 :16; /* Reserved */
1665 } ppli1_bits;
1666 u64 ppli1_data;
1667 } pal_proc_n_log_info1_t;
1668
1669 typedef union pal_proc_n_log_info2_u {
1670 struct {
1671 u64 la :16, /* Logical address */
1672 reserved :48; /* Reserved */
1673 } ppli2_bits;
1674 u64 ppli2_data;
1675 } pal_proc_n_log_info2_t;
1676
1677 typedef struct pal_logical_to_physical_s
1678 {
1679 pal_log_overview_t overview;
1680 pal_proc_n_log_info1_t ppli1;
1681 pal_proc_n_log_info2_t ppli2;
1682 } pal_logical_to_physical_t;
1683
1684 #define overview_num_log overview.overview_bits.num_log
1685 #define overview_tpc overview.overview_bits.tpc
1686 #define overview_cpp overview.overview_bits.cpp
1687 #define overview_ppid overview.overview_bits.ppid
1688 #define log1_tid ppli1.ppli1_bits.tid
1689 #define log1_cid ppli1.ppli1_bits.cid
1690 #define log2_la ppli2.ppli2_bits.la
1691
1692 /* Get information on logical to physical processor mappings. */
1693 static inline s64
1694 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1695 {
1696 struct ia64_pal_retval iprv;
1697
1698 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1699
1700 if (iprv.status == PAL_STATUS_SUCCESS)
1701 {
1702 mapping->overview.overview_data = iprv.v0;
1703 mapping->ppli1.ppli1_data = iprv.v1;
1704 mapping->ppli2.ppli2_data = iprv.v2;
1705 }
1706
1707 return iprv.status;
1708 }
1709
1710 typedef struct pal_cache_shared_info_s
1711 {
1712 u64 num_shared;
1713 pal_proc_n_log_info1_t ppli1;
1714 pal_proc_n_log_info2_t ppli2;
1715 } pal_cache_shared_info_t;
1716
1717 /* Get information on logical to physical processor mappings. */
1718 static inline s64
1719 ia64_pal_cache_shared_info(u64 level,
1720 u64 type,
1721 u64 proc_number,
1722 pal_cache_shared_info_t *info)
1723 {
1724 struct ia64_pal_retval iprv;
1725
1726 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1727
1728 if (iprv.status == PAL_STATUS_SUCCESS) {
1729 info->num_shared = iprv.v0;
1730 info->ppli1.ppli1_data = iprv.v1;
1731 info->ppli2.ppli2_data = iprv.v2;
1732 }
1733
1734 return iprv.status;
1735 }
1736 #endif /* __ASSEMBLY__ */
1737
1738 #endif /* _ASM_IA64_PAL_H */
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