| blob | c602f884f182ee91c7ce2a71fe77ab4071fb0edd |
1 /*
2 * NetChip 2280 high/full speed USB device controller.
3 * Unlike many such controllers, this one talks PCI.
4 */
5 #ifndef __LINUX_USB_NET2280_H
6 #define __LINUX_USB_NET2280_H
8 /*
9 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
10 * Copyright (C) 2003 David Brownell
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
27 /*-------------------------------------------------------------------------*/
29 /* NET2280 MEMORY MAPPED REGISTERS
30 *
31 * The register layout came from the chip documentation, and the bit
32 * number definitions were extracted from chip specification.
33 *
34 * Use the shift operator ('<<') to build bit masks, with readl/writel
35 * to access the registers through PCI.
36 */
38 /* main registers, BAR0 + 0x0000 */
40 // offset 0x0000
41 u32 devinit;
42 #define LOCAL_CLOCK_FREQUENCY 8
43 #define FORCE_PCI_RESET 7
44 #define PCI_ID 6
45 #define PCI_ENABLE 5
46 #define FIFO_SOFT_RESET 4
47 #define CFG_SOFT_RESET 3
48 #define PCI_SOFT_RESET 2
49 #define USB_SOFT_RESET 1
50 #define M8051_RESET 0
51 u32 eectl;
52 #define EEPROM_ADDRESS_WIDTH 23
53 #define EEPROM_CHIP_SELECT_ACTIVE 22
54 #define EEPROM_PRESENT 21
55 #define EEPROM_VALID 20
56 #define EEPROM_BUSY 19
57 #define EEPROM_CHIP_SELECT_ENABLE 18
58 #define EEPROM_BYTE_READ_START 17
59 #define EEPROM_BYTE_WRITE_START 16
60 #define EEPROM_READ_DATA 8
61 #define EEPROM_WRITE_DATA 0
62 u32 eeclkfreq;
63 u32 _unused0;
64 // offset 0x0010
67 #define SETUP_PACKET_INTERRUPT_ENABLE 7
68 #define ENDPOINT_F_INTERRUPT_ENABLE 6
69 #define ENDPOINT_E_INTERRUPT_ENABLE 5
70 #define ENDPOINT_D_INTERRUPT_ENABLE 4
71 #define ENDPOINT_C_INTERRUPT_ENABLE 3
72 #define ENDPOINT_B_INTERRUPT_ENABLE 2
73 #define ENDPOINT_A_INTERRUPT_ENABLE 1
74 #define ENDPOINT_0_INTERRUPT_ENABLE 0
75 u32 pciirqenb1;
76 #define PCI_INTERRUPT_ENABLE 31
77 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
78 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
79 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
80 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
81 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
82 #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18
83 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
84 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
85 #define GPIO_INTERRUPT_ENABLE 13
86 #define DMA_D_INTERRUPT_ENABLE 12
87 #define DMA_C_INTERRUPT_ENABLE 11
88 #define DMA_B_INTERRUPT_ENABLE 10
89 #define DMA_A_INTERRUPT_ENABLE 9
90 #define EEPROM_DONE_INTERRUPT_ENABLE 8
91 #define VBUS_INTERRUPT_ENABLE 7
92 #define CONTROL_STATUS_INTERRUPT_ENABLE 6
93 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
94 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
95 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
96 #define RESUME_INTERRUPT_ENABLE 1
97 #define SOF_INTERRUPT_ENABLE 0
99 #define SETUP_PACKET_INTERRUPT_ENABLE 7
100 #define ENDPOINT_F_INTERRUPT_ENABLE 6
101 #define ENDPOINT_E_INTERRUPT_ENABLE 5
102 #define ENDPOINT_D_INTERRUPT_ENABLE 4
103 #define ENDPOINT_C_INTERRUPT_ENABLE 3
104 #define ENDPOINT_B_INTERRUPT_ENABLE 2
105 #define ENDPOINT_A_INTERRUPT_ENABLE 1
106 #define ENDPOINT_0_INTERRUPT_ENABLE 0
107 u32 cpu_irqenb1;
108 #define CPU_INTERRUPT_ENABLE 31
109 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
110 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
111 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
112 #define PCI_INTA_INTERRUPT_ENABLE 24
113 #define PCI_PME_INTERRUPT_ENABLE 23
114 #define PCI_SERR_INTERRUPT_ENABLE 22
115 #define PCI_PERR_INTERRUPT_ENABLE 21
116 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
117 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
118 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
119 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
120 #define GPIO_INTERRUPT_ENABLE 13
121 #define DMA_D_INTERRUPT_ENABLE 12
122 #define DMA_C_INTERRUPT_ENABLE 11
123 #define DMA_B_INTERRUPT_ENABLE 10
124 #define DMA_A_INTERRUPT_ENABLE 9
125 #define EEPROM_DONE_INTERRUPT_ENABLE 8
126 #define VBUS_INTERRUPT_ENABLE 7
127 #define CONTROL_STATUS_INTERRUPT_ENABLE 6
128 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
129 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
130 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
131 #define RESUME_INTERRUPT_ENABLE 1
132 #define SOF_INTERRUPT_ENABLE 0
134 // offset 0x0020
135 u32 _unused1;
136 u32 usbirqenb1;
137 #define USB_INTERRUPT_ENABLE 31
138 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
139 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
140 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
141 #define PCI_INTA_INTERRUPT_ENABLE 24
142 #define PCI_PME_INTERRUPT_ENABLE 23
143 #define PCI_SERR_INTERRUPT_ENABLE 22
144 #define PCI_PERR_INTERRUPT_ENABLE 21
145 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
146 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
147 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
148 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
149 #define GPIO_INTERRUPT_ENABLE 13
150 #define DMA_D_INTERRUPT_ENABLE 12
151 #define DMA_C_INTERRUPT_ENABLE 11
152 #define DMA_B_INTERRUPT_ENABLE 10
153 #define DMA_A_INTERRUPT_ENABLE 9
154 #define EEPROM_DONE_INTERRUPT_ENABLE 8
155 #define VBUS_INTERRUPT_ENABLE 7
156 #define CONTROL_STATUS_INTERRUPT_ENABLE 6
157 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
158 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
159 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
160 #define RESUME_INTERRUPT_ENABLE 1
161 #define SOF_INTERRUPT_ENABLE 0
162 u32 irqstat0;
163 #define INTA_ASSERTED 12
164 #define SETUP_PACKET_INTERRUPT 7
165 #define ENDPOINT_F_INTERRUPT 6
166 #define ENDPOINT_E_INTERRUPT 5
167 #define ENDPOINT_D_INTERRUPT 4
168 #define ENDPOINT_C_INTERRUPT 3
169 #define ENDPOINT_B_INTERRUPT 2
170 #define ENDPOINT_A_INTERRUPT 1
171 #define ENDPOINT_0_INTERRUPT 0
172 u32 irqstat1;
173 #define POWER_STATE_CHANGE_INTERRUPT 27
174 #define PCI_ARBITER_TIMEOUT_INTERRUPT 26
175 #define PCI_PARITY_ERROR_INTERRUPT 25
176 #define PCI_INTA_INTERRUPT 24
177 #define PCI_PME_INTERRUPT 23
178 #define PCI_SERR_INTERRUPT 22
179 #define PCI_PERR_INTERRUPT 21
180 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20
181 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19
182 #define PCI_RETRY_ABORT_INTERRUPT 17
183 #define PCI_MASTER_CYCLE_DONE_INTERRUPT 16
184 #define SOF_DOWN_INTERRUPT 14
185 #define GPIO_INTERRUPT 13
186 #define DMA_D_INTERRUPT 12
187 #define DMA_C_INTERRUPT 11
188 #define DMA_B_INTERRUPT 10
189 #define DMA_A_INTERRUPT 9
190 #define EEPROM_DONE_INTERRUPT 8
191 #define VBUS_INTERRUPT 7
192 #define CONTROL_STATUS_INTERRUPT 6
193 #define ROOT_PORT_RESET_INTERRUPT 4
194 #define SUSPEND_REQUEST_INTERRUPT 3
195 #define SUSPEND_REQUEST_CHANGE_INTERRUPT 2
196 #define RESUME_INTERRUPT 1
197 #define SOF_INTERRUPT 0
198 // offset 0x0030
199 u32 idxaddr;
200 u32 idxdata;
201 u32 fifoctl;
202 #define PCI_BASE2_RANGE 16
203 #define IGNORE_FIFO_AVAILABILITY 3
204 #define PCI_BASE2_SELECT 2
205 #define FIFO_CONFIGURATION_SELECT 0
206 u32 _unused2;
207 // offset 0x0040
208 u32 memaddr;
209 #define START 28
210 #define DIRECTION 27
211 #define FIFO_DIAGNOSTIC_SELECT 24
212 #define MEMORY_ADDRESS 0
213 u32 memdata0;
214 u32 memdata1;
215 u32 _unused3;
216 // offset 0x0050
217 u32 gpioctl;
218 #define GPIO3_LED_SELECT 12
219 #define GPIO3_INTERRUPT_ENABLE 11
220 #define GPIO2_INTERRUPT_ENABLE 10
221 #define GPIO1_INTERRUPT_ENABLE 9
222 #define GPIO0_INTERRUPT_ENABLE 8
223 #define GPIO3_OUTPUT_ENABLE 7
224 #define GPIO2_OUTPUT_ENABLE 6
225 #define GPIO1_OUTPUT_ENABLE 5
226 #define GPIO0_OUTPUT_ENABLE 4
227 #define GPIO3_DATA 3
228 #define GPIO2_DATA 2
229 #define GPIO1_DATA 1
230 #define GPIO0_DATA 0
231 u32 gpiostat;
232 #define GPIO3_INTERRUPT 3
233 #define GPIO2_INTERRUPT 2
234 #define GPIO1_INTERRUPT 1
235 #define GPIO0_INTERRUPT 0
238 /* usb control, BAR0 + 0x0080 */
240 // offset 0x0080
241 u32 stdrsp;
242 #define STALL_UNSUPPORTED_REQUESTS 31
243 #define SET_TEST_MODE 16
244 #define GET_OTHER_SPEED_CONFIGURATION 15
245 #define GET_DEVICE_QUALIFIER 14
246 #define SET_ADDRESS 13
247 #define ENDPOINT_SET_CLEAR_HALT 12
248 #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11
249 #define GET_STRING_DESCRIPTOR_2 10
250 #define GET_STRING_DESCRIPTOR_1 9
251 #define GET_STRING_DESCRIPTOR_0 8
252 #define GET_SET_INTERFACE 6
253 #define GET_SET_CONFIGURATION 5
254 #define GET_CONFIGURATION_DESCRIPTOR 4
255 #define GET_DEVICE_DESCRIPTOR 3
256 #define GET_ENDPOINT_STATUS 2
257 #define GET_INTERFACE_STATUS 1
258 #define GET_DEVICE_STATUS 0
259 u32 prodvendid;
260 #define PRODUCT_ID 16
261 #define VENDOR_ID 0
262 u32 relnum;
263 u32 usbctl;
264 #define SERIAL_NUMBER_INDEX 16
265 #define PRODUCT_ID_STRING_ENABLE 13
266 #define VENDOR_ID_STRING_ENABLE 12
267 #define USB_ROOT_PORT_WAKEUP_ENABLE 11
268 #define VBUS_PIN 10
269 #define TIMED_DISCONNECT 9
270 #define SUSPEND_IMMEDIATELY 7
271 #define SELF_POWERED_USB_DEVICE 6
272 #define REMOTE_WAKEUP_SUPPORT 5
273 #define PME_POLARITY 4
274 #define USB_DETECT_ENABLE 3
275 #define PME_WAKEUP_ENABLE 2
276 #define DEVICE_REMOTE_WAKEUP_ENABLE 1
277 #define SELF_POWERED_STATUS 0
278 // offset 0x0090
279 u32 usbstat;
280 #define HIGH_SPEED 7
281 #define FULL_SPEED 6
282 #define GENERATE_RESUME 5
283 #define GENERATE_DEVICE_REMOTE_WAKEUP 4
284 u32 xcvrdiag;
285 #define FORCE_HIGH_SPEED_MODE 31
286 #define FORCE_FULL_SPEED_MODE 30
287 #define USB_TEST_MODE 24
288 #define LINE_STATE 16
289 #define TRANSCEIVER_OPERATION_MODE 2
290 #define TRANSCEIVER_SELECT 1
291 #define TERMINATION_SELECT 0
292 u32 setup0123;
293 u32 setup4567;
294 // offset 0x0090
295 u32 _unused0;
296 u32 ouraddr;
297 #define FORCE_IMMEDIATE 7
298 #define OUR_USB_ADDRESS 0
299 u32 ourconfig;
302 /* pci control, BAR0 + 0x0100 */
304 // offset 0x0100
305 u32 pcimstctl;
306 #define PCI_ARBITER_PARK_SELECT 13
307 #define PCI_MULTI LEVEL_ARBITER 12
308 #define PCI_RETRY_ABORT_ENABLE 11
309 #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10
310 #define DMA_READ_MULTIPLE_ENABLE 9
311 #define DMA_READ_LINE_ENABLE 8
312 #define PCI_MASTER_COMMAND_SELECT 6
313 #define MEM_READ_OR_WRITE 0
314 #define IO_READ_OR_WRITE 1
315 #define CFG_READ_OR_WRITE 2
316 #define PCI_MASTER_START 5
317 #define PCI_MASTER_READ_WRITE 4
318 #define PCI_MASTER_WRITE 0
319 #define PCI_MASTER_READ 1
320 #define PCI_MASTER_BYTE_WRITE_ENABLES 0
321 u32 pcimstaddr;
322 u32 pcimstdata;
323 u32 pcimststat;
324 #define PCI_ARBITER_CLEAR 2
325 #define PCI_EXTERNAL_ARBITER 1
326 #define PCI_HOST_MODE 0
329 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
330 * for channels 0..3. see also struct net2280_dma: descriptor
331 * that can be loaded into some of these registers.
332 */
334 // offset 0x0180, 0x01a0, 0x01c0, 0x01e0,
335 u32 dmactl;
336 #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25
337 #define DMA_CLEAR_COUNT_ENABLE 21
338 #define DESCRIPTOR_POLLING_RATE 19
339 #define POLL_CONTINUOUS 0
340 #define POLL_1_USEC 1
341 #define POLL_100_USEC 2
342 #define POLL_1_MSEC 3
343 #define DMA_VALID_BIT_POLLING_ENABLE 18
344 #define DMA_VALID_BIT_ENABLE 17
345 #define DMA_SCATTER_GATHER_ENABLE 16
346 #define DMA_OUT_AUTO_START_ENABLE 4
347 #define DMA_PREEMPT_ENABLE 3
348 #define DMA_FIFO_VALIDATE 2
349 #define DMA_ENABLE 1
350 #define DMA_ADDRESS_HOLD 0
351 u32 dmastat;
352 #define DMA_ABORT_DONE_INTERRUPT 27
353 #define DMA_SCATTER_GATHER_DONE_INTERRUPT 25
354 #define DMA_TRANSACTION_DONE_INTERRUPT 24
355 #define DMA_ABORT 1
356 #define DMA_START 0
358 // offset 0x0190, 0x01b0, 0x01d0, 0x01f0,
359 u32 dmacount;
360 #define VALID_BIT 31
361 #define DMA_DIRECTION 30
362 #define DMA_DONE_INTERRUPT_ENABLE 29
363 #define END_OF_CHAIN 28
364 #define DMA_BYTE_COUNT_MASK ((1<<24)-1)
365 #define DMA_BYTE_COUNT 0
366 u32 dmaaddr;
367 u32 dmadesc;
368 u32 _unused1;
371 /* dedicated endpoint registers, BAR0 + 0x0200 */
374 // offset 0x0200, 0x0210, 0x220, 0x230, 0x240
375 u32 dep_cfg;
376 // offset 0x0204, 0x0214, 0x224, 0x234, 0x244
377 u32 dep_rsp;
381 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
382 * like this, for ep0 then the configurable endpoints A..F
383 * ep0 reserved for control; E and F have only 64 bytes of fifo
384 */
386 // offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0
387 u32 ep_cfg;
388 #define ENDPOINT_BYTE_COUNT 16
389 #define ENDPOINT_ENABLE 10
390 #define ENDPOINT_TYPE 8
391 #define ENDPOINT_DIRECTION 7
392 #define ENDPOINT_NUMBER 0
393 u32 ep_rsp;
394 #define SET_NAK_OUT_PACKETS 15
395 #define SET_EP_HIDE_STATUS_PHASE 14
396 #define SET_EP_FORCE_CRC_ERROR 13
397 #define SET_INTERRUPT_MODE 12
398 #define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11
399 #define SET_NAK_OUT_PACKETS_MODE 10
400 #define SET_ENDPOINT_TOGGLE 9
401 #define SET_ENDPOINT_HALT 8
402 #define CLEAR_NAK_OUT_PACKETS 7
403 #define CLEAR_EP_HIDE_STATUS_PHASE 6
404 #define CLEAR_EP_FORCE_CRC_ERROR 5
405 #define CLEAR_INTERRUPT_MODE 4
406 #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3
407 #define CLEAR_NAK_OUT_PACKETS_MODE 2
408 #define CLEAR_ENDPOINT_TOGGLE 1
409 #define CLEAR_ENDPOINT_HALT 0
410 u32 ep_irqenb;
411 #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6
412 #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5
413 #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
414 #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
415 #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1
416 #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
417 u32 ep_stat;
418 #define FIFO_VALID_COUNT 24
419 #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22
420 #define TIMEOUT 21
421 #define USB_STALL_SENT 20
422 #define USB_IN_NAK_SENT 19
423 #define USB_IN_ACK_RCVD 18
424 #define USB_OUT_PING_NAK_SENT 17
425 #define USB_OUT_ACK_SENT 16
426 #define FIFO_OVERFLOW 13
427 #define FIFO_UNDERFLOW 12
428 #define FIFO_FULL 11
429 #define FIFO_EMPTY 10
430 #define FIFO_FLUSH 9
431 #define SHORT_PACKET_OUT_DONE_INTERRUPT 6
432 #define SHORT_PACKET_TRANSFERRED_INTERRUPT 5
433 #define NAK_OUT_PACKETS 4
434 #define DATA_PACKET_RECEIVED_INTERRUPT 3
435 #define DATA_PACKET_TRANSMITTED_INTERRUPT 2
436 #define DATA_OUT_PING_TOKEN_INTERRUPT 1
437 #define DATA_IN_TOKEN_INTERRUPT 0
438 // offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0
439 u32 ep_avail;
440 u32 ep_data;