2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 unsigned int pci_pm_d3_delay
= 10;
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus
* bus
)
34 struct list_head
*tmp
;
37 max
= bus
->subordinate
;
38 list_for_each(tmp
, &bus
->children
) {
39 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
49 * pci_max_busnr - returns maximum PCI bus number
51 * Returns the highest PCI bus number present in the system global list of
54 unsigned char __devinit
57 struct pci_bus
*bus
= NULL
;
61 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
62 n
= pci_bus_max_busnr(bus
);
71 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 pos
, int cap
)
77 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
81 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
87 pos
+= PCI_CAP_LIST_NEXT
;
92 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
94 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
95 pos
+ PCI_CAP_LIST_NEXT
, cap
);
97 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
99 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
104 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
105 if (!(status
& PCI_STATUS_CAP_LIST
))
109 case PCI_HEADER_TYPE_NORMAL
:
110 case PCI_HEADER_TYPE_BRIDGE
:
111 pos
= PCI_CAPABILITY_LIST
;
113 case PCI_HEADER_TYPE_CARDBUS
:
114 pos
= PCI_CB_CAPABILITY_LIST
;
119 return __pci_find_next_cap(bus
, devfn
, pos
, cap
);
123 * pci_find_capability - query for devices' capabilities
124 * @dev: PCI device to query
125 * @cap: capability code
127 * Tell if a device supports a given PCI capability.
128 * Returns the address of the requested capability structure within the
129 * device's PCI configuration space or 0 in case the device does not
130 * support it. Possible values for @cap:
132 * %PCI_CAP_ID_PM Power Management
133 * %PCI_CAP_ID_AGP Accelerated Graphics Port
134 * %PCI_CAP_ID_VPD Vital Product Data
135 * %PCI_CAP_ID_SLOTID Slot Identification
136 * %PCI_CAP_ID_MSI Message Signalled Interrupts
137 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
138 * %PCI_CAP_ID_PCIX PCI-X
139 * %PCI_CAP_ID_EXP PCI Express
141 int pci_find_capability(struct pci_dev
*dev
, int cap
)
143 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
147 * pci_bus_find_capability - query for devices' capabilities
148 * @bus: the PCI bus to query
149 * @devfn: PCI device to query
150 * @cap: capability code
152 * Like pci_find_capability() but works for pci devices that do not have a
153 * pci_dev structure set up yet.
155 * Returns the address of the requested capability structure within the
156 * device's PCI configuration space or 0 in case the device does not
159 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
163 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
165 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
169 * pci_find_ext_capability - Find an extended capability
170 * @dev: PCI device to query
171 * @cap: capability code
173 * Returns the address of the requested extended capability structure
174 * within the device's PCI configuration space or 0 if the device does
175 * not support it. Possible values for @cap:
177 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
178 * %PCI_EXT_CAP_ID_VC Virtual Channel
179 * %PCI_EXT_CAP_ID_DSN Device Serial Number
180 * %PCI_EXT_CAP_ID_PWR Power Budgeting
182 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
185 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
188 if (dev
->cfg_size
<= 256)
191 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
195 * If we have no capabilities, this is indicated by cap ID,
196 * cap version and next pointer all being 0.
202 if (PCI_EXT_CAP_ID(header
) == cap
)
205 pos
= PCI_EXT_CAP_NEXT(header
);
209 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
215 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
218 * pci_find_parent_resource - return resource region of parent bus of given region
219 * @dev: PCI device structure contains resources to be searched
220 * @res: child resource record for which parent is sought
222 * For given resource region of given device, return the resource
223 * region of parent bus the given region is contained in or where
224 * it should be allocated from.
227 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
229 const struct pci_bus
*bus
= dev
->bus
;
231 struct resource
*best
= NULL
;
233 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
234 struct resource
*r
= bus
->resource
[i
];
237 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
238 continue; /* Not contained */
239 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
240 continue; /* Wrong type */
241 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
242 return r
; /* Exact match */
243 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
244 best
= r
; /* Approximating prefetchable by non-prefetchable */
250 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
251 * @dev: PCI device to have its BARs restored
253 * Restore the BAR values for a given device, so as to make it
254 * accessible by its driver.
257 pci_restore_bars(struct pci_dev
*dev
)
261 switch (dev
->hdr_type
) {
262 case PCI_HEADER_TYPE_NORMAL
:
265 case PCI_HEADER_TYPE_BRIDGE
:
268 case PCI_HEADER_TYPE_CARDBUS
:
272 /* Should never get here, but just in case... */
276 for (i
= 0; i
< numres
; i
++)
277 pci_update_resource(dev
, &dev
->resource
[i
], i
);
280 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
283 * pci_set_power_state - Set the power state of a PCI device
284 * @dev: PCI device to be suspended
285 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
287 * Transition a device to a new power state, using the Power Management
288 * Capabilities in the device's config space.
291 * -EINVAL if trying to enter a lower state than we're already in.
292 * 0 if we're already in the requested state.
293 * -EIO if device does not support PCI PM.
294 * 0 if we can successfully change the power state.
297 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
299 int pm
, need_restore
= 0;
302 /* bound the state we're entering */
303 if (state
> PCI_D3hot
)
306 /* Validate current state:
307 * Can enter D0 from any state, but if we can only go deeper
308 * to sleep if we're already in a low power state
310 if (state
!= PCI_D0
&& dev
->current_state
> state
) {
311 printk(KERN_ERR
"%s(): %s: state=%d, current state=%d\n",
312 __FUNCTION__
, pci_name(dev
), state
, dev
->current_state
);
314 } else if (dev
->current_state
== state
)
315 return 0; /* we're already there */
318 * If the device or the parent bridge can't support PCI PM, ignore
319 * the request if we're doing anything besides putting it into D0
320 * (which would only happen on boot).
322 if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
325 /* find PCI PM capability in list */
326 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
328 /* abort if the device doesn't support PM capabilities */
332 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
333 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
335 "PCI: %s has unsupported PM cap regs version (%u)\n",
336 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
340 /* check if this device supports the desired state */
341 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
343 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
346 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
348 /* If we're (effectively) in D3, force entire word to 0.
349 * This doesn't affect PME_Status, disables PME_En, and
350 * sets PowerState to 0.
352 switch (dev
->current_state
) {
356 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
359 case PCI_UNKNOWN
: /* Boot-up */
360 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
361 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
363 /* Fall-through: force to D0 */
369 /* enter specified state */
370 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
372 /* Mandatory power management transition delays */
373 /* see PCI PM 1.1 5.6.1 table 18 */
374 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
375 msleep(pci_pm_d3_delay
);
376 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
380 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
381 * Firmware method after native method ?
383 if (platform_pci_set_power_state
)
384 platform_pci_set_power_state(dev
, state
);
386 dev
->current_state
= state
;
388 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
389 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
390 * from D3hot to D0 _may_ perform an internal reset, thereby
391 * going to "D0 Uninitialized" rather than "D0 Initialized".
392 * For example, at least some versions of the 3c905B and the
393 * 3c556B exhibit this behaviour.
395 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
396 * devices in a D3hot state at boot. Consequently, we need to
397 * restore at least the BARs so that the device will be
398 * accessible to its driver.
401 pci_restore_bars(dev
);
406 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
409 * pci_choose_state - Choose the power state of a PCI device
410 * @dev: PCI device to be suspended
411 * @state: target sleep state for the whole system. This is the value
412 * that is passed to suspend() function.
414 * Returns PCI power state suitable for given device and given system
418 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
422 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
425 if (platform_pci_choose_state
) {
426 ret
= platform_pci_choose_state(dev
, state
);
431 switch (state
.event
) {
434 case PM_EVENT_FREEZE
:
435 case PM_EVENT_SUSPEND
:
438 printk("They asked me for state %d\n", state
.event
);
444 EXPORT_SYMBOL(pci_choose_state
);
447 * pci_save_state - save the PCI configuration space of a device before suspending
448 * @dev: - PCI device that we're dealing with
451 pci_save_state(struct pci_dev
*dev
)
454 /* XXX: 100% dword access ok here? */
455 for (i
= 0; i
< 16; i
++)
456 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
457 if ((i
= pci_save_msi_state(dev
)) != 0)
459 if ((i
= pci_save_msix_state(dev
)) != 0)
465 * pci_restore_state - Restore the saved state of a PCI device
466 * @dev: - PCI device that we're dealing with
469 pci_restore_state(struct pci_dev
*dev
)
475 * The Base Address register should be programmed before the command
478 for (i
= 15; i
>= 0; i
--) {
479 pci_read_config_dword(dev
, i
* 4, &val
);
480 if (val
!= dev
->saved_config_space
[i
]) {
481 printk(KERN_DEBUG
"PM: Writing back config space on "
482 "device %s at offset %x (was %x, writing %x)\n",
484 val
, (int)dev
->saved_config_space
[i
]);
485 pci_write_config_dword(dev
,i
* 4,
486 dev
->saved_config_space
[i
]);
489 pci_restore_msi_state(dev
);
490 pci_restore_msix_state(dev
);
495 * pci_enable_device_bars - Initialize some of a device for use
496 * @dev: PCI device to be initialized
497 * @bars: bitmask of BAR's that must be configured
499 * Initialize device before it's used by a driver. Ask low-level code
500 * to enable selected I/O and memory resources. Wake up the device if it
501 * was suspended. Beware, this function can fail.
505 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
509 err
= pci_set_power_state(dev
, PCI_D0
);
510 if (err
< 0 && err
!= -EIO
)
512 err
= pcibios_enable_device(dev
, bars
);
519 * pci_enable_device - Initialize device before it's used by a driver.
520 * @dev: PCI device to be initialized
522 * Initialize device before it's used by a driver. Ask low-level code
523 * to enable I/O and memory. Wake up the device if it was suspended.
524 * Beware, this function can fail.
527 pci_enable_device(struct pci_dev
*dev
)
534 err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
537 pci_fixup_device(pci_fixup_enable
, dev
);
543 * pcibios_disable_device - disable arch specific PCI resources for device dev
544 * @dev: the PCI device to disable
546 * Disables architecture specific PCI resources for the device. This
547 * is the default implementation. Architecture implementations can
550 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
553 * pci_disable_device - Disable PCI device after use
554 * @dev: PCI device to be disabled
556 * Signal to the system that the PCI device is not in use by the system
557 * anymore. This only involves disabling PCI bus-mastering, if active.
560 pci_disable_device(struct pci_dev
*dev
)
564 if (dev
->msi_enabled
)
565 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
567 if (dev
->msix_enabled
)
568 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
571 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
572 if (pci_command
& PCI_COMMAND_MASTER
) {
573 pci_command
&= ~PCI_COMMAND_MASTER
;
574 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
576 dev
->is_busmaster
= 0;
578 pcibios_disable_device(dev
);
583 * pci_enable_wake - enable device to generate PME# when suspended
584 * @dev: - PCI device to operate on
585 * @state: - Current state of device.
586 * @enable: - Flag to enable or disable generation
588 * Set the bits in the device's PM Capabilities to generate PME# when
589 * the system is suspended.
591 * -EIO is returned if device doesn't have PM Capabilities.
592 * -EINVAL is returned if device supports it, but can't generate wake events.
593 * 0 if operation is successful.
596 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
601 /* find PCI PM capability in list */
602 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
604 /* If device doesn't support PM Capabilities, but request is to disable
605 * wake events, it's a nop; otherwise fail */
607 return enable
? -EIO
: 0;
609 /* Check device's ability to generate PME# */
610 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
612 value
&= PCI_PM_CAP_PME_MASK
;
613 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
615 /* Check if it can generate PME# from requested state. */
616 if (!value
|| !(value
& (1 << state
)))
617 return enable
? -EINVAL
: 0;
619 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
621 /* Clear PME_Status by writing 1 to it and enable PME# */
622 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
625 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
627 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
633 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
641 while (dev
->bus
->self
) {
642 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
643 dev
= dev
->bus
->self
;
650 * pci_release_region - Release a PCI bar
651 * @pdev: PCI device whose resources were previously reserved by pci_request_region
652 * @bar: BAR to release
654 * Releases the PCI I/O and memory resources previously reserved by a
655 * successful call to pci_request_region. Call this function only
656 * after all use of the PCI regions has ceased.
658 void pci_release_region(struct pci_dev
*pdev
, int bar
)
660 if (pci_resource_len(pdev
, bar
) == 0)
662 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
663 release_region(pci_resource_start(pdev
, bar
),
664 pci_resource_len(pdev
, bar
));
665 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
666 release_mem_region(pci_resource_start(pdev
, bar
),
667 pci_resource_len(pdev
, bar
));
671 * pci_request_region - Reserved PCI I/O and memory resource
672 * @pdev: PCI device whose resources are to be reserved
673 * @bar: BAR to be reserved
674 * @res_name: Name to be associated with resource.
676 * Mark the PCI region associated with PCI device @pdev BR @bar as
677 * being reserved by owner @res_name. Do not access any
678 * address inside the PCI regions unless this call returns
681 * Returns 0 on success, or %EBUSY on error. A warning
682 * message is also printed on failure.
684 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
686 if (pci_resource_len(pdev
, bar
) == 0)
689 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
690 if (!request_region(pci_resource_start(pdev
, bar
),
691 pci_resource_len(pdev
, bar
), res_name
))
694 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
695 if (!request_mem_region(pci_resource_start(pdev
, bar
),
696 pci_resource_len(pdev
, bar
), res_name
))
703 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%llx@%llx "
705 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
706 bar
+ 1, /* PCI BAR # */
707 (unsigned long long)pci_resource_len(pdev
, bar
),
708 (unsigned long long)pci_resource_start(pdev
, bar
),
715 * pci_release_regions - Release reserved PCI I/O and memory resources
716 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
718 * Releases all PCI I/O and memory resources previously reserved by a
719 * successful call to pci_request_regions. Call this function only
720 * after all use of the PCI regions has ceased.
723 void pci_release_regions(struct pci_dev
*pdev
)
727 for (i
= 0; i
< 6; i
++)
728 pci_release_region(pdev
, i
);
732 * pci_request_regions - Reserved PCI I/O and memory resources
733 * @pdev: PCI device whose resources are to be reserved
734 * @res_name: Name to be associated with resource.
736 * Mark all PCI regions associated with PCI device @pdev as
737 * being reserved by owner @res_name. Do not access any
738 * address inside the PCI regions unless this call returns
741 * Returns 0 on success, or %EBUSY on error. A warning
742 * message is also printed on failure.
744 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
748 for (i
= 0; i
< 6; i
++)
749 if(pci_request_region(pdev
, i
, res_name
))
755 pci_release_region(pdev
, i
);
761 * pci_set_master - enables bus-mastering for device dev
762 * @dev: the PCI device to enable
764 * Enables bus-mastering on the device and calls pcibios_set_master()
765 * to do the needed arch specific settings.
768 pci_set_master(struct pci_dev
*dev
)
772 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
773 if (! (cmd
& PCI_COMMAND_MASTER
)) {
774 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
775 cmd
|= PCI_COMMAND_MASTER
;
776 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
778 dev
->is_busmaster
= 1;
779 pcibios_set_master(dev
);
782 #ifndef HAVE_ARCH_PCI_MWI
783 /* This can be overridden by arch code. */
784 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
787 * pci_generic_prep_mwi - helper function for pci_set_mwi
788 * @dev: the PCI device for which MWI is enabled
790 * Helper function for generic implementation of pcibios_prep_mwi
791 * function. Originally copied from drivers/net/acenic.c.
792 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
794 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
797 pci_generic_prep_mwi(struct pci_dev
*dev
)
801 if (!pci_cache_line_size
)
802 return -EINVAL
; /* The system doesn't support MWI. */
804 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
805 equal to or multiple of the right value. */
806 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
807 if (cacheline_size
>= pci_cache_line_size
&&
808 (cacheline_size
% pci_cache_line_size
) == 0)
811 /* Write the correct value. */
812 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
814 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
815 if (cacheline_size
== pci_cache_line_size
)
818 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
819 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
823 #endif /* !HAVE_ARCH_PCI_MWI */
826 * pci_set_mwi - enables memory-write-invalidate PCI transaction
827 * @dev: the PCI device for which MWI is enabled
829 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
830 * and then calls @pcibios_set_mwi to do the needed arch specific
831 * operations or a generic mwi-prep function.
833 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
836 pci_set_mwi(struct pci_dev
*dev
)
841 #ifdef HAVE_ARCH_PCI_MWI
842 rc
= pcibios_prep_mwi(dev
);
844 rc
= pci_generic_prep_mwi(dev
);
850 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
851 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
852 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
853 cmd
|= PCI_COMMAND_INVALIDATE
;
854 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
861 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
862 * @dev: the PCI device to disable
864 * Disables PCI Memory-Write-Invalidate transaction on the device
867 pci_clear_mwi(struct pci_dev
*dev
)
871 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
872 if (cmd
& PCI_COMMAND_INVALIDATE
) {
873 cmd
&= ~PCI_COMMAND_INVALIDATE
;
874 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
879 * pci_intx - enables/disables PCI INTx for device dev
880 * @pdev: the PCI device to operate on
881 * @enable: boolean: whether to enable or disable PCI INTx
883 * Enables/disables PCI INTx for device dev
886 pci_intx(struct pci_dev
*pdev
, int enable
)
888 u16 pci_command
, new;
890 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
893 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
895 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
898 if (new != pci_command
) {
899 pci_write_config_word(pdev
, PCI_COMMAND
, new);
903 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
905 * These can be overridden by arch-specific implementations
908 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
910 if (!pci_dma_supported(dev
, mask
))
913 dev
->dma_mask
= mask
;
919 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
921 if (!pci_dma_supported(dev
, mask
))
924 dev
->dev
.coherent_dma_mask
= mask
;
930 static int __devinit
pci_init(void)
932 struct pci_dev
*dev
= NULL
;
934 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
935 pci_fixup_device(pci_fixup_final
, dev
);
940 static int __devinit
pci_setup(char *str
)
943 char *k
= strchr(str
, ',');
946 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
947 if (!strcmp(str
, "nomsi")) {
950 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
959 device_initcall(pci_init
);
961 __setup("pci=", pci_setup
);
963 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
964 /* FIXME: Some boxes have multiple ISA bridges! */
965 struct pci_dev
*isa_bridge
;
966 EXPORT_SYMBOL(isa_bridge
);
969 EXPORT_SYMBOL_GPL(pci_restore_bars
);
970 EXPORT_SYMBOL(pci_enable_device_bars
);
971 EXPORT_SYMBOL(pci_enable_device
);
972 EXPORT_SYMBOL(pci_disable_device
);
973 EXPORT_SYMBOL(pci_find_capability
);
974 EXPORT_SYMBOL(pci_bus_find_capability
);
975 EXPORT_SYMBOL(pci_release_regions
);
976 EXPORT_SYMBOL(pci_request_regions
);
977 EXPORT_SYMBOL(pci_release_region
);
978 EXPORT_SYMBOL(pci_request_region
);
979 EXPORT_SYMBOL(pci_set_master
);
980 EXPORT_SYMBOL(pci_set_mwi
);
981 EXPORT_SYMBOL(pci_clear_mwi
);
982 EXPORT_SYMBOL_GPL(pci_intx
);
983 EXPORT_SYMBOL(pci_set_dma_mask
);
984 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
985 EXPORT_SYMBOL(pci_assign_resource
);
986 EXPORT_SYMBOL(pci_find_parent_resource
);
988 EXPORT_SYMBOL(pci_set_power_state
);
989 EXPORT_SYMBOL(pci_save_state
);
990 EXPORT_SYMBOL(pci_restore_state
);
991 EXPORT_SYMBOL(pci_enable_wake
);
995 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
996 EXPORT_SYMBOL(pci_pci_problems
);