drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/smp_lock.h>
  16 #include <linux/pci.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/msi.h>
  19
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22 #include <asm/smp.h>
  23
  24 #include "pci.h"
  25 #include "msi.h"
  26
  27 static struct kmem_cache* msi_cachep;
  28
  29 static int pci_msi_enable = 1;
  30
  31 static int msi_cache_init(void)
  32 {
  33         msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
  34                                         0, SLAB_HWCACHE_ALIGN, NULL, NULL);
  35         if (!msi_cachep)
  36                 return -ENOMEM;
  37
  38         return 0;
  39 }
  40
  41 static void msi_set_enable(struct pci_dev *dev, int enable)
  42 {
  43         int pos;
  44         u16 control;
  45
  46         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
  47         if (pos) {
  48                 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  49                 control &= ~PCI_MSI_FLAGS_ENABLE;
  50                 if (enable)
  51                         control |= PCI_MSI_FLAGS_ENABLE;
  52                 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  53         }
  54 }
  55
  56 static void msix_set_enable(struct pci_dev *dev, int enable)
  57 {
  58         int pos;
  59         u16 control;
  60
  61         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  62         if (pos) {
  63                 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  64                 control &= ~PCI_MSIX_FLAGS_ENABLE;
  65                 if (enable)
  66                         control |= PCI_MSIX_FLAGS_ENABLE;
  67                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
  68         }
  69 }
  70
  71 static void msi_set_mask_bit(unsigned int irq, int flag)
  72 {
  73         struct msi_desc *entry;
  74
  75         entry = get_irq_msi(irq);
  76         BUG_ON(!entry || !entry->dev);
  77         switch (entry->msi_attrib.type) {
  78         case PCI_CAP_ID_MSI:
  79                 if (entry->msi_attrib.maskbit) {
  80                         int pos;
  81                         u32 mask_bits;
  82
  83                         pos = (long)entry->mask_base;
  84                         pci_read_config_dword(entry->dev, pos, &mask_bits);
  85                         mask_bits &= ~(1);
  86                         mask_bits |= flag;
  87                         pci_write_config_dword(entry->dev, pos, mask_bits);
  88                 } else {
  89                         msi_set_enable(entry->dev, !flag);
  90                 }
  91                 break;
  92         case PCI_CAP_ID_MSIX:
  93         {
  94                 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
  95                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
  96                 writel(flag, entry->mask_base + offset);
  97                 break;
  98         }
  99         default:
 100                 BUG();
 101                 break;
 102         }
 103         entry->msi_attrib.masked = !!flag;
 104 }
 105
 106 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 107 {
 108         struct msi_desc *entry = get_irq_msi(irq);
 109         switch(entry->msi_attrib.type) {
 110         case PCI_CAP_ID_MSI:
 111         {
 112                 struct pci_dev *dev = entry->dev;
 113                 int pos = entry->msi_attrib.pos;
 114                 u16 data;
 115
 116                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
 117                                         &msg->address_lo);
 118                 if (entry->msi_attrib.is_64) {
 119                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
 120                                                 &msg->address_hi);
 121                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 122                 } else {
 123                         msg->address_hi = 0;
 124                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 125                 }
 126                 msg->data = data;
 127                 break;
 128         }
 129         case PCI_CAP_ID_MSIX:
 130         {
 131                 void __iomem *base;
 132                 base = entry->mask_base +
 133                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 134
 135                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 136                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 137                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
 138                 break;
 139         }
 140         default:
 141                 BUG();
 142         }
 143 }
 144
 145 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 146 {
 147         struct msi_desc *entry = get_irq_msi(irq);
 148         switch (entry->msi_attrib.type) {
 149         case PCI_CAP_ID_MSI:
 150         {
 151                 struct pci_dev *dev = entry->dev;
 152                 int pos = entry->msi_attrib.pos;
 153
 154                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 155                                         msg->address_lo);
 156                 if (entry->msi_attrib.is_64) {
 157                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 158                                                 msg->address_hi);
 159                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 160                                                 msg->data);
 161                 } else {
 162                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 163                                                 msg->data);
 164                 }
 165                 break;
 166         }
 167         case PCI_CAP_ID_MSIX:
 168         {
 169                 void __iomem *base;
 170                 base = entry->mask_base +
 171                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 172
 173                 writel(msg->address_lo,
 174                         base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 175                 writel(msg->address_hi,
 176                         base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 177                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
 178                 break;
 179         }
 180         default:
 181                 BUG();
 182         }
 183         entry->msg = *msg;
 184 }
 185
 186 void mask_msi_irq(unsigned int irq)
 187 {
 188         msi_set_mask_bit(irq, 1);
 189 }
 190
 191 void unmask_msi_irq(unsigned int irq)
 192 {
 193         msi_set_mask_bit(irq, 0);
 194 }
 195
 196 static int msi_free_irq(struct pci_dev* dev, int irq);
 197
 198 static int msi_init(void)
 199 {
 200         static int status = -ENOMEM;
 201
 202         if (!status)
 203                 return status;
 204
 205         status = msi_cache_init();
 206         if (status < 0) {
 207                 pci_msi_enable = 0;
 208                 printk(KERN_WARNING "PCI: MSI cache init failed\n");
 209                 return status;
 210         }
 211
 212         return status;
 213 }
 214
 215 static struct msi_desc* alloc_msi_entry(void)
 216 {
 217         struct msi_desc *entry;
 218
 219         entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
 220         if (!entry)
 221                 return NULL;
 222
 223         entry->link.tail = entry->link.head = 0;        /* single message */
 224         entry->dev = NULL;
 225
 226         return entry;
 227 }
 228
 229 #ifdef CONFIG_PM
 230 static void __pci_restore_msi_state(struct pci_dev *dev)
 231 {
 232         int pos;
 233         u16 control;
 234         struct msi_desc *entry;
 235
 236         if (!dev->msi_enabled)
 237                 return;
 238
 239         entry = get_irq_msi(dev->irq);
 240         pos = entry->msi_attrib.pos;
 241
 242         pci_intx(dev, 0);               /* disable intx */
 243         msi_set_enable(dev, 0);
 244         write_msi_msg(dev->irq, &entry->msg);
 245         if (entry->msi_attrib.maskbit)
 246                 msi_set_mask_bit(dev->irq, entry->msi_attrib.masked);
 247
 248         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 249         control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 250         if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
 251                 control |= PCI_MSI_FLAGS_ENABLE;
 252         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 253 }
 254
 255 static void __pci_restore_msix_state(struct pci_dev *dev)
 256 {
 257         int pos;
 258         int irq, head, tail = 0;
 259         struct msi_desc *entry;
 260         u16 control;
 261
 262         if (!dev->msix_enabled)
 263                 return;
 264
 265         /* route the table */
 266         pci_intx(dev, 0);               /* disable intx */
 267         msix_set_enable(dev, 0);
 268         irq = head = dev->first_msi_irq;
 269         entry = get_irq_msi(irq);
 270         pos = entry->msi_attrib.pos;
 271         while (head != tail) {
 272                 entry = get_irq_msi(irq);
 273                 write_msi_msg(irq, &entry->msg);
 274                 msi_set_mask_bit(irq, entry->msi_attrib.masked);
 275
 276                 tail = entry->link.tail;
 277                 irq = tail;
 278         }
 279
 280         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 281         control &= ~PCI_MSIX_FLAGS_MASKALL;
 282         control |= PCI_MSIX_FLAGS_ENABLE;
 283         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 284 }
 285
 286 void pci_restore_msi_state(struct pci_dev *dev)
 287 {
 288         __pci_restore_msi_state(dev);
 289         __pci_restore_msix_state(dev);
 290 }
 291 #endif  /* CONFIG_PM */
 292
 293 /**
 294  * msi_capability_init - configure device's MSI capability structure
 295  * @dev: pointer to the pci_dev data structure of MSI device function
 296  *
 297  * Setup the MSI capability structure of device function with a single
 298  * MSI irq, regardless of device function is capable of handling
 299  * multiple messages. A return of zero indicates the successful setup
 300  * of an entry zero with the new MSI irq or non-zero for otherwise.
 301  **/
 302 static int msi_capability_init(struct pci_dev *dev)
 303 {
 304         struct msi_desc *entry;
 305         int pos, irq;
 306         u16 control;
 307
 308         msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */
 309
 310         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 311         pci_read_config_word(dev, msi_control_reg(pos), &control);
 312         /* MSI Entry Initialization */
 313         entry = alloc_msi_entry();
 314         if (!entry)
 315                 return -ENOMEM;
 316
 317         entry->msi_attrib.type = PCI_CAP_ID_MSI;
 318         entry->msi_attrib.is_64 = is_64bit_address(control);
 319         entry->msi_attrib.entry_nr = 0;
 320         entry->msi_attrib.maskbit = is_mask_bit_support(control);
 321         entry->msi_attrib.masked = 1;
 322         entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
 323         entry->msi_attrib.pos = pos;
 324         if (is_mask_bit_support(control)) {
 325                 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
 326                                 is_64bit_address(control));
 327         }
 328         entry->dev = dev;
 329         if (entry->msi_attrib.maskbit) {
 330                 unsigned int maskbits, temp;
 331                 /* All MSIs are unmasked by default, Mask them all */
 332                 pci_read_config_dword(dev,
 333                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 334                         &maskbits);
 335                 temp = (1 << multi_msi_capable(control));
 336                 temp = ((temp - 1) & ~temp);
 337                 maskbits |= temp;
 338                 pci_write_config_dword(dev,
 339                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 340                         maskbits);
 341         }
 342         /* Configure MSI capability structure */
 343         irq = arch_setup_msi_irq(dev, entry);
 344         if (irq < 0) {
 345                 kmem_cache_free(msi_cachep, entry);
 346                 return irq;
 347         }
 348         entry->link.head = irq;
 349         entry->link.tail = irq;
 350         dev->first_msi_irq = irq;
 351         set_irq_msi(irq, entry);
 352
 353         /* Set MSI enabled bits  */
 354         pci_intx(dev, 0);               /* disable intx */
 355         msi_set_enable(dev, 1);
 356         dev->msi_enabled = 1;
 357
 358         dev->irq = irq;
 359         return 0;
 360 }
 361
 362 /**
 363  * msix_capability_init - configure device's MSI-X capability
 364  * @dev: pointer to the pci_dev data structure of MSI-X device function
 365  * @entries: pointer to an array of struct msix_entry entries
 366  * @nvec: number of @entries
 367  *
 368  * Setup the MSI-X capability structure of device function with a
 369  * single MSI-X irq. A return of zero indicates the successful setup of
 370  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 371  **/
 372 static int msix_capability_init(struct pci_dev *dev,
 373                                 struct msix_entry *entries, int nvec)
 374 {
 375         struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
 376         int irq, pos, i, j, nr_entries, temp = 0;
 377         unsigned long phys_addr;
 378         u32 table_offset;
 379         u16 control;
 380         u8 bir;
 381         void __iomem *base;
 382
 383         msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */
 384
 385         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 386         /* Request & Map MSI-X table region */
 387         pci_read_config_word(dev, msi_control_reg(pos), &control);
 388         nr_entries = multi_msix_capable(control);
 389
 390         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 391         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 392         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 393         phys_addr = pci_resource_start (dev, bir) + table_offset;
 394         base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 395         if (base == NULL)
 396                 return -ENOMEM;
 397
 398         /* MSI-X Table Initialization */
 399         for (i = 0; i < nvec; i++) {
 400                 entry = alloc_msi_entry();
 401                 if (!entry)
 402                         break;
 403
 404                 j = entries[i].entry;
 405                 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
 406                 entry->msi_attrib.is_64 = 1;
 407                 entry->msi_attrib.entry_nr = j;
 408                 entry->msi_attrib.maskbit = 1;
 409                 entry->msi_attrib.masked = 1;
 410                 entry->msi_attrib.default_irq = dev->irq;
 411                 entry->msi_attrib.pos = pos;
 412                 entry->dev = dev;
 413                 entry->mask_base = base;
 414
 415                 /* Configure MSI-X capability structure */
 416                 irq = arch_setup_msi_irq(dev, entry);
 417                 if (irq < 0) {
 418                         kmem_cache_free(msi_cachep, entry);
 419                         break;
 420                 }
 421                 entries[i].vector = irq;
 422                 if (!head) {
 423                         entry->link.head = irq;
 424                         entry->link.tail = irq;
 425                         head = entry;
 426                 } else {
 427                         entry->link.head = temp;
 428                         entry->link.tail = tail->link.tail;
 429                         tail->link.tail = irq;
 430                         head->link.head = irq;
 431                 }
 432                 temp = irq;
 433                 tail = entry;
 434
 435                 set_irq_msi(irq, entry);
 436         }
 437         if (i != nvec) {
 438                 int avail = i - 1;
 439                 i--;
 440                 for (; i >= 0; i--) {
 441                         irq = (entries + i)->vector;
 442                         msi_free_irq(dev, irq);
 443                         (entries + i)->vector = 0;
 444                 }
 445                 /* If we had some success report the number of irqs
 446                  * we succeeded in setting up.
 447                  */
 448                 if (avail <= 0)
 449                         avail = -EBUSY;
 450                 return avail;
 451         }
 452         dev->first_msi_irq = entries[0].vector;
 453         /* Set MSI-X enabled bits */
 454         pci_intx(dev, 0);               /* disable intx */
 455         msix_set_enable(dev, 1);
 456         dev->msix_enabled = 1;
 457
 458         return 0;
 459 }
 460
 461 /**
 462  * pci_msi_supported - check whether MSI may be enabled on device
 463  * @dev: pointer to the pci_dev data structure of MSI device function
 464  *
 465  * Look at global flags, the device itself, and its parent busses
 466  * to return 0 if MSI are supported for the device.
 467  **/
 468 static
 469 int pci_msi_supported(struct pci_dev * dev)
 470 {
 471         struct pci_bus *bus;
 472
 473         /* MSI must be globally enabled and supported by the device */
 474         if (!pci_msi_enable || !dev || dev->no_msi)
 475                 return -EINVAL;
 476
 477         /* Any bridge which does NOT route MSI transactions from it's
 478          * secondary bus to it's primary bus must set NO_MSI flag on
 479          * the secondary pci_bus.
 480          * We expect only arch-specific PCI host bus controller driver
 481          * or quirks for specific PCI bridges to be setting NO_MSI.
 482          */
 483         for (bus = dev->bus; bus; bus = bus->parent)
 484                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 485                         return -EINVAL;
 486
 487         return 0;
 488 }
 489
 490 /**
 491  * pci_enable_msi - configure device's MSI capability structure
 492  * @dev: pointer to the pci_dev data structure of MSI device function
 493  *
 494  * Setup the MSI capability structure of device function with
 495  * a single MSI irq upon its software driver call to request for
 496  * MSI mode enabled on its hardware device function. A return of zero
 497  * indicates the successful setup of an entry zero with the new MSI
 498  * irq or non-zero for otherwise.
 499  **/
 500 int pci_enable_msi(struct pci_dev* dev)
 501 {
 502         int pos, status;
 503
 504         if (pci_msi_supported(dev) < 0)
 505                 return -EINVAL;
 506
 507         status = msi_init();
 508         if (status < 0)
 509                 return status;
 510
 511         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 512         if (!pos)
 513                 return -EINVAL;
 514
 515         WARN_ON(!!dev->msi_enabled);
 516
 517         /* Check whether driver already requested for MSI-X irqs */
 518         if (dev->msix_enabled) {
 519                 printk(KERN_INFO "PCI: %s: Can't enable MSI.  "
 520                         "Device already has MSI-X enabled\n",
 521                         pci_name(dev));
 522                 return -EINVAL;
 523         }
 524         status = msi_capability_init(dev);
 525         return status;
 526 }
 527
 528 void pci_disable_msi(struct pci_dev* dev)
 529 {
 530         struct msi_desc *entry;
 531         int default_irq;
 532
 533         if (!pci_msi_enable)
 534                 return;
 535         if (!dev)
 536                 return;
 537
 538         if (!dev->msi_enabled)
 539                 return;
 540
 541         msi_set_enable(dev, 0);
 542         pci_intx(dev, 1);               /* enable intx */
 543         dev->msi_enabled = 0;
 544
 545         entry = get_irq_msi(dev->first_msi_irq);
 546         if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
 547                 return;
 548         }
 549         if (irq_has_action(dev->first_msi_irq)) {
 550                 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
 551                        "free_irq() on MSI irq %d\n",
 552                        pci_name(dev), dev->first_msi_irq);
 553                 BUG_ON(irq_has_action(dev->first_msi_irq));
 554         } else {
 555                 default_irq = entry->msi_attrib.default_irq;
 556                 msi_free_irq(dev, dev->first_msi_irq);
 557
 558                 /* Restore dev->irq to its default pin-assertion irq */
 559                 dev->irq = default_irq;
 560         }
 561         dev->first_msi_irq = 0;
 562 }
 563
 564 static int msi_free_irq(struct pci_dev* dev, int irq)
 565 {
 566         struct msi_desc *entry;
 567         int head, entry_nr, type;
 568         void __iomem *base;
 569
 570         entry = get_irq_msi(irq);
 571         if (!entry || entry->dev != dev) {
 572                 return -EINVAL;
 573         }
 574         type = entry->msi_attrib.type;
 575         entry_nr = entry->msi_attrib.entry_nr;
 576         head = entry->link.head;
 577         base = entry->mask_base;
 578         get_irq_msi(entry->link.head)->link.tail = entry->link.tail;
 579         get_irq_msi(entry->link.tail)->link.head = entry->link.head;
 580
 581         arch_teardown_msi_irq(irq);
 582         kmem_cache_free(msi_cachep, entry);
 583
 584         if (type == PCI_CAP_ID_MSIX) {
 585                 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
 586                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
 587
 588                 if (head == irq)
 589                         iounmap(base);
 590         }
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * pci_enable_msix - configure device's MSI-X capability structure
 597  * @dev: pointer to the pci_dev data structure of MSI-X device function
 598  * @entries: pointer to an array of MSI-X entries
 599  * @nvec: number of MSI-X irqs requested for allocation by device driver
 600  *
 601  * Setup the MSI-X capability structure of device function with the number
 602  * of requested irqs upon its software driver call to request for
 603  * MSI-X mode enabled on its hardware device function. A return of zero
 604  * indicates the successful configuration of MSI-X capability structure
 605  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 606  * Or a return of > 0 indicates that driver request is exceeding the number
 607  * of irqs available. Driver should use the returned value to re-send
 608  * its request.
 609  **/
 610 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 611 {
 612         int status, pos, nr_entries;
 613         int i, j;
 614         u16 control;
 615
 616         if (!entries || pci_msi_supported(dev) < 0)
 617                 return -EINVAL;
 618
 619         status = msi_init();
 620         if (status < 0)
 621                 return status;
 622
 623         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 624         if (!pos)
 625                 return -EINVAL;
 626
 627         pci_read_config_word(dev, msi_control_reg(pos), &control);
 628         nr_entries = multi_msix_capable(control);
 629         if (nvec > nr_entries)
 630                 return -EINVAL;
 631
 632         /* Check for any invalid entries */
 633         for (i = 0; i < nvec; i++) {
 634                 if (entries[i].entry >= nr_entries)
 635                         return -EINVAL;         /* invalid entry */
 636                 for (j = i + 1; j < nvec; j++) {
 637                         if (entries[i].entry == entries[j].entry)
 638                                 return -EINVAL; /* duplicate entry */
 639                 }
 640         }
 641         WARN_ON(!!dev->msix_enabled);
 642
 643         /* Check whether driver already requested for MSI irq */
 644         if (dev->msi_enabled) {
 645                 printk(KERN_INFO "PCI: %s: Can't enable MSI-X.  "
 646                        "Device already has an MSI irq assigned\n",
 647                        pci_name(dev));
 648                 return -EINVAL;
 649         }
 650         status = msix_capability_init(dev, entries, nvec);
 651         return status;
 652 }
 653
 654 void pci_disable_msix(struct pci_dev* dev)
 655 {
 656         int irq, head, tail = 0, warning = 0;
 657
 658         if (!pci_msi_enable)
 659                 return;
 660         if (!dev)
 661                 return;
 662
 663         if (!dev->msix_enabled)
 664                 return;
 665
 666         msix_set_enable(dev, 0);
 667         pci_intx(dev, 1);               /* enable intx */
 668         dev->msix_enabled = 0;
 669
 670         irq = head = dev->first_msi_irq;
 671         while (head != tail) {
 672                 tail = get_irq_msi(irq)->link.tail;
 673                 if (irq_has_action(irq))
 674                         warning = 1;
 675                 else if (irq != head)   /* Release MSI-X irq */
 676                         msi_free_irq(dev, irq);
 677                 irq = tail;
 678         }
 679         msi_free_irq(dev, irq);
 680         if (warning) {
 681                 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
 682                         "free_irq() on all MSI-X irqs\n",
 683                         pci_name(dev));
 684                 BUG_ON(warning > 0);
 685         }
 686         dev->first_msi_irq = 0;
 687 }
 688
 689 /**
 690  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 691  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 692  *
 693  * Being called during hotplug remove, from which the device function
 694  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 695  * allocated for this device function, are reclaimed to unused state,
 696  * which may be used later on.
 697  **/
 698 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
 699 {
 700         if (!pci_msi_enable || !dev)
 701                 return;
 702
 703         if (dev->msi_enabled) {
 704                 if (irq_has_action(dev->first_msi_irq)) {
 705                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 706                                "called without free_irq() on MSI irq %d\n",
 707                                pci_name(dev), dev->first_msi_irq);
 708                         BUG_ON(irq_has_action(dev->first_msi_irq));
 709                 } else /* Release MSI irq assigned to this device */
 710                         msi_free_irq(dev, dev->first_msi_irq);
 711         }
 712         if (dev->msix_enabled) {
 713                 int irq, head, tail = 0, warning = 0;
 714                 void __iomem *base = NULL;
 715
 716                 irq = head = dev->first_msi_irq;
 717                 while (head != tail) {
 718                         tail = get_irq_msi(irq)->link.tail;
 719                         base = get_irq_msi(irq)->mask_base;
 720                         if (irq_has_action(irq))
 721                                 warning = 1;
 722                         else if (irq != head) /* Release MSI-X irq */
 723                                 msi_free_irq(dev, irq);
 724                         irq = tail;
 725                 }
 726                 msi_free_irq(dev, irq);
 727                 if (warning) {
 728                         iounmap(base);
 729                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 730                                "called without free_irq() on all MSI-X irqs\n",
 731                                pci_name(dev));
 732                         BUG_ON(warning > 0);
 733                 }
 734         }
 735 }
 736
 737 void pci_no_msi(void)
 738 {
 739         pci_msi_enable = 0;
 740 }
 741
 742 EXPORT_SYMBOL(pci_enable_msi);
 743 EXPORT_SYMBOL(pci_disable_msi);
 744 EXPORT_SYMBOL(pci_enable_msix);
 745 EXPORT_SYMBOL(pci_disable_msix);