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[PATCH] Remove obsolete PIC mode
[linux-2.6/verdex.git] / arch / x86_64 / kernel / mpparse.c
blob02262450355275e98b6c3b573a84563281ef1e7d
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
25
26 #include <asm/smp.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
32 #include <asm/acpi.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 int acpi_found_madt;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 unsigned char apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47
48 static int mp_current_pci_id = 0;
49 /* I/O APIC entries */
50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51
52 /* # of MP IRQ source entries */
53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54
55 /* MP IRQ source entries */
56 int mp_irq_entries;
57
58 int nr_ioapics;
59 unsigned long mp_lapic_addr = 0;
60
61
62
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_id = -1U;
65 /* Internal processor count */
66 unsigned int num_processors __initdata = 0;
67
68 unsigned disabled_cpus __initdata;
69
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
72
73 /* ACPI MADT entry parsing functions */
74 #ifdef CONFIG_ACPI
75 extern struct acpi_boot_flags acpi_boot;
76 extern int acpi_parse_lapic (acpi_table_entry_header *header);
77 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
78 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
79 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
80 #endif /*CONFIG_ACPI*/
81
82 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
83
84
85 /*
86 * Intel MP BIOS table parsing routines:
87 */
88
89 /*
90 * Checksum an MP configuration block.
91 */
92
93 static int __init mpf_checksum(unsigned char *mp, int len)
94 {
95 int sum = 0;
96
97 while (len--)
98 sum += *mp++;
99
100 return sum & 0xFF;
101 }
102
103 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
104 {
105 int cpu;
106 unsigned char ver;
107 cpumask_t tmp_map;
108
109 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
110 disabled_cpus++;
111 return;
112 }
113
114 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
115 m->mpc_apicid,
116 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
117 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
118 m->mpc_apicver);
119
120 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
121 Dprintk(" Bootup CPU\n");
122 boot_cpu_id = m->mpc_apicid;
123 }
124 if (num_processors >= NR_CPUS) {
125 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
126 " Processor ignored.\n", NR_CPUS);
127 return;
128 }
129
130 num_processors++;
131 cpus_complement(tmp_map, cpu_present_map);
132 cpu = first_cpu(tmp_map);
133
134 #if MAX_APICS < 255
135 if ((int)m->mpc_apicid > MAX_APICS) {
136 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
137 m->mpc_apicid, MAX_APICS);
138 return;
139 }
140 #endif
141 ver = m->mpc_apicver;
142
143 physid_set(m->mpc_apicid, phys_cpu_present_map);
144 /*
145 * Validate version
146 */
147 if (ver == 0x0) {
148 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
149 ver = 0x10;
150 }
151 apic_version[m->mpc_apicid] = ver;
152 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
153 /*
154 * bios_cpu_apicid is required to have processors listed
155 * in same order as logical cpu numbers. Hence the first
156 * entry is BSP, and so on.
157 */
158 cpu = 0;
159 }
160 bios_cpu_apicid[cpu] = m->mpc_apicid;
161 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
162
163 cpu_set(cpu, cpu_possible_map);
164 cpu_set(cpu, cpu_present_map);
165 }
166
167 static void __init MP_bus_info (struct mpc_config_bus *m)
168 {
169 char str[7];
170
171 memcpy(str, m->mpc_bustype, 6);
172 str[6] = 0;
173 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
174
175 if (strncmp(str, "ISA", 3) == 0) {
176 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
177 } else if (strncmp(str, "PCI", 3) == 0) {
178 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
179 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
180 mp_current_pci_id++;
181 } else {
182 printk(KERN_ERR "Unknown bustype %s\n", str);
183 }
184 }
185
186 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
187 {
188 if (!(m->mpc_flags & MPC_APIC_USABLE))
189 return;
190
191 printk("I/O APIC #%d Version %d at 0x%X.\n",
192 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
193 if (nr_ioapics >= MAX_IO_APICS) {
194 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
195 MAX_IO_APICS, nr_ioapics);
196 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
197 }
198 if (!m->mpc_apicaddr) {
199 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
200 " found in MP table, skipping!\n");
201 return;
202 }
203 mp_ioapics[nr_ioapics] = *m;
204 nr_ioapics++;
205 }
206
207 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
208 {
209 mp_irqs [mp_irq_entries] = *m;
210 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
211 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
212 m->mpc_irqtype, m->mpc_irqflag & 3,
213 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
214 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
215 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
216 panic("Max # of irq sources exceeded!!\n");
217 }
218
219 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
220 {
221 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
222 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
223 m->mpc_irqtype, m->mpc_irqflag & 3,
224 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
225 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
226 /*
227 * Well it seems all SMP boards in existence
228 * use ExtINT/LVT1 == LINT0 and
229 * NMI/LVT2 == LINT1 - the following check
230 * will show us if this assumptions is false.
231 * Until then we do not have to add baggage.
232 */
233 if ((m->mpc_irqtype == mp_ExtINT) &&
234 (m->mpc_destapiclint != 0))
235 BUG();
236 if ((m->mpc_irqtype == mp_NMI) &&
237 (m->mpc_destapiclint != 1))
238 BUG();
239 }
240
241 /*
242 * Read/parse the MPC
243 */
244
245 static int __init smp_read_mpc(struct mp_config_table *mpc)
246 {
247 char str[16];
248 int count=sizeof(*mpc);
249 unsigned char *mpt=((unsigned char *)mpc)+count;
250
251 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
252 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
253 mpc->mpc_signature[0],
254 mpc->mpc_signature[1],
255 mpc->mpc_signature[2],
256 mpc->mpc_signature[3]);
257 return 0;
258 }
259 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
260 printk("SMP mptable: checksum error!\n");
261 return 0;
262 }
263 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
264 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
265 mpc->mpc_spec);
266 return 0;
267 }
268 if (!mpc->mpc_lapic) {
269 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
270 return 0;
271 }
272 memcpy(str,mpc->mpc_oem,8);
273 str[8]=0;
274 printk(KERN_INFO "OEM ID: %s ",str);
275
276 memcpy(str,mpc->mpc_productid,12);
277 str[12]=0;
278 printk("Product ID: %s ",str);
279
280 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
281
282 /* save the local APIC address, it might be non-default */
283 if (!acpi_lapic)
284 mp_lapic_addr = mpc->mpc_lapic;
285
286 /*
287 * Now process the configuration blocks.
288 */
289 while (count < mpc->mpc_length) {
290 switch(*mpt) {
291 case MP_PROCESSOR:
292 {
293 struct mpc_config_processor *m=
294 (struct mpc_config_processor *)mpt;
295 if (!acpi_lapic)
296 MP_processor_info(m);
297 mpt += sizeof(*m);
298 count += sizeof(*m);
299 break;
300 }
301 case MP_BUS:
302 {
303 struct mpc_config_bus *m=
304 (struct mpc_config_bus *)mpt;
305 MP_bus_info(m);
306 mpt += sizeof(*m);
307 count += sizeof(*m);
308 break;
309 }
310 case MP_IOAPIC:
311 {
312 struct mpc_config_ioapic *m=
313 (struct mpc_config_ioapic *)mpt;
314 MP_ioapic_info(m);
315 mpt+=sizeof(*m);
316 count+=sizeof(*m);
317 break;
318 }
319 case MP_INTSRC:
320 {
321 struct mpc_config_intsrc *m=
322 (struct mpc_config_intsrc *)mpt;
323
324 MP_intsrc_info(m);
325 mpt+=sizeof(*m);
326 count+=sizeof(*m);
327 break;
328 }
329 case MP_LINTSRC:
330 {
331 struct mpc_config_lintsrc *m=
332 (struct mpc_config_lintsrc *)mpt;
333 MP_lintsrc_info(m);
334 mpt+=sizeof(*m);
335 count+=sizeof(*m);
336 break;
337 }
338 }
339 }
340 clustered_apic_check();
341 if (!num_processors)
342 printk(KERN_ERR "SMP mptable: no processors registered!\n");
343 return num_processors;
344 }
345
346 static int __init ELCR_trigger(unsigned int irq)
347 {
348 unsigned int port;
349
350 port = 0x4d0 + (irq >> 3);
351 return (inb(port) >> (irq & 7)) & 1;
352 }
353
354 static void __init construct_default_ioirq_mptable(int mpc_default_type)
355 {
356 struct mpc_config_intsrc intsrc;
357 int i;
358 int ELCR_fallback = 0;
359
360 intsrc.mpc_type = MP_INTSRC;
361 intsrc.mpc_irqflag = 0; /* conforming */
362 intsrc.mpc_srcbus = 0;
363 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
364
365 intsrc.mpc_irqtype = mp_INT;
366
367 /*
368 * If true, we have an ISA/PCI system with no IRQ entries
369 * in the MP table. To prevent the PCI interrupts from being set up
370 * incorrectly, we try to use the ELCR. The sanity check to see if
371 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
372 * never be level sensitive, so we simply see if the ELCR agrees.
373 * If it does, we assume it's valid.
374 */
375 if (mpc_default_type == 5) {
376 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
377
378 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
379 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
380 else {
381 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
382 ELCR_fallback = 1;
383 }
384 }
385
386 for (i = 0; i < 16; i++) {
387 switch (mpc_default_type) {
388 case 2:
389 if (i == 0 || i == 13)
390 continue; /* IRQ0 & IRQ13 not connected */
391 /* fall through */
392 default:
393 if (i == 2)
394 continue; /* IRQ2 is never connected */
395 }
396
397 if (ELCR_fallback) {
398 /*
399 * If the ELCR indicates a level-sensitive interrupt, we
400 * copy that information over to the MP table in the
401 * irqflag field (level sensitive, active high polarity).
402 */
403 if (ELCR_trigger(i))
404 intsrc.mpc_irqflag = 13;
405 else
406 intsrc.mpc_irqflag = 0;
407 }
408
409 intsrc.mpc_srcbusirq = i;
410 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
411 MP_intsrc_info(&intsrc);
412 }
413
414 intsrc.mpc_irqtype = mp_ExtINT;
415 intsrc.mpc_srcbusirq = 0;
416 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
417 MP_intsrc_info(&intsrc);
418 }
419
420 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
421 {
422 struct mpc_config_processor processor;
423 struct mpc_config_bus bus;
424 struct mpc_config_ioapic ioapic;
425 struct mpc_config_lintsrc lintsrc;
426 int linttypes[2] = { mp_ExtINT, mp_NMI };
427 int i;
428
429 /*
430 * local APIC has default address
431 */
432 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
433
434 /*
435 * 2 CPUs, numbered 0 & 1.
436 */
437 processor.mpc_type = MP_PROCESSOR;
438 /* Either an integrated APIC or a discrete 82489DX. */
439 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
440 processor.mpc_cpuflag = CPU_ENABLED;
441 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
442 (boot_cpu_data.x86_model << 4) |
443 boot_cpu_data.x86_mask;
444 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
445 processor.mpc_reserved[0] = 0;
446 processor.mpc_reserved[1] = 0;
447 for (i = 0; i < 2; i++) {
448 processor.mpc_apicid = i;
449 MP_processor_info(&processor);
450 }
451
452 bus.mpc_type = MP_BUS;
453 bus.mpc_busid = 0;
454 switch (mpc_default_type) {
455 default:
456 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
457 mpc_default_type);
458 /* fall through */
459 case 1:
460 case 5:
461 memcpy(bus.mpc_bustype, "ISA ", 6);
462 break;
463 }
464 MP_bus_info(&bus);
465 if (mpc_default_type > 4) {
466 bus.mpc_busid = 1;
467 memcpy(bus.mpc_bustype, "PCI ", 6);
468 MP_bus_info(&bus);
469 }
470
471 ioapic.mpc_type = MP_IOAPIC;
472 ioapic.mpc_apicid = 2;
473 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
474 ioapic.mpc_flags = MPC_APIC_USABLE;
475 ioapic.mpc_apicaddr = 0xFEC00000;
476 MP_ioapic_info(&ioapic);
477
478 /*
479 * We set up most of the low 16 IO-APIC pins according to MPS rules.
480 */
481 construct_default_ioirq_mptable(mpc_default_type);
482
483 lintsrc.mpc_type = MP_LINTSRC;
484 lintsrc.mpc_irqflag = 0; /* conforming */
485 lintsrc.mpc_srcbusid = 0;
486 lintsrc.mpc_srcbusirq = 0;
487 lintsrc.mpc_destapic = MP_APIC_ALL;
488 for (i = 0; i < 2; i++) {
489 lintsrc.mpc_irqtype = linttypes[i];
490 lintsrc.mpc_destapiclint = i;
491 MP_lintsrc_info(&lintsrc);
492 }
493 }
494
495 static struct intel_mp_floating *mpf_found;
496
497 /*
498 * Scan the memory blocks for an SMP configuration block.
499 */
500 void __init get_smp_config (void)
501 {
502 struct intel_mp_floating *mpf = mpf_found;
503
504 /*
505 * ACPI supports both logical (e.g. Hyper-Threading) and physical
506 * processors, where MPS only supports physical.
507 */
508 if (acpi_lapic && acpi_ioapic) {
509 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
510 return;
511 }
512 else if (acpi_lapic)
513 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
514
515 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
516
517 /*
518 * Now see if we need to read further.
519 */
520 if (mpf->mpf_feature1 != 0) {
521
522 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
523 construct_default_ISA_mptable(mpf->mpf_feature1);
524
525 } else if (mpf->mpf_physptr) {
526
527 /*
528 * Read the physical hardware table. Anything here will
529 * override the defaults.
530 */
531 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
532 smp_found_config = 0;
533 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
534 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
535 return;
536 }
537 /*
538 * If there are no explicit MP IRQ entries, then we are
539 * broken. We set up most of the low 16 IO-APIC pins to
540 * ISA defaults and hope it will work.
541 */
542 if (!mp_irq_entries) {
543 struct mpc_config_bus bus;
544
545 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
546
547 bus.mpc_type = MP_BUS;
548 bus.mpc_busid = 0;
549 memcpy(bus.mpc_bustype, "ISA ", 6);
550 MP_bus_info(&bus);
551
552 construct_default_ioirq_mptable(0);
553 }
554
555 } else
556 BUG();
557
558 printk(KERN_INFO "Processors: %d\n", num_processors);
559 /*
560 * Only use the first configuration found.
561 */
562 }
563
564 static int __init smp_scan_config (unsigned long base, unsigned long length)
565 {
566 extern void __bad_mpf_size(void);
567 unsigned int *bp = phys_to_virt(base);
568 struct intel_mp_floating *mpf;
569
570 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
571 if (sizeof(*mpf) != 16)
572 __bad_mpf_size();
573
574 while (length > 0) {
575 mpf = (struct intel_mp_floating *)bp;
576 if ((*bp == SMP_MAGIC_IDENT) &&
577 (mpf->mpf_length == 1) &&
578 !mpf_checksum((unsigned char *)bp, 16) &&
579 ((mpf->mpf_specification == 1)
580 || (mpf->mpf_specification == 4)) ) {
581
582 smp_found_config = 1;
583 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
584 if (mpf->mpf_physptr)
585 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
586 mpf_found = mpf;
587 return 1;
588 }
589 bp += 4;
590 length -= 16;
591 }
592 return 0;
593 }
594
595 void __init find_intel_smp (void)
596 {
597 unsigned int address;
598
599 /*
600 * FIXME: Linux assumes you have 640K of base ram..
601 * this continues the error...
602 *
603 * 1) Scan the bottom 1K for a signature
604 * 2) Scan the top 1K of base RAM
605 * 3) Scan the 64K of bios
606 */
607 if (smp_scan_config(0x0,0x400) ||
608 smp_scan_config(639*0x400,0x400) ||
609 smp_scan_config(0xF0000,0x10000))
610 return;
611 /*
612 * If it is an SMP machine we should know now.
613 *
614 * there is a real-mode segmented pointer pointing to the
615 * 4K EBDA area at 0x40E, calculate and scan it here.
616 *
617 * NOTE! There are Linux loaders that will corrupt the EBDA
618 * area, and as such this kind of SMP config may be less
619 * trustworthy, simply because the SMP table may have been
620 * stomped on during early boot. These loaders are buggy and
621 * should be fixed.
622 */
623
624 address = *(unsigned short *)phys_to_virt(0x40E);
625 address <<= 4;
626 if (smp_scan_config(address, 0x1000))
627 return;
628
629 /* If we have come this far, we did not find an MP table */
630 printk(KERN_INFO "No mptable found.\n");
631 }
632
633 /*
634 * - Intel MP Configuration Table
635 */
636 void __init find_smp_config (void)
637 {
638 find_intel_smp();
639 }
640
641
642 /* --------------------------------------------------------------------------
643 ACPI-based MP Configuration
644 -------------------------------------------------------------------------- */
645
646 #ifdef CONFIG_ACPI
647
648 void __init mp_register_lapic_address (
649 u64 address)
650 {
651 mp_lapic_addr = (unsigned long) address;
652
653 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
654
655 if (boot_cpu_id == -1U)
656 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
657
658 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
659 }
660
661
662 void __cpuinit mp_register_lapic (
663 u8 id,
664 u8 enabled)
665 {
666 struct mpc_config_processor processor;
667 int boot_cpu = 0;
668
669 if (id >= MAX_APICS) {
670 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
671 id, MAX_APICS);
672 return;
673 }
674
675 if (id == boot_cpu_physical_apicid)
676 boot_cpu = 1;
677
678 processor.mpc_type = MP_PROCESSOR;
679 processor.mpc_apicid = id;
680 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
681 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
682 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
683 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
684 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
685 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
686 processor.mpc_reserved[0] = 0;
687 processor.mpc_reserved[1] = 0;
688
689 MP_processor_info(&processor);
690 }
691
692 #define MP_ISA_BUS 0
693 #define MP_MAX_IOAPIC_PIN 127
694
695 static struct mp_ioapic_routing {
696 int apic_id;
697 int gsi_start;
698 int gsi_end;
699 u32 pin_programmed[4];
700 } mp_ioapic_routing[MAX_IO_APICS];
701
702
703 static int mp_find_ioapic (
704 int gsi)
705 {
706 int i = 0;
707
708 /* Find the IOAPIC that manages this GSI. */
709 for (i = 0; i < nr_ioapics; i++) {
710 if ((gsi >= mp_ioapic_routing[i].gsi_start)
711 && (gsi <= mp_ioapic_routing[i].gsi_end))
712 return i;
713 }
714
715 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
716
717 return -1;
718 }
719
720
721 void __init mp_register_ioapic (
722 u8 id,
723 u32 address,
724 u32 gsi_base)
725 {
726 int idx = 0;
727
728 if (nr_ioapics >= MAX_IO_APICS) {
729 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
730 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
731 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
732 }
733 if (!address) {
734 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
735 " found in MADT table, skipping!\n");
736 return;
737 }
738
739 idx = nr_ioapics++;
740
741 mp_ioapics[idx].mpc_type = MP_IOAPIC;
742 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
743 mp_ioapics[idx].mpc_apicaddr = address;
744
745 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
746 mp_ioapics[idx].mpc_apicid = id;
747 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
748
749 /*
750 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
751 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
752 */
753 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
754 mp_ioapic_routing[idx].gsi_start = gsi_base;
755 mp_ioapic_routing[idx].gsi_end = gsi_base +
756 io_apic_get_redir_entries(idx);
757
758 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
759 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
760 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
761 mp_ioapic_routing[idx].gsi_start,
762 mp_ioapic_routing[idx].gsi_end);
763
764 return;
765 }
766
767
768 void __init mp_override_legacy_irq (
769 u8 bus_irq,
770 u8 polarity,
771 u8 trigger,
772 u32 gsi)
773 {
774 struct mpc_config_intsrc intsrc;
775 int ioapic = -1;
776 int pin = -1;
777
778 /*
779 * Convert 'gsi' to 'ioapic.pin'.
780 */
781 ioapic = mp_find_ioapic(gsi);
782 if (ioapic < 0)
783 return;
784 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
785
786 /*
787 * TBD: This check is for faulty timer entries, where the override
788 * erroneously sets the trigger to level, resulting in a HUGE
789 * increase of timer interrupts!
790 */
791 if ((bus_irq == 0) && (trigger == 3))
792 trigger = 1;
793
794 intsrc.mpc_type = MP_INTSRC;
795 intsrc.mpc_irqtype = mp_INT;
796 intsrc.mpc_irqflag = (trigger << 2) | polarity;
797 intsrc.mpc_srcbus = MP_ISA_BUS;
798 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
799 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
800 intsrc.mpc_dstirq = pin; /* INTIN# */
801
802 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
803 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
804 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
805 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
806
807 mp_irqs[mp_irq_entries] = intsrc;
808 if (++mp_irq_entries == MAX_IRQ_SOURCES)
809 panic("Max # of irq sources exceeded!\n");
810
811 return;
812 }
813
814
815 void __init mp_config_acpi_legacy_irqs (void)
816 {
817 struct mpc_config_intsrc intsrc;
818 int i = 0;
819 int ioapic = -1;
820
821 /*
822 * Fabricate the legacy ISA bus (bus #31).
823 */
824 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
825 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
826
827 /*
828 * Locate the IOAPIC that manages the ISA IRQs (0-15).
829 */
830 ioapic = mp_find_ioapic(0);
831 if (ioapic < 0)
832 return;
833
834 intsrc.mpc_type = MP_INTSRC;
835 intsrc.mpc_irqflag = 0; /* Conforming */
836 intsrc.mpc_srcbus = MP_ISA_BUS;
837 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
838
839 /*
840 * Use the default configuration for the IRQs 0-15. Unless
841 * overridden by (MADT) interrupt source override entries.
842 */
843 for (i = 0; i < 16; i++) {
844 int idx;
845
846 for (idx = 0; idx < mp_irq_entries; idx++) {
847 struct mpc_config_intsrc *irq = mp_irqs + idx;
848
849 /* Do we already have a mapping for this ISA IRQ? */
850 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
851 break;
852
853 /* Do we already have a mapping for this IOAPIC pin */
854 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
855 (irq->mpc_dstirq == i))
856 break;
857 }
858
859 if (idx != mp_irq_entries) {
860 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
861 continue; /* IRQ already used */
862 }
863
864 intsrc.mpc_irqtype = mp_INT;
865 intsrc.mpc_srcbusirq = i; /* Identity mapped */
866 intsrc.mpc_dstirq = i;
867
868 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
869 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
870 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
871 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
872 intsrc.mpc_dstirq);
873
874 mp_irqs[mp_irq_entries] = intsrc;
875 if (++mp_irq_entries == MAX_IRQ_SOURCES)
876 panic("Max # of irq sources exceeded!\n");
877 }
878
879 return;
880 }
881
882 #define MAX_GSI_NUM 4096
883
884 int mp_register_gsi(u32 gsi, int triggering, int polarity)
885 {
886 int ioapic = -1;
887 int ioapic_pin = 0;
888 int idx, bit = 0;
889 static int pci_irq = 16;
890 /*
891 * Mapping between Global System Interrupts, which
892 * represent all possible interrupts, to the IRQs
893 * assigned to actual devices.
894 */
895 static int gsi_to_irq[MAX_GSI_NUM];
896
897 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
898 return gsi;
899
900 /* Don't set up the ACPI SCI because it's already set up */
901 if (acpi_fadt.sci_int == gsi)
902 return gsi;
903
904 ioapic = mp_find_ioapic(gsi);
905 if (ioapic < 0) {
906 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
907 return gsi;
908 }
909
910 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
911
912 /*
913 * Avoid pin reprogramming. PRTs typically include entries
914 * with redundant pin->gsi mappings (but unique PCI devices);
915 * we only program the IOAPIC on the first.
916 */
917 bit = ioapic_pin % 32;
918 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
919 if (idx > 3) {
920 printk(KERN_ERR "Invalid reference to IOAPIC pin "
921 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
922 ioapic_pin);
923 return gsi;
924 }
925 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
926 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
927 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
928 return gsi_to_irq[gsi];
929 }
930
931 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
932
933 if (triggering == ACPI_LEVEL_SENSITIVE) {
934 /*
935 * For PCI devices assign IRQs in order, avoiding gaps
936 * due to unused I/O APIC pins.
937 */
938 int irq = gsi;
939 if (gsi < MAX_GSI_NUM) {
940 /*
941 * Retain the VIA chipset work-around (gsi > 15), but
942 * avoid a problem where the 8254 timer (IRQ0) is setup
943 * via an override (so it's not on pin 0 of the ioapic),
944 * and at the same time, the pin 0 interrupt is a PCI
945 * type. The gsi > 15 test could cause these two pins
946 * to be shared as IRQ0, and they are not shareable.
947 * So test for this condition, and if necessary, avoid
948 * the pin collision.
949 */
950 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
951 gsi = pci_irq++;
952 /*
953 * Don't assign IRQ used by ACPI SCI
954 */
955 if (gsi == acpi_fadt.sci_int)
956 gsi = pci_irq++;
957 gsi_to_irq[irq] = gsi;
958 } else {
959 printk(KERN_ERR "GSI %u is too high\n", gsi);
960 return gsi;
961 }
962 }
963
964 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
965 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
966 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
967 return gsi;
968 }
969
970 #endif /*CONFIG_ACPI*/
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